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1 266 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Debug Unit                                         ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Basic OR1200 debug unit.                                    ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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//
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// Debug unit
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//
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module du(
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        // RISC Internal Interface
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        clk, rst,
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        dclsu_lsuop, icfetch_op, ex_freeze, branch_op,
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        du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
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        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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        // External Debug Interface
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        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
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);
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parameter dw = `OPERAND_WIDTH;
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parameter aw = `OPERAND_WIDTH;
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//
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// I/O
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//
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//
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// RISC Internal Interface
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//
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input                           clk;            // Clock
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input                           rst;            // Reset
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input   [`LSUOP_WIDTH-1:0]       dclsu_lsuop;    // LSU status
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input   [`FETCHOP_WIDTH-1:0]     icfetch_op;     // IFETCH unit status
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input                           ex_freeze;      // EX stage freeze
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input   [`BRANCHOP_WIDTH-1:0]    branch_op;      // Branch op
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output                          du_stall;       // Debug Unit Stall
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output  [aw-1:0]         du_addr;        // Debug Unit Address
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input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
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output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
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output                          du_read;        // Debug Unit Read Enable
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output                          du_write;       // Debug Unit Write Enable
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input   [`EXCEPT_WIDTH-1:0]      du_except;      // Exception started
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input                           spr_cs;         // SPR Chip Select
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input                           spr_write;      // SPR Read/Write
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input   [aw-1:0]         spr_addr;       // SPR Address
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input   [dw-1:0]         spr_dat_i;      // SPR Data Input
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output  [dw-1:0]         spr_dat_o;      // SPR Data Output
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//
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// External Debug Interface
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//
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input                           dbg_stall_i;    // External Stall Input
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input   [dw-1:0]         dbg_dat_i;      // External Data Input
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input   [aw-1:0]         dbg_adr_i;      // External Address Input
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input   [2:0]                    dbg_op_i;       // External Operation Select Input
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input                           dbg_ewt_i;      // External Watchpoint Trigger Input
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output  [3:0]                    dbg_lss_o;      // External Load/Store Unit Status
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output  [1:0]                    dbg_is_o;       // External Insn Fetch Status
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output  [10:0]                   dbg_wp_o;       // Watchpoints Outputs
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output                          dbg_bp_o;       // Breakpoint Output
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output  [dw-1:0]         dbg_dat_o;      // External Data Output
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//
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// Some connections go directly from the CPU through DU to Debug I/F
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//
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assign dbg_lss_o = dclsu_lsuop;
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assign dbg_is_o = icfetch_op;
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assign dbg_wp_o = 11'b000_0000_0000;
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assign dbg_dat_o = du_dat_i;
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//
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// Some connections go directly from Debug I/F through DU to the CPU
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//
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assign du_stall = dbg_stall_i;
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assign du_addr = dbg_adr_i;
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assign du_dat_o = dbg_dat_i;
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assign du_read = (dbg_op_i == `DU_OP_READSPR);
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assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
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`ifdef DU_IMPLEMENTED
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//
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// Debug Mode Register 1 (only ST and BT implemented)
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//
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`ifdef DU_DMR1
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reg     [23:22]                 dmr1;           // DMR1 implemented (ST & BT)
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`else
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wire    [23:22]                 dmr1;           // DMR1 not implemented
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`endif
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//
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// Debug Mode Register 2 (not implemented)
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//
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`ifdef DU_DMR2
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wire    [31:0]                   dmr2;           // DMR not implemented
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`endif
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//
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// Debug Stop Register
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//
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`ifdef DU_DSR
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reg     [13:0]                   dsr;            // DSR implemented
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`else
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wire    [13:0]                   dsr;            // DSR not implemented
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`endif
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//
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// Debug Reason Register
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//
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`ifdef DU_DRR
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reg     [13:0]                   drr;            // DRR implemented
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reg     [13:0]                   except_unmasked;
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`else
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wire    [13:0]                   drr;            // DRR not implemented
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`endif
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//
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// Internal wires
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//
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wire    [13:0]                   except_masked;
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wire                            dmr1_sel;       // DMR1 select
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wire                            dsr_sel;        // DSR select
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wire                            drr_sel;        // DRR select
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reg                             dbg_bp_r;
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`ifdef DU_READREGS
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reg     [31:0]                   spr_dat_o;
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`endif
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//
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// DU registers address decoder
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//
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`ifdef DU_DMR1
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assign dmr1_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DMR1));
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`endif
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`ifdef DU_DSR
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assign dsr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DSR));
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`endif
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`ifdef DU_DRR
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assign drr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DRR));
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`endif
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//
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// Decode started exception
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//
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always @(du_except)
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        case (du_except)
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                4'he: except_unmasked = 14'b10_0000_0000_0000;
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                4'hd: except_unmasked = 14'b01_0000_0000_0000;
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                4'hc: except_unmasked = 14'b00_1000_0000_0000;
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                4'hb: except_unmasked = 14'b00_0100_0000_0000;
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                4'ha: except_unmasked = 14'b00_0010_0000_0000;
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                4'h9: except_unmasked = 14'b00_0001_0000_0000;
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                4'h8: except_unmasked = 14'b00_0000_1000_0000;
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                4'h7: except_unmasked = 14'b00_0000_0100_0000;
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                4'h6: except_unmasked = 14'b00_0000_0010_0000;
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                4'h5: except_unmasked = 14'b00_0000_0001_0000;
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                4'h4: except_unmasked = 14'b00_0000_0000_1000;
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                4'h3: except_unmasked = 14'b00_0000_0000_0100;
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                4'h2: except_unmasked = 14'b00_0000_0000_0010;
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                4'h1: except_unmasked = 14'b00_0000_0000_0001;
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                default: except_unmasked = 14'b00_0000_0000_0000;
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        endcase
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//
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// Get only 'stop' exceptions
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//
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assign except_masked = dsr & except_unmasked;
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//
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// dbg_bp_o is registered
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//
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assign dbg_bp_o = dbg_bp_r;
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//
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// Breakpoint activation register
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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                dbg_bp_r <= #1 1'b0;
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        else
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                dbg_bp_r <= |except_masked
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`ifdef DU_DMR1_ST
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                        | ~ex_freeze & dmr1[`DU_DMR1_ST]
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`endif
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`ifdef DU_DMR1_BT
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                        | ~ex_freeze & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT]
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`endif
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                        ;
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//
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// Write to DMR1
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//
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`ifdef DU_DMR1
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always @(posedge clk or posedge rst)
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        if (rst)
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                dmr1 <= 2'b00;
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        else if (dmr1_sel && spr_write)
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                dmr1 <= #1 spr_dat_i[23:22];
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`else
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assign dmr1 = 2'b00;
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`endif
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//
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// DMR2 bits tied to zero
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//
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`ifdef DU_DMR2
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assign dmr2 = 32'h0000_0000;
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`endif
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//
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// Write to DSR
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//
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`ifdef DU_DSR
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always @(posedge clk or posedge rst)
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        if (rst)
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                dsr <= 14'b0;
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        else if (dsr_sel && spr_write)
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                dsr <= #1 spr_dat_i[13:0];
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`else
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assign dsr = 14'b0;
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`endif
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//
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// Write to DRR
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//
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`ifdef DU_DRR
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always @(posedge clk or posedge rst)
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        if (rst)
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                drr <= 14'b0;
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        else if (drr_sel && spr_write)
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                drr <= #1 spr_dat_i[13:0];
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        else
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                drr <= #1 drr | except_masked;
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`else
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assign drr = 14'b0;
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`endif
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//
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// Read DU registers
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//
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`ifdef DU_READREGS
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always @(spr_addr or dsr or drr)
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        case (spr_addr[`SPROFS_BITS])
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`ifdef DU_DMR1
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                `DU_OFS_DMR1:
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                        spr_dat_o = {8'b0, dmr1, 22'b0};
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`endif
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`ifdef DU_DMR2
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                `DU_OFS_DMR2:
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                        spr_dat_o = dmr2;
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`endif
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`ifdef DU_DSR
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                `DU_OFS_DSR:
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                        spr_dat_o = {18'b0, dsr};
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`endif
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`ifdef DU_DRR
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                `DU_OFS_DRR:
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                        spr_dat_o = {18'b0, drr};
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`endif
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                default:
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                        spr_dat_o = 32'h0000_0000;
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        endcase
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`endif
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`else
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//
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// When DU is not implemented, drive all outputs as would when DU is disabled
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//
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assign dbg_bp_o = 1'b0;
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//
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// Read DU registers
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//
326
`ifdef DU_READREGS
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assign spr_dat_o = 32'h0000_0000;
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`ifdef DU_UNUSED_ZERO
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`endif
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`endif
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`endif
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endmodule

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