OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [generic_dpram_32x32.v] - Blame information for rev 266

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 266 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Generic Double-Port Synchronous RAM                         ////
4
////                                                              ////
5
////  This file is part of memory library available from          ////
6
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  This block is a wrapper with common double-port             ////
10
////  synchronous memory interface for different                  ////
11
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12
////  interface it also provides behavioral model of generic      ////
13
////  double-port synchronous RAM.                                ////
14
////  It should be used in all OPENCORES designs that want to be  ////
15
////  portable accross different target technologies and          ////
16
////  independent of target memory.                               ////
17
////                                                              ////
18
////  Supported ASIC RAMs are:                                    ////
19
////  - Artisan Double-Port Sync RAM                              ////
20
////  - Avant! Two-Port Sync RAM (*)                              ////
21
////  - Virage 2-port Sync RAM                                    ////
22
////                                                              ////
23
////  Supported FPGA RAMs are:                                    ////
24
////  - Xilinx Virtex RAMB4_S16_S16                               ////
25
////                                                              ////
26
////  To Do:                                                      ////
27
////   - fix Avant!                                               ////
28
////   - xilinx rams need external tri-state logic                ////
29
////   - add additional RAMs (Altera, VS etc)                     ////
30
////                                                              ////
31
////  Author(s):                                                  ////
32
////      - Damjan Lampret, lampret@opencores.org                 ////
33
////                                                              ////
34
//////////////////////////////////////////////////////////////////////
35
////                                                              ////
36
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
37
////                                                              ////
38
//// This source file may be used and distributed without         ////
39
//// restriction provided that this copyright statement is not    ////
40
//// removed from the file and that any derivative work contains  ////
41
//// the original copyright notice and the associated disclaimer. ////
42
////                                                              ////
43
//// This source file is free software; you can redistribute it   ////
44
//// and/or modify it under the terms of the GNU Lesser General   ////
45
//// Public License as published by the Free Software Foundation; ////
46
//// either version 2.1 of the License, or (at your option) any   ////
47
//// later version.                                               ////
48
////                                                              ////
49
//// This source is distributed in the hope that it will be       ////
50
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
51
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
52
//// PURPOSE.  See the GNU Lesser General Public License for more ////
53
//// details.                                                     ////
54
////                                                              ////
55
//// You should have received a copy of the GNU Lesser General    ////
56
//// Public License along with this source; if not, download it   ////
57
//// from http://www.opencores.org/lgpl.shtml                     ////
58
////                                                              ////
59
//////////////////////////////////////////////////////////////////////
60
//
61
// CVS Revision History
62
//
63
// $Log: not supported by cvs2svn $
64
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
65
// no message
66
//
67
// Revision 1.1  2001/08/09 13:39:33  lampret
68
// Major clean-up.
69
//
70
// Revision 1.2  2001/07/30 05:38:02  lampret
71
// Adding empty directories required by HDL coding guidelines
72
//
73
//
74
 
75
// synopsys translate_off
76
`include "timescale.v"
77
// synopsys translate_on
78
`include "defines.v"
79
 
80
module generic_dpram_32x32(
81
        // Generic synchronous double-port RAM interface
82
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
83
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
84
);
85
 
86
//
87
// Default address and data buses width
88
//
89
parameter aw = 5;
90
parameter dw = 32;
91
 
92
//
93
// Generic synchronous double-port RAM interface
94
//
95
input                   clk_a;  // Clock
96
input                   rst_a;  // Reset
97
input                   ce_a;   // Chip enable input
98
input                   oe_a;   // Output enable input
99
input   [aw-1:0] addr_a; // address bus inputs
100
output  [dw-1:0] do_a;   // output data bus
101
input                   clk_b;  // Clock
102
input                   rst_b;  // Reset
103
input                   ce_b;   // Chip enable input
104
input                   we_b;   // Write enable input
105
input   [aw-1:0] addr_b; // address bus inputs
106
input   [dw-1:0] di_b;   // input data bus
107
 
108
//
109
// Internal wires and registers
110
//
111
 
112
`ifdef ARTISAN_SDP
113
 
114
//
115
// Instantiation of ASIC memory:
116
//
117
// Artisan Synchronous Double-Port RAM (ra2sh)
118
//
119
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
120
        .qa(do_a),
121
        .clka(clk_a),
122
        .cena(~ce_a),
123
        .wena(1'b1),
124
        .aa(addr_a),
125
        .da(32'h00000000),
126
        .oena(~oe_a),
127
        .qb(),
128
        .clkb(clk_b),
129
        .cenb(~ce_b),
130
        .wenb(~we_b),
131
        .ab(addr_b),
132
        .db(di_b),
133
        .oenb(1'b1)
134
);
135
 
136
`else
137
 
138
`ifdef AVANT_ATP
139
 
140
//
141
// Instantiation of ASIC memory:
142
//
143
// Avant! Asynchronous Two-Port RAM
144
//
145
avant_atp avant_atp(
146
        .web(~we),
147
        .reb(),
148
        .oeb(~oe),
149
        .rcsb(),
150
        .wcsb(),
151
        .ra(addr),
152
        .wa(addr),
153
        .di(di),
154
        .do(do)
155
);
156
 
157
`else
158
 
159
`ifdef VIRAGE_STP
160
 
161
//
162
// Instantiation of ASIC memory:
163
//
164
// Virage Synchronous 2-port R/W RAM
165
//
166
virage_stp virage_stp(
167
        .QA(do_a),
168
        .QB(),
169
 
170
        .ADRA(addr_a),
171
        .DA(32'h00000000),
172
        .WEA(1'b0),
173
        .OEA(oe_a),
174
        .MEA(ce_a),
175
        .CLKA(clk_a),
176
 
177
        .ADRB(addr_b),
178
        .DB(di_b),
179
        .WEB(we_b),
180
        .OEB(1'b1),
181
        .MEB(ce_b),
182
        .CLKB(clk_b)
183
);
184
 
185
`else
186
 
187
`ifdef XILINX_RAM32X1D
188
 
189
//
190
// Instantiation of FPGA memory:
191
//
192
// Virtex/Spartan2
193
//
194
 
195
//
196
// Block 0
197
//
198
xcv_ram32x8d xcv_ram32x8d_0 (
199
        .DPO(do_a[7:0]),
200
        .SPO(),
201
        .A(addr_b),
202
        .D(di_b[7:0]),
203
        .DPRA(addr_a),
204
        .WCLK(clk_b),
205
        .WE(we_b)
206
);
207
 
208
//
209
// Block 1
210
//
211
xcv_ram32x8d xcv_ram32x8d_1 (
212
        .DPO(do_a[15:8]),
213
        .SPO(),
214
        .A(addr_b),
215
        .D(di_b[15:8]),
216
        .DPRA(addr_a),
217
        .WCLK(clk_b),
218
        .WE(we_b)
219
);
220
 
221
 
222
//
223
// Block 2
224
//
225
xcv_ram32x8d xcv_ram32x8d_2 (
226
        .DPO(do_a[23:16]),
227
        .SPO(),
228
        .A(addr_b),
229
        .D(di_b[23:16]),
230
        .DPRA(addr_a),
231
        .WCLK(clk_b),
232
        .WE(we_b)
233
);
234
 
235
//
236
// Block 3
237
//
238
xcv_ram32x8d xcv_ram32x8d_3 (
239
        .DPO(do_a[31:24]),
240
        .SPO(),
241
        .A(addr_b),
242
        .D(di_b[31:24]),
243
        .DPRA(addr_a),
244
        .WCLK(clk_b),
245
        .WE(we_b)
246
);
247
 
248
`else
249
 
250
`ifdef XILINX_RAMB4
251
 
252
//
253
// Instantiation of FPGA memory:
254
//
255
// Virtex/Spartan2
256
//
257
 
258
//
259
// Block 0
260
//
261
RAMB4_S16_S16 ramb4_s16_0(
262
        .CLKA(clk_a),
263
        .RSTA(rst_a),
264
        .ADDRA({3'b000, addr_a}),
265
        .DIA(16'h0000),
266
        .ENA(ce_a),
267
        .WEA(1'b0),
268
        .DOA(do_a[15:0]),
269
 
270
        .CLKB(clk_b),
271
        .RSTB(rst_b),
272
        .ADDRB({3'b000, addr_b}),
273
        .DIB(di_b[15:0]),
274
        .ENB(ce_b),
275
        .WEB(we_b),
276
        .DOB()
277
);
278
 
279
//
280
// Block 1
281
//
282
RAMB4_S16_S16 ramb4_s16_1(
283
        .CLKA(clk_a),
284
        .RSTA(rst_a),
285
        .ADDRA({3'b000, addr_a}),
286
        .DIA(16'h0000),
287
        .ENA(ce_a),
288
        .WEA(1'b0),
289
        .DOA(do_a[31:16]),
290
 
291
        .CLKB(clk_b),
292
        .RSTB(rst_b),
293
        .ADDRB({3'b000, addr_b}),
294
        .DIB(di_b[31:16]),
295
        .ENB(ce_b),
296
        .WEB(we_b),
297
        .DOB()
298
);
299
 
300
`else
301
 
302
//
303
// Generic double-port synchronous RAM model
304
//
305
 
306
//
307
// Generic RAM's registers and wires
308
//
309
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
310
reg     [dw-1:0] do_reg;                 // RAM data output register
311
 
312
//
313
// Data output drivers
314
//
315
assign do_a = (oe_a) ? do_reg : {dw{1'bz}};
316
 
317
//
318
// RAM read
319
//
320
always @(posedge clk_a)
321
        if (ce_a)
322
                do_reg <= #1 mem[addr_a];
323
 
324
//
325
// RAM write
326
//
327
always @(posedge clk_b)
328
        if (ce_b && we_b)
329
                mem[addr_b] <= #1 di_b;
330
 
331
`endif  // !XILINX_RAMB4_S16_S16
332
`endif  // !XILINX_RAM32X1D
333
`endif  // !VIRAGE_STP
334
`endif  // !AVANT_ATP
335
`endif  // !ARTISAN_SDP
336
 
337
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.