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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Generic Single-Port Synchronous RAM                         ////

////                                                              ////

////  This file is part of memory library available from          ////

////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////

////                                                              ////

////  Description                                                 ////

////  This block is a wrapper with common single-port             ////

////  synchronous memory interface for different                  ////

////  types of ASIC and FPGA RAMs. Beside universal memory        ////

////  interface it also provides behavioral model of generic      ////

////  single-port synchronous RAM.                                ////

////  It should be used in all OPENCORES designs that want to be  ////

////  portable accross different target technologies and          ////

////  independent of target memory.                               ////

////                                                              ////

////  Supported ASIC RAMs are:                                    ////

////  - Artisan Single-Port Sync RAM                              ////

////  - Avant! Two-Port Sync RAM (*)                              ////

////  - Virage Single-Port Sync RAM                               ////

////  - Virtual Silicon Single-Port Sync RAM                      ////

////                                                              ////

////  Supported FPGA RAMs are:                                    ////

////  - Xilinx Virtex RAMB4_S16                                   ////

////                                                              ////

////  To Do:                                                      ////

////   - xilinx rams need external tri-state logic                ////

////   - fix avant! two-port ram                                  ////

////   - add additional RAMs (Altera etc)                         ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.1.1.1  2001/10/06 10:18:36  igorm

// no message

//

// Revision 1.1  2001/08/09 13:39:33  lampret

// Major clean-up.

//

// Revision 1.2  2001/07/30 05:38:02  lampret

// Adding empty directories required by HDL coding guidelines

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "defines.v"

module generic_spram_64x37(

        // Generic synchronous single-port RAM interface

        clk, rst, ce, we, oe, addr, di, do

);

//

// Default address and data buses width

//

parameter aw = 6;

parameter dw = 37;

//

// Generic synchronous single-port RAM interface

//

input                   clk;    // Clock

input                   rst;    // Reset

input                   ce;     // Chip enable input

input                   we;     // Write enable input

input                   oe;     // Output enable input

input   [aw-1:0] addr;   // address bus inputs

input   [dw-1:0] di;     // input data bus

output  [dw-1:0] do;     // output data bus

//

// Internal wires and registers

//

`ifdef ARTISAN_SSP

//

// Instantiation of ASIC memory:

//

// Artisan Synchronous Single-Port RAM (ra1sh)

//

art_hssp_64x37 #(dw, 1<<aw, aw) artisan_ssp(

        .clk(clk),

        .cen(~ce),

        .wen(~we),

        .a(addr),

        .d(di),

        .oen(~oe),

        .q(do)

);

`else

`ifdef AVANT_ATP

//

// Instantiation of ASIC memory:

//

// Avant! Asynchronous Two-Port RAM

//

avant_atp avant_atp(

        .web(~we),

        .reb(),

        .oeb(~oe),

        .rcsb(),

        .wcsb(),

        .ra(addr),

        .wa(addr),

        .di(di),

        .do(do)

);

`else

`ifdef VIRAGE_SSP

//

// Instantiation of ASIC memory:

//

// Virage Synchronous 1-port R/W RAM

//

virage_ssp virage_ssp(

        .clk(clk),

        .adr(addr),

        .d(di),

        .we(we),

        .oe(oe),

        .me(ce),

        .q(do)

);

`else

`ifdef VIRTUALSILICON_SSP

//

// Instantiation of ASIC memory:

//

// Virtual Silicon Single-Port Synchronous SRAM

//

virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(

        .CK(clk),

        .ADR(addr),

        .DI(di),

        .WEN(~we),

        .CEN(~ce),

        .OEN(~oe),

        .DOUT(do)

);

`else

`ifdef XILINX_RAMB4

//

// Instantiation of FPGA memory:

//

// Virtex/Spartan2

//

//

// Block 0

//

RAMB4_S16 ramb4_s16_0(

        .CLK(clk),

        .RST(rst),

        .ADDR({2'b00, addr}),

        .DI(di[15:0]),

        .EN(ce),

        .WE(we),

        .DO(do[15:0])

);

//

// Block 1

//

RAMB4_S16 ramb4_s16_1(

        .CLK(clk),

        .RST(rst),

        .ADDR({2'b00, addr}),

        .DI(di[31:16]),

        .EN(ce),

        .WE(we),

        .DO(do[31:16])

);

//

// Block 2

//

RAMB4_S16 ramb4_s16_2(

        .CLK(clk),

        .RST(rst),

        .ADDR({2'b00, addr}),

        .DI(di[36:32]),

        .EN(ce),

        .WE(we),

        .DO(do[36:32])

);

`else

//

// Generic single-port synchronous RAM model

//

//

// Generic RAM's registers and wires

//

reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content

reg     [dw-1:0] do_reg;                 // RAM data output register

//

// Data output drivers

//

assign do = (oe) ? do_reg : {dw{1'bz}};

//

// RAM read and write

//

always @(posedge clk)

        if (ce && !we)

                do_reg <= #1 mem[addr];

        else if (ce && we)

                mem[addr] <= #1 di;

`endif  // !XILINX_RAMB4_S16

`endif  // !VIRTUALSILICON_SSP

`endif  // !VIRAGE_SSP

`endif  // !AVANT_ATP

`endif  // !ARTISAN_SSP

endmodule