URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [id.v] - Blame information for rev 1765

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction decode                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Majority of instruction decoding is performed here.         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module id(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,
        rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
        wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
        multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
        force_dslot_fetch, id_macrc_op, ex_macrc_op
);
 
//
// I/O
//
input                                   clk;
input                                   rst;
input                                   id_freeze;
input                                   ex_freeze;
input                                   wb_freeze;
input                                   except_flushpipe;
input   [31:0]                           if_insn;
output  [`BRANCHOP_WIDTH-1:0]            branch_op;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addra;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrb;
output  [`ALUOP_WIDTH-1:0]               alu_op;
output  [`SHROTOP_WIDTH-1:0]             shrot_op;
output  [`RFWBOP_WIDTH-1:0]              rfwb_op;
output  [31:0]                           wb_insn;
output  [31:0]                           simm;
output  [31:2]                          branch_addrofs;
output  [31:0]                           lsu_addrofs;
output  [`SEL_WIDTH-1:0]         sel_a;
output  [`SEL_WIDTH-1:0]         sel_b;
output  [`LSUOP_WIDTH-1:0]               lsu_op;
output  [`COMPOP_WIDTH-1:0]              comp_op;
output  [`MULTICYCLE_WIDTH-1:0]          multicycle;
output  [15:0]                           spr_addrimm;
input                                   wbforw_valid;
output                                  sig_syscall;
output                                  sig_trap;
output                                  force_dslot_fetch;
output                                  id_macrc_op;
output                                  ex_macrc_op;
 
//
// Internal wires and regs
//
reg     [`BRANCHOP_WIDTH-1:0]            pre_branch_op;
reg     [`BRANCHOP_WIDTH-1:0]            branch_op;
reg     [`ALUOP_WIDTH-1:0]               alu_op;
reg     [`SHROTOP_WIDTH-1:0]             shrot_op;
reg     [31:0]                           id_insn;
reg     [31:0]                           ex_insn;
reg     [31:0]                           wb_insn;
reg     [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
reg     [`REGFILE_ADDR_WIDTH-1:0]        wb_rfaddrw;
reg     [`RFWBOP_WIDTH-1:0]              rfwb_op;
reg     [31:0]                           lsu_addrofs;
reg     [`SEL_WIDTH-1:0]         sel_a;
reg     [`SEL_WIDTH-1:0]         sel_b;
reg                                     sel_imm;
reg     [`LSUOP_WIDTH-1:0]               lsu_op;
reg     [`COMPOP_WIDTH-1:0]              comp_op;
reg     [`MULTICYCLE_WIDTH-1:0]          multicycle;
reg                                     imm_signextend;
reg     [15:0]                           spr_addrimm;
reg                                     sig_syscall;
reg                                     sig_trap;
wire                                    rst_or_except_flushpipe;
reg                                     ex_macrc_op;
 
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
 
//
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
// instructions
//
assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
 
//
// Sign/Zero extension of immediates
//
assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
 
//
// Sign extension of branch offset
//
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
 
//
// Async reset for most of pipeline flops
//
assign rst_or_except_flushpipe = rst | except_flushpipe;
 
//
// l.macrc in ID stage
//
assign id_macrc_op = (id_insn[31:26] == 6'b00_0110) & id_insn[16];
 
//
// Generation of sel_a
//
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
                sel_a = `SEL_EX_FORW;
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
                sel_a = `SEL_WB_FORW;
        else
                sel_a = `SEL_RF;
 
//
// Generation of sel_b
//
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if (sel_imm)
                sel_b = `SEL_IMM;
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
                sel_b = `SEL_EX_FORW;
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
                sel_b = `SEL_WB_FORW;
        else
                sel_b = `SEL_RF;
 
//
// l.macrc in EX stage
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                ex_macrc_op <= #1 1'b0;
        else if (!ex_freeze & id_freeze)
                ex_macrc_op <= #1 1'b0;
        else if (!ex_freeze)
                ex_macrc_op <= #1 id_macrc_op;
end
 
//
// Decode of spr_addrimm
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                spr_addrimm <= #1 16'h0000;
        else if (!ex_freeze & id_freeze)
                spr_addrimm <= #1 16'h0000;
        else if (!ex_freeze) begin
                case (id_insn[31:26])   // synopsys full_case parallel_case
                        // l.mfspr
                        `OR32_MFSPR:
                                spr_addrimm <= #1 id_insn[15:0];
                        // l.mtspr
                        default:
                                spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
                endcase
        end
end
 
//
// Decode of multicycle
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
    // l.lwz
    `OR32_LWZ:
      multicycle = `TWO_CYCLES;
 
    // l.lbz
    `OR32_LBZ:
      multicycle = `TWO_CYCLES;
 
    // l.lbs
    `OR32_LBS:
      multicycle = `TWO_CYCLES;
 
    // l.lhz
    `OR32_LHZ:
      multicycle = `TWO_CYCLES;
 
    // l.lhs
    `OR32_LHS:
      multicycle = `TWO_CYCLES;
 
    // l.sw
    `OR32_SW:
      multicycle = `TWO_CYCLES;
 
    // l.sb
    `OR32_SB:
      multicycle = `TWO_CYCLES;
 
    // l.sh
    `OR32_SH:
      multicycle = `TWO_CYCLES;
 
    // ALU instructions except the one with immediate
    `OR32_ALU:
      multicycle = id_insn[`ALUMCYC_POS];
 
    // Single cycle instructions
    default: begin
      multicycle = `ONE_CYCLE;
    end
 
  endcase
 
end
 
//
// Decode of imm_signextend
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
        // l.addi
        `OR32_ADDI:
                imm_signextend = `on;
 
        // l.addic
        `OR32_ADDIC:
                imm_signextend = `on;
 
        // l.xori
        `OR32_XORI:
                imm_signextend = `on;
 
        // l.muli
        `OR32_MULI:
                imm_signextend = `on;
 
        // l.maci
        `OR32_MACI:
                imm_signextend = `on;
 
        // SFXX insns with immediate
        `OR32_SFXXI:
                imm_signextend = `on;
 
        // Instructions with no or zero extended immediate
        default: begin
                imm_signextend = `off;
        end
 
endcase
 
end
 
//
// LSU addr offset
//
always @(lsu_op or ex_insn) begin
        lsu_addrofs[10:0] = ex_insn[10:0];
        case(lsu_op)    // synopsys parallel_case full_case
                `LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
                        lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
                default :
                        lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
        endcase
end
 
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
        if (rst)
                rf_addrw <= #1 5'd0;
        else if (!ex_freeze & id_freeze)
                rf_addrw <= #1 5'd00;
        else if (!ex_freeze)
                case (pre_branch_op)    // synopsys parallel_case full_case
                        `BRANCHOP_JR, `BRANCHOP_BAL:
                                rf_addrw <= #1 5'd09;   // link register r9
                        default:
                                rf_addrw <= #1 id_insn[25:21];
                endcase
end
 
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
        if (rst)
                wb_rfaddrw <= #1 5'd0;
        else if (!wb_freeze)
                wb_rfaddrw <= #1 rf_addrw;
end
 
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_insn[31:26] <= #1 `OR32_NOP;
                id_insn[25:0] <= #1 26'd0;
        end
        else if (!id_freeze) begin
                id_insn <= #1 if_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: id_insn <= %h", $time, if_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_insn[31:26] <= #1 `OR32_NOP;
                ex_insn[25:0] <= #1 26'd0;
        end
        else if (!ex_freeze & id_freeze)
                ex_insn <= #1 {`OR32_NOP, 26'h000_4444};
        else if (!ex_freeze) begin
                ex_insn <= #1 id_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_insn <= %h", $time, id_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_insn[31:26] <= #1 `OR32_NOP;
                wb_insn[25:0] <= #1 26'd0;
        end
        else if (!wb_freeze) begin
                wb_insn <= #1 ex_insn;
        end
end
 
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sel_imm <= #1 1'b0;
        else if (!id_freeze) begin
          case (if_insn[31:26])         // synopsys full_case parallel_case
 
            // j.jalr
            `OR32_JALR:
              sel_imm <= #1 `off;
 
            // l.jr
            `OR32_JR:
              sel_imm <= #1 `off;
 
            // l.rfe
            `OR32_RFE:
              sel_imm <= #1 `off;
 
            // l.mfspr
            `OR32_MFSPR:
              sel_imm <= #1 `off;
 
            // l.mtspr
            `OR32_MTSPR:
              sel_imm <= #1 `off;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              sel_imm <= #1 `off;
 
            // l.sw
            `OR32_SW:
              sel_imm <= #1 `off;
 
            // l.sb
            `OR32_SB:
              sel_imm <= #1 `off;
 
            // l.sh
            `OR32_SH:
              sel_imm <= #1 `off;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              sel_imm <= #1 `off;
 
            // SFXX instructions
            `OR32_SFXX:
              sel_imm <= #1 `off;
 
            // l.nop
            `OR32_NOP:
              sel_imm <= #1 `off;
 
            // All instructions with immediates
            default: begin
              sel_imm <= #1 `on;
            end
 
          endcase
 
        end
end
 
 
//
// Decode of alu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                alu_op <= #1 `ALUOP_NOP;
        else if (!ex_freeze & id_freeze)
                alu_op <= #1 `ALUOP_NOP;
        else if (!ex_freeze) begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.j
            `OR32_J:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jal
            `OR32_JAL:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jalr
            `OR32_JALR:
              alu_op <= #1 `ALUOP_OR;
 
            // l.jr
            `OR32_JR:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bnf
            `OR32_BNF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bf
            `OR32_BF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.rfe
            `OR32_RFE:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.movhi
            `OR32_MOVHI:
              alu_op <= #1 `ALUOP_MOVHI;
 
            // l.mfspr
            `OR32_MFSPR:
              alu_op <= #1 `ALUOP_MFSR;
 
            // l.mtspr
            `OR32_MTSPR:
              alu_op <= #1 `ALUOP_MTSR;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.lwz
            `OR32_LWZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbz
            `OR32_LBZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbs
            `OR32_LBS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhz
            `OR32_LHZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhs
            `OR32_LHS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addi
            `OR32_ADDI:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addic
            `OR32_ADDIC:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.andi
            `OR32_ANDI:
              alu_op <= #1 `ALUOP_AND;
 
            // l.ori
            `OR32_ORI:
              alu_op <= #1 `ALUOP_OR;
 
            // l.xori
            `OR32_XORI:
              alu_op <= #1 `ALUOP_XOR;
 
            // l.muli
            `OR32_MULI:
              alu_op <= #1 `ALUOP_MUL;
 
            // l.maci
            `OR32_MACI:
              alu_op <= #1 `ALUOP_MAC;
 
            // Shift and rotate insns with immediate
            `OR32_SH_ROTI:
              alu_op <= #1 `ALUOP_SHROT;
 
            // SFXX insns with immediate
            `OR32_SFXXI:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.sw
            `OR32_SW:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sb
            `OR32_SB:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sh
            `OR32_SH:
              alu_op <= #1 `ALUOP_ADD;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              alu_op <= #1 id_insn[3:0];
 
            // SFXX instructions
            `OR32_SFXX:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.nop
            `OR32_NOP:
              alu_op <= #1 `ALUOP_NOP;
 
            // Illegal and OR1200 unsupported instructions
            default: begin
              alu_op <= #1 `ALUOP_NOP;
`ifdef OR1200_VERBOSE
// synopsys translate_off
              $display("%t: Illegal insn.... insn %h", $time, id_insn);
// synopsys translate_on
`endif
            end
 
          endcase
 
        end
end
 
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!ex_freeze & id_freeze)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!ex_freeze) begin
                shrot_op <= #1 id_insn[`SHROTOP_POS];
        end
end
 
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!ex_freeze & id_freeze)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!ex_freeze) begin
                case (id_insn[31:26])           // synopsys full_case parallel_case
 
                  // j.jal
                  `OR32_JAL:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // j.jalr
                  `OR32_JALR:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // l.movhi
                  `OR32_MOVHI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.mfspr
                  `OR32_MFSPR:
                    rfwb_op <= #1 `RFWBOP_SPRS;
 
                  // l.lwz
                  `OR32_LWZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbz
                  `OR32_LBZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbs
                  `OR32_LBS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhz
                  `OR32_LHZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhs
                  `OR32_LHS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.addi
                  `OR32_ADDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.addic
                  `OR32_ADDIC:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.andi
                  `OR32_ANDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.ori
                  `OR32_ORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.xori
                  `OR32_XORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.muli
                  `OR32_MULI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.maci
                  `OR32_MACI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Shift and rotate insns with immediate
                  `OR32_SH_ROTI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // ALU instructions except the one with immediate
                  `OR32_ALU:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Instructions w/o register-file write-back
                  default: begin
                    rfwb_op <= #1 `RFWBOP_NOP;
                  end
 
                endcase
        end
end
 
//
// Decode of pre_branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                pre_branch_op <= #1 `BRANCHOP_NOP;
        else if (!id_freeze) begin
                case (if_insn[31:26])           // synopsys full_case parallel_case
 
                  // l.j
                  `OR32_J:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jal
                  `OR32_JAL:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jalr
                  `OR32_JALR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.jr
                  `OR32_JR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.bnf
                  `OR32_BNF:
                    pre_branch_op <= #1 `BRANCHOP_BNF;
 
                  // l.bf
                  `OR32_BF:
                    pre_branch_op <= #1 `BRANCHOP_BF;
 
                  // l.rfe
                  `OR32_RFE:
                    pre_branch_op <= #1 `BRANCHOP_RFE;
 
                  // Non branch instructions
                  default: begin
                    pre_branch_op <= #1 `BRANCHOP_NOP;
                  end
                endcase
        end
end
 
//
// Generation of branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!ex_freeze & id_freeze)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!ex_freeze) begin
                branch_op <= #1 pre_branch_op;
        end
end
 
//
// Decode of lsu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!ex_freeze & id_freeze)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!ex_freeze)  begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.lwz
            `OR32_LWZ:
              lsu_op <= #1 `LSUOP_LWZ;
 
            // l.lbz
            `OR32_LBZ:
              lsu_op <= #1 `LSUOP_LBZ;
 
            // l.lbs
            `OR32_LBS:
              lsu_op <= #1 `LSUOP_LBS;
 
            // l.lhz
            `OR32_LHZ:
              lsu_op <= #1 `LSUOP_LHZ;
 
            // l.lhs
            `OR32_LHS:
              lsu_op <= #1 `LSUOP_LHS;
 
            // l.sw
            `OR32_SW:
              lsu_op <= #1 `LSUOP_SW;
 
            // l.sb
            `OR32_SB:
              lsu_op <= #1 `LSUOP_SB;
 
            // l.sh
            `OR32_SH:
              lsu_op <= #1 `LSUOP_SH;
 
            // Non load/store instructions
            default: begin
              lsu_op <= #1 `LSUOP_NOP;
            end
          endcase
        end
end
 
//
// Decode of comp_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                comp_op <= #1 4'd0;
        else if (!ex_freeze & id_freeze)
                comp_op <= #1 4'd0;
        else if (!ex_freeze) begin
                comp_op <= #1 id_insn[24:21];
        end
end
 
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_syscall <= #1 1'b0;
        else if (!ex_freeze & id_freeze)
                sig_syscall <= #1 1'b0;
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                if (id_insn[31:23] == {`OR32_XSYNC, 3'b000})
                        $display("Generating sig_syscall");
// synopsys translate_on
`endif
                sig_syscall <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b000});
        end
end
 
//
// Decode of l.trap
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_trap <= #1 1'b0;
        else if (!ex_freeze & id_freeze)
                sig_trap <= #1 1'b0;
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                if (id_insn[31:23] == {`OR32_XSYNC, 3'b010})
                        $display("Generating sig_trap");
// synopsys translate_on
`endif
                sig_trap <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b010});
        end
end
 
endmodule

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [id.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction decode ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Majority of instruction decoding is performed here. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/13 03:36:20 lampret`
51			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
52			`//`
53			`// Revision 1.1 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`//`
57
58			`include "timescale.v"
59			`include "defines.v"
60
61			`module id(`
62			`// Clock and reset`
63			`clk, rst,`
64
65			`// Internal i/f`
66			`id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,`
67			`rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,`
68			`wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,`
69			`multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,`
70			`force_dslot_fetch, id_macrc_op, ex_macrc_op`
71			`);`
72
73			`//`
74			`// I/O`
75			`//`
76			`input clk;`
77			`input rst;`
78			`input id_freeze;`
79			`input ex_freeze;`
80			`input wb_freeze;`
81			`input except_flushpipe;`
82			`input [31:0] if_insn;`
83			output [`BRANCHOP_WIDTH-1:0] branch_op;
84			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
85			output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
86			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrb;
87			output [`ALUOP_WIDTH-1:0] alu_op;
88			output [`SHROTOP_WIDTH-1:0] shrot_op;
89			output [`RFWBOP_WIDTH-1:0] rfwb_op;
90			`output [31:0] wb_insn;`
91			`output [31:0] simm;`
92			`output [31:2] branch_addrofs;`
93			`output [31:0] lsu_addrofs;`
94			output [`SEL_WIDTH-1:0] sel_a;
95			output [`SEL_WIDTH-1:0] sel_b;
96			output [`LSUOP_WIDTH-1:0] lsu_op;
97			output [`COMPOP_WIDTH-1:0] comp_op;
98			output [`MULTICYCLE_WIDTH-1:0] multicycle;
99			`output [15:0] spr_addrimm;`
100			`input wbforw_valid;`
101			`output sig_syscall;`
102			`output sig_trap;`
103			`output force_dslot_fetch;`
104			`output id_macrc_op;`
105			`output ex_macrc_op;`
106
107			`//`
108			`// Internal wires and regs`
109			`//`
110			reg [`BRANCHOP_WIDTH-1:0] pre_branch_op;
111			reg [`BRANCHOP_WIDTH-1:0] branch_op;
112			reg [`ALUOP_WIDTH-1:0] alu_op;
113			reg [`SHROTOP_WIDTH-1:0] shrot_op;
114			`reg [31:0] id_insn;`
115			`reg [31:0] ex_insn;`
116			`reg [31:0] wb_insn;`
117			reg [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
118			reg [`REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
119			reg [`RFWBOP_WIDTH-1:0] rfwb_op;
120			`reg [31:0] lsu_addrofs;`
121			reg [`SEL_WIDTH-1:0] sel_a;
122			reg [`SEL_WIDTH-1:0] sel_b;
123			`reg sel_imm;`
124			reg [`LSUOP_WIDTH-1:0] lsu_op;
125			reg [`COMPOP_WIDTH-1:0] comp_op;
126			reg [`MULTICYCLE_WIDTH-1:0] multicycle;
127			`reg imm_signextend;`
128			`reg [15:0] spr_addrimm;`
129			`reg sig_syscall;`
130			`reg sig_trap;`
131			`wire rst_or_except_flushpipe;`
132			`reg ex_macrc_op;`
133
134			`//`
135			`// Register file read addresses`
136			`//`
137			`assign rf_addra = if_insn[20:16];`
138			`assign rf_addrb = if_insn[15:11];`
139
140			`//`
141			`// Force fetch of delay slot instruction when jump/branch is preceeded by load/store`
142			`// instructions`
143			`//`
144			`assign force_dslot_fetch = ((\|pre_branch_op) & (\|lsu_op));`
145
146			`//`
147			`// Sign/Zero extension of immediates`
148			`//`
149			assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
150
151			`//`
152			`// Sign extension of branch offset`
153			`//`
154			`assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};`
155
156			`//`
157			`// Async reset for most of pipeline flops`
158			`//`
159			`assign rst_or_except_flushpipe = rst \| except_flushpipe;`
160
161			`//`
162			`// l.macrc in ID stage`
163			`//`
164			`assign id_macrc_op = (id_insn[31:26] == 6'b00_0110) & id_insn[16];`
165
166			`//`
167			`// Generation of sel_a`
168			`//`
169			`always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
170			`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`
171			sel_a = `SEL_EX_FORW;
172			`else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)`
173			sel_a = `SEL_WB_FORW;
174			`else`
175			sel_a = `SEL_RF;
176
177			`//`
178			`// Generation of sel_b`
179			`//`
180			`always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
181			`if (sel_imm)`
182			sel_b = `SEL_IMM;
183			`else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])`
184			sel_b = `SEL_EX_FORW;
185			`else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)`
186			sel_b = `SEL_WB_FORW;
187			`else`
188			sel_b = `SEL_RF;
189
190			`//`
191			`// l.macrc in EX stage`
192			`//`
193			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
194			`if (rst_or_except_flushpipe)`
195			`ex_macrc_op <= #1 1'b0;`
196			`else if (!ex_freeze & id_freeze)`
197			`ex_macrc_op <= #1 1'b0;`
198			`else if (!ex_freeze)`
199			`ex_macrc_op <= #1 id_macrc_op;`
200			`end`
201
202			`//`
203			`// Decode of spr_addrimm`
204			`//`
205			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
206			`if (rst_or_except_flushpipe)`
207			`spr_addrimm <= #1 16'h0000;`
208			`else if (!ex_freeze & id_freeze)`
209			`spr_addrimm <= #1 16'h0000;`
210			`else if (!ex_freeze) begin`
211			`case (id_insn[31:26]) // synopsys full_case parallel_case`
212			`// l.mfspr`
213			`OR32_MFSPR:
214			`spr_addrimm <= #1 id_insn[15:0];`
215			`// l.mtspr`
216			`default:`
217			`spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};`
218			`endcase`
219			`end`
220			`end`
221
222			`//`
223			`// Decode of multicycle`
224			`//`
225			`always @(id_insn) begin`
226			`case (id_insn[31:26]) // synopsys full_case parallel_case`
227
228			`// l.lwz`
229			`OR32_LWZ:
230			multicycle = `TWO_CYCLES;
231
232			`// l.lbz`
233			`OR32_LBZ:
234			multicycle = `TWO_CYCLES;
235
236			`// l.lbs`
237			`OR32_LBS:
238			multicycle = `TWO_CYCLES;
239
240			`// l.lhz`
241			`OR32_LHZ:
242			multicycle = `TWO_CYCLES;
243
244			`// l.lhs`
245			`OR32_LHS:
246			multicycle = `TWO_CYCLES;
247
248			`// l.sw`
249			`OR32_SW:
250			multicycle = `TWO_CYCLES;
251
252			`// l.sb`
253			`OR32_SB:
254			multicycle = `TWO_CYCLES;
255
256			`// l.sh`
257			`OR32_SH:
258			multicycle = `TWO_CYCLES;
259
260			`// ALU instructions except the one with immediate`
261			`OR32_ALU:
262			multicycle = id_insn[`ALUMCYC_POS];
263
264			`// Single cycle instructions`
265			`default: begin`
266			multicycle = `ONE_CYCLE;
267			`end`
268
269			`endcase`
270
271			`end`
272
273			`//`
274			`// Decode of imm_signextend`
275			`//`
276			`always @(id_insn) begin`
277			`case (id_insn[31:26]) // synopsys full_case parallel_case`
278
279			`// l.addi`
280			`OR32_ADDI:
281			imm_signextend = `on;
282
283			`// l.addic`
284			`OR32_ADDIC:
285			imm_signextend = `on;
286
287			`// l.xori`
288			`OR32_XORI:
289			imm_signextend = `on;
290
291			`// l.muli`
292			`OR32_MULI:
293			imm_signextend = `on;
294
295			`// l.maci`
296			`OR32_MACI:
297			imm_signextend = `on;
298
299			`// SFXX insns with immediate`
300			`OR32_SFXXI:
301			imm_signextend = `on;
302
303			`// Instructions with no or zero extended immediate`
304			`default: begin`
305			imm_signextend = `off;
306			`end`
307
308			`endcase`
309
310			`end`
311
312			`//`
313			`// LSU addr offset`
314			`//`
315			`always @(lsu_op or ex_insn) begin`
316			`lsu_addrofs[10:0] = ex_insn[10:0];`
317			`case(lsu_op) // synopsys parallel_case full_case`
318			`LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
319			`lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};`
320			`default :`
321			`lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};`
322			`endcase`
323			`end`
324
325			`//`
326			`// Register file write address`
327			`//`
328			`always @(posedge clk or posedge rst) begin`
329			`if (rst)`
330			`rf_addrw <= #1 5'd0;`
331			`else if (!ex_freeze & id_freeze)`
332			`rf_addrw <= #1 5'd00;`
333			`else if (!ex_freeze)`
334			`case (pre_branch_op) // synopsys parallel_case full_case`
335			`BRANCHOP_JR, `BRANCHOP_BAL:
336			`rf_addrw <= #1 5'd09; // link register r9`
337			`default:`
338			`rf_addrw <= #1 id_insn[25:21];`
339			`endcase`
340			`end`
341
342			`//`
343			`// rf_addrw in wb stage (used in forwarding logic)`
344			`//`
345			`always @(posedge clk or posedge rst) begin`
346			`if (rst)`
347			`wb_rfaddrw <= #1 5'd0;`
348			`else if (!wb_freeze)`
349			`wb_rfaddrw <= #1 rf_addrw;`
350			`end`
351
352			`//`
353			`// Instruction latch in id_insn`
354			`//`
355			`always @(posedge clk or posedge rst) begin`
356			`if (rst) begin`
357			id_insn[31:26] <= #1 `OR32_NOP;
358			`id_insn[25:0] <= #1 26'd0;`
359			`end`
360			`else if (!id_freeze) begin`
361			`id_insn <= #1 if_insn;`
362			`ifdef OR1200_VERBOSE
363			`// synopsys translate_off`
364			`$display("%t: id_insn <= %h", $time, if_insn);`
365			`// synopsys translate_on`
366			`endif
367			`end`
368			`end`
369
370			`//`
371			`// Instruction latch in ex_insn`
372			`//`
373			`always @(posedge clk or posedge rst) begin`
374			`if (rst) begin`
375			ex_insn[31:26] <= #1 `OR32_NOP;
376			`ex_insn[25:0] <= #1 26'd0;`
377			`end`
378			`else if (!ex_freeze & id_freeze)`
379			ex_insn <= #1 {`OR32_NOP, 26'h000_4444};
380			`else if (!ex_freeze) begin`
381			`ex_insn <= #1 id_insn;`
382			`ifdef OR1200_VERBOSE
383			`// synopsys translate_off`
384			`$display("%t: ex_insn <= %h", $time, id_insn);`
385			`// synopsys translate_on`
386			`endif
387			`end`
388			`end`
389
390			`//`
391			`// Instruction latch in wb_insn`
392			`//`
393			`always @(posedge clk or posedge rst) begin`
394			`if (rst) begin`
395			wb_insn[31:26] <= #1 `OR32_NOP;
396			`wb_insn[25:0] <= #1 26'd0;`
397			`end`
398			`else if (!wb_freeze) begin`
399			`wb_insn <= #1 ex_insn;`
400			`end`
401			`end`
402
403			`//`
404			`// Decode of sel_imm`
405			`//`
406			`always @(posedge clk or posedge rst) begin`
407			`if (rst)`
408			`sel_imm <= #1 1'b0;`
409			`else if (!id_freeze) begin`
410			`case (if_insn[31:26]) // synopsys full_case parallel_case`
411
412			`// j.jalr`
413			`OR32_JALR:
414			sel_imm <= #1 `off;
415
416			`// l.jr`
417			`OR32_JR:
418			sel_imm <= #1 `off;
419
420			`// l.rfe`
421			`OR32_RFE:
422			sel_imm <= #1 `off;
423
424			`// l.mfspr`
425			`OR32_MFSPR:
426			sel_imm <= #1 `off;
427
428			`// l.mtspr`
429			`OR32_MTSPR:
430			sel_imm <= #1 `off;
431
432			`// l.sys, l.brk and all three sync insns`
433			`OR32_XSYNC:
434			sel_imm <= #1 `off;
435
436			`// l.sw`
437			`OR32_SW:
438			sel_imm <= #1 `off;
439
440			`// l.sb`
441			`OR32_SB:
442			sel_imm <= #1 `off;
443
444			`// l.sh`
445			`OR32_SH:
446			sel_imm <= #1 `off;
447
448			`// ALU instructions except the one with immediate`
449			`OR32_ALU:
450			sel_imm <= #1 `off;
451
452			`// SFXX instructions`
453			`OR32_SFXX:
454			sel_imm <= #1 `off;
455
456			`// l.nop`
457			`OR32_NOP:
458			sel_imm <= #1 `off;
459
460			`// All instructions with immediates`
461			`default: begin`
462			sel_imm <= #1 `on;
463			`end`
464
465			`endcase`
466
467			`end`
468			`end`
469
470
471			`//`
472			`// Decode of alu_op`
473			`//`
474			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
475			`if (rst_or_except_flushpipe)`
476			alu_op <= #1 `ALUOP_NOP;
477			`else if (!ex_freeze & id_freeze)`
478			alu_op <= #1 `ALUOP_NOP;
479			`else if (!ex_freeze) begin`
480			`case (id_insn[31:26]) // synopsys full_case parallel_case`
481
482			`// l.j`
483			`OR32_J:
484			alu_op <= #1 `ALUOP_IMM;
485
486			`// j.jal`
487			`OR32_JAL:
488			alu_op <= #1 `ALUOP_IMM;
489
490			`// j.jalr`
491			`OR32_JALR:
492			alu_op <= #1 `ALUOP_OR;
493
494			`// l.jr`
495			`OR32_JR:
496			alu_op <= #1 `ALUOP_ADD;
497
498			`// l.bnf`
499			`OR32_BNF:
500			alu_op <= #1 `ALUOP_ADD;
501
502			`// l.bf`
503			`OR32_BF:
504			alu_op <= #1 `ALUOP_ADD;
505
506			`// l.rfe`
507			`OR32_RFE:
508			alu_op <= #1 `ALUOP_NOP;
509
510			`// l.movhi`
511			`OR32_MOVHI:
512			alu_op <= #1 `ALUOP_MOVHI;
513
514			`// l.mfspr`
515			`OR32_MFSPR:
516			alu_op <= #1 `ALUOP_MFSR;
517
518			`// l.mtspr`
519			`OR32_MTSPR:
520			alu_op <= #1 `ALUOP_MTSR;
521
522			`// l.sys, l.brk and all three sync insns`
523			`OR32_XSYNC:
524			alu_op <= #1 `ALUOP_NOP;
525
526			`// l.lwz`
527			`OR32_LWZ:
528			alu_op <= #1 `ALUOP_ADD;
529
530			`// l.lbz`
531			`OR32_LBZ:
532			alu_op <= #1 `ALUOP_ADD;
533
534			`// l.lbs`
535			`OR32_LBS:
536			alu_op <= #1 `ALUOP_ADD;
537
538			`// l.lhz`
539			`OR32_LHZ:
540			alu_op <= #1 `ALUOP_ADD;
541
542			`// l.lhs`
543			`OR32_LHS:
544			alu_op <= #1 `ALUOP_ADD;
545
546			`// l.addi`
547			`OR32_ADDI:
548			alu_op <= #1 `ALUOP_ADD;
549
550			`// l.addic`
551			`OR32_ADDIC:
552			alu_op <= #1 `ALUOP_ADD;
553
554			`// l.andi`
555			`OR32_ANDI:
556			alu_op <= #1 `ALUOP_AND;
557
558			`// l.ori`
559			`OR32_ORI:
560			alu_op <= #1 `ALUOP_OR;
561
562			`// l.xori`
563			`OR32_XORI:
564			alu_op <= #1 `ALUOP_XOR;
565
566			`// l.muli`
567			`OR32_MULI:
568			alu_op <= #1 `ALUOP_MUL;
569
570			`// l.maci`
571			`OR32_MACI:
572			alu_op <= #1 `ALUOP_MAC;
573
574			`// Shift and rotate insns with immediate`
575			`OR32_SH_ROTI:
576			alu_op <= #1 `ALUOP_SHROT;
577
578			`// SFXX insns with immediate`
579			`OR32_SFXXI:
580			alu_op <= #1 `ALUOP_COMP;
581
582			`// l.sw`
583			`OR32_SW:
584			alu_op <= #1 `ALUOP_ADD;
585
586			`// l.sb`
587			`OR32_SB:
588			alu_op <= #1 `ALUOP_ADD;
589
590			`// l.sh`
591			`OR32_SH:
592			alu_op <= #1 `ALUOP_ADD;
593
594			`// ALU instructions except the one with immediate`
595			`OR32_ALU:
596			`alu_op <= #1 id_insn[3:0];`
597
598			`// SFXX instructions`
599			`OR32_SFXX:
600			alu_op <= #1 `ALUOP_COMP;
601
602			`// l.nop`
603			`OR32_NOP:
604			alu_op <= #1 `ALUOP_NOP;
605
606			`// Illegal and OR1200 unsupported instructions`
607			`default: begin`
608			alu_op <= #1 `ALUOP_NOP;
609			`ifdef OR1200_VERBOSE
610			`// synopsys translate_off`
611			`$display("%t: Illegal insn.... insn %h", $time, id_insn);`
612			`// synopsys translate_on`
613			`endif
614			`end`
615
616			`endcase`
617
618			`end`
619			`end`
620
621			`//`
622			`// Decode of shrot_op`
623			`//`
624			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
625			`if (rst_or_except_flushpipe)`
626			shrot_op <= #1 `SHROTOP_NOP;
627			`else if (!ex_freeze & id_freeze)`
628			shrot_op <= #1 `SHROTOP_NOP;
629			`else if (!ex_freeze) begin`
630			shrot_op <= #1 id_insn[`SHROTOP_POS];
631			`end`
632			`end`
633
634			`//`
635			`// Decode of rfwb_op`
636			`//`
637			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
638			`if (rst_or_except_flushpipe)`
639			rfwb_op <= #1 `RFWBOP_NOP;
640			`else if (!ex_freeze & id_freeze)`
641			rfwb_op <= #1 `RFWBOP_NOP;
642			`else if (!ex_freeze) begin`
643			`case (id_insn[31:26]) // synopsys full_case parallel_case`
644
645			`// j.jal`
646			`OR32_JAL:
647			rfwb_op <= #1 `RFWBOP_LR;
648
649			`// j.jalr`
650			`OR32_JALR:
651			rfwb_op <= #1 `RFWBOP_LR;
652
653			`// l.movhi`
654			`OR32_MOVHI:
655			rfwb_op <= #1 `RFWBOP_ALU;
656
657			`// l.mfspr`
658			`OR32_MFSPR:
659			rfwb_op <= #1 `RFWBOP_SPRS;
660
661			`// l.lwz`
662			`OR32_LWZ:
663			rfwb_op <= #1 `RFWBOP_LSU;
664
665			`// l.lbz`
666			`OR32_LBZ:
667			rfwb_op <= #1 `RFWBOP_LSU;
668
669			`// l.lbs`
670			`OR32_LBS:
671			rfwb_op <= #1 `RFWBOP_LSU;
672
673			`// l.lhz`
674			`OR32_LHZ:
675			rfwb_op <= #1 `RFWBOP_LSU;
676
677			`// l.lhs`
678			`OR32_LHS:
679			rfwb_op <= #1 `RFWBOP_LSU;
680
681			`// l.addi`
682			`OR32_ADDI:
683			rfwb_op <= #1 `RFWBOP_ALU;
684
685			`// l.addic`
686			`OR32_ADDIC:
687			rfwb_op <= #1 `RFWBOP_ALU;
688
689			`// l.andi`
690			`OR32_ANDI:
691			rfwb_op <= #1 `RFWBOP_ALU;
692
693			`// l.ori`
694			`OR32_ORI:
695			rfwb_op <= #1 `RFWBOP_ALU;
696
697			`// l.xori`
698			`OR32_XORI:
699			rfwb_op <= #1 `RFWBOP_ALU;
700
701			`// l.muli`
702			`OR32_MULI:
703			rfwb_op <= #1 `RFWBOP_ALU;
704
705			`// l.maci`
706			`OR32_MACI:
707			rfwb_op <= #1 `RFWBOP_ALU;
708
709			`// Shift and rotate insns with immediate`
710			`OR32_SH_ROTI:
711			rfwb_op <= #1 `RFWBOP_ALU;
712
713			`// ALU instructions except the one with immediate`
714			`OR32_ALU:
715			rfwb_op <= #1 `RFWBOP_ALU;
716
717			`// Instructions w/o register-file write-back`
718			`default: begin`
719			rfwb_op <= #1 `RFWBOP_NOP;
720			`end`
721
722			`endcase`
723			`end`
724			`end`
725
726			`//`
727			`// Decode of pre_branch_op`
728			`//`
729			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
730			`if (rst_or_except_flushpipe)`
731			pre_branch_op <= #1 `BRANCHOP_NOP;
732			`else if (!id_freeze) begin`
733			`case (if_insn[31:26]) // synopsys full_case parallel_case`
734
735			`// l.j`
736			`OR32_J:
737			pre_branch_op <= #1 `BRANCHOP_BAL;
738
739			`// j.jal`
740			`OR32_JAL:
741			pre_branch_op <= #1 `BRANCHOP_BAL;
742
743			`// j.jalr`
744			`OR32_JALR:
745			pre_branch_op <= #1 `BRANCHOP_JR;
746
747			`// l.jr`
748			`OR32_JR:
749			pre_branch_op <= #1 `BRANCHOP_JR;
750
751			`// l.bnf`
752			`OR32_BNF:
753			pre_branch_op <= #1 `BRANCHOP_BNF;
754
755			`// l.bf`
756			`OR32_BF:
757			pre_branch_op <= #1 `BRANCHOP_BF;
758
759			`// l.rfe`
760			`OR32_RFE:
761			pre_branch_op <= #1 `BRANCHOP_RFE;
762
763			`// Non branch instructions`
764			`default: begin`
765			pre_branch_op <= #1 `BRANCHOP_NOP;
766			`end`
767			`endcase`
768			`end`
769			`end`
770
771			`//`
772			`// Generation of branch_op`
773			`//`
774			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
775			`if (rst_or_except_flushpipe)`
776			branch_op <= #1 `BRANCHOP_NOP;
777			`else if (!ex_freeze & id_freeze)`
778			branch_op <= #1 `BRANCHOP_NOP;
779			`else if (!ex_freeze) begin`
780			`branch_op <= #1 pre_branch_op;`
781			`end`
782			`end`
783
784			`//`
785			`// Decode of lsu_op`
786			`//`
787			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
788			`if (rst_or_except_flushpipe)`
789			lsu_op <= #1 `LSUOP_NOP;
790			`else if (!ex_freeze & id_freeze)`
791			lsu_op <= #1 `LSUOP_NOP;
792			`else if (!ex_freeze) begin`
793			`case (id_insn[31:26]) // synopsys full_case parallel_case`
794
795			`// l.lwz`
796			`OR32_LWZ:
797			lsu_op <= #1 `LSUOP_LWZ;
798
799			`// l.lbz`
800			`OR32_LBZ:
801			lsu_op <= #1 `LSUOP_LBZ;
802
803			`// l.lbs`
804			`OR32_LBS:
805			lsu_op <= #1 `LSUOP_LBS;
806
807			`// l.lhz`
808			`OR32_LHZ:
809			lsu_op <= #1 `LSUOP_LHZ;
810
811			`// l.lhs`
812			`OR32_LHS:
813			lsu_op <= #1 `LSUOP_LHS;
814
815			`// l.sw`
816			`OR32_SW:
817			lsu_op <= #1 `LSUOP_SW;
818
819			`// l.sb`
820			`OR32_SB:
821			lsu_op <= #1 `LSUOP_SB;
822
823			`// l.sh`
824			`OR32_SH:
825			lsu_op <= #1 `LSUOP_SH;
826
827			`// Non load/store instructions`
828			`default: begin`
829			lsu_op <= #1 `LSUOP_NOP;
830			`end`
831			`endcase`
832			`end`
833			`end`
834
835			`//`
836			`// Decode of comp_op`
837			`//`
838			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
839			`if (rst_or_except_flushpipe)`
840			`comp_op <= #1 4'd0;`
841			`else if (!ex_freeze & id_freeze)`
842			`comp_op <= #1 4'd0;`
843			`else if (!ex_freeze) begin`
844			`comp_op <= #1 id_insn[24:21];`
845			`end`
846			`end`
847
848			`//`
849			`// Decode of l.sys`
850			`//`
851			`always @(posedge clk or posedge rst) begin`
852			`if (rst)`
853			`sig_syscall <= #1 1'b0;`
854			`else if (!ex_freeze & id_freeze)`
855			`sig_syscall <= #1 1'b0;`
856			`else if (!ex_freeze) begin`
857			`ifdef OR1200_VERBOSE
858			`// synopsys translate_off`
859			if (id_insn[31:23] == {`OR32_XSYNC, 3'b000})
860			`$display("Generating sig_syscall");`
861			`// synopsys translate_on`
862			`endif
863			sig_syscall <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b000});
864			`end`
865			`end`
866
867			`//`
868			`// Decode of l.trap`
869			`//`
870			`always @(posedge clk or posedge rst) begin`
871			`if (rst)`
872			`sig_trap <= #1 1'b0;`
873			`else if (!ex_freeze & id_freeze)`
874			`sig_trap <= #1 1'b0;`
875			`else if (!ex_freeze) begin`
876			`ifdef OR1200_VERBOSE
877			`// synopsys translate_off`
878			if (id_insn[31:23] == {`OR32_XSYNC, 3'b010})
879			`$display("Generating sig_trap");`
880			`// synopsys translate_on`
881			`endif
882			sig_trap <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b010});
883			`end`
884			`end`
885
886			`endmodule`