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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [mem2reg.v] - Blame information for rev 1765

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1 266 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's mem2reg alignment                                  ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Two versions of Memory to register data alignment.          ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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module mem2reg(addr, lsu_op, memdata, regdata);
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parameter width = `OPERAND_WIDTH;
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//
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// I/O
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//
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input   [1:0]                    addr;
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input   [`LSUOP_WIDTH-1:0]       lsu_op;
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input   [width-1:0]              memdata;
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output  [width-1:0]              regdata;
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//
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// Faster implementation of mem2reg
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//
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`ifdef MEM2REG_FAST
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`define SEL_00 2'b00
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`define SEL_01 2'b01
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`define SEL_10 2'b10
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`define SEL_11 2'b11
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reg     [width-1:0]              regdata;
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reg     [width-1:0]              aligned;
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reg     [1:0]                    sel_byte0, sel_byte1,
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                                sel_byte2, sel_byte3;
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//
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// Byte select 0
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//
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always @(addr or lsu_op) begin
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        casex({lsu_op[2:0], addr})
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                {3'b01x, 2'b00}:
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                        sel_byte0 = `SEL_11;
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                {3'b01x, 2'b01}:
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                        sel_byte0 = `SEL_10;
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                {3'b01x, 2'b10}:
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                        sel_byte0 = `SEL_01;
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                {3'b01x, 2'b11}:
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                        sel_byte0 = `SEL_00;
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                {3'b10x, 2'b00}:
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                        sel_byte0 = `SEL_10;
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                {3'b10x, 2'b10}:
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                        sel_byte0 = `SEL_00;
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                default:
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                        sel_byte0 = `SEL_00;
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        endcase
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end
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//
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// Byte select 1
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//
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always @(addr or lsu_op) begin
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        casex({lsu_op[2:0], addr})
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                {3'b010, 2'bxx}:
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                        sel_byte1 = `SEL_00;    // zero extend
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                {3'b011, 2'bxx}:
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                        sel_byte1 = `SEL_10;    // sign extend byte
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                {3'b10x, 2'b00}:
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                        sel_byte1 = `SEL_11;
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                default:
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                        sel_byte1 = `SEL_01;
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        endcase
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end
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//
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// Byte select 2
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//
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always @(addr or lsu_op) begin
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        casex({lsu_op[2:0], addr})
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                {3'b010, 2'bxx},
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                {3'b100, 2'bxx}:
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                        sel_byte2 = `SEL_00;    // zero extend
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                {3'b011, 2'bxx}:
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                        sel_byte2 = `SEL_01;    // sign extend byte
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                {3'b101, 2'bxx}:
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                        sel_byte2 = `SEL_11;    // sign extend halfword
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                default:
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                        sel_byte2 = `SEL_10;
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        endcase
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end
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//
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// Byte select 3
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//
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always @(addr or lsu_op) begin
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        casex({lsu_op[2:0], addr})
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                {3'b010, 2'bxx},
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                {3'b100, 2'bxx}:
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                        sel_byte3 = `SEL_00;    // zero extend
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                {3'b011, 2'bxx}:
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                        sel_byte3 = `SEL_01;    // sign extend byte
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                {3'b101, 2'bxx}:
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                        sel_byte3 = `SEL_10;    // sign extend halfword
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                default:
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                        sel_byte3 = `SEL_11;
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        endcase
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end
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//
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// Byte 0
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//
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always @(sel_byte0 or memdata) begin
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        case(sel_byte0) // synopsys full_case parallel_case infer_mux
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                `SEL_00: begin
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                                regdata[7:0] = memdata[7:0];
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                        end
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                `SEL_01: begin
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                                regdata[7:0] = memdata[15:8];
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                        end
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                `SEL_10: begin
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                                regdata[7:0] = memdata[23:16];
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                        end
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                `SEL_11: begin
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                                regdata[7:0] = memdata[31:24];
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                        end
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        endcase
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end
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//
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// Byte 1
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//
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always @(sel_byte1 or memdata) begin
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        case(sel_byte1) // synopsys full_case parallel_case infer_mux
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                `SEL_00: begin
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                                regdata[15:8] = 8'b0;
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                        end
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                `SEL_01: begin
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                                regdata[15:8] = memdata[15:8];
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                        end
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                `SEL_10: begin
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                                regdata[15:8] = {8{memdata[7]}};
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                        end
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                `SEL_11: begin
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                                regdata[15:8] = memdata[31:24];
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                        end
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        endcase
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end
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//
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// Byte 2
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//
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always @(sel_byte2 or memdata) begin
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        case(sel_byte2) // synopsys full_case parallel_case infer_mux
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                `SEL_00: begin
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                                regdata[23:16] = 8'b0;
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                        end
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                `SEL_01: begin
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                                regdata[23:16] = {8{memdata[7]}};
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                        end
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                `SEL_10: begin
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                                regdata[23:16] = memdata[23:16];
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                        end
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                `SEL_11: begin
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                                regdata[23:16] = {8{memdata[15]}};
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                        end
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        endcase
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end
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//
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// Byte 3
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//
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always @(sel_byte3 or memdata) begin
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        case(sel_byte3) // synopsys full_case parallel_case infer_mux
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                `SEL_00: begin
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                                regdata[31:24] = 8'b0;
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                        end
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                `SEL_01: begin
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                                regdata[31:24] = {8{memdata[7]}};
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                        end
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                `SEL_10: begin
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                                regdata[31:24] = {8{memdata[15]}};
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                        end
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                `SEL_11: begin
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                                regdata[31:24] = memdata[31:24];
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                        end
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        endcase
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end
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`else
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//
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// Slow implementation of mem2reg
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//
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reg     [width-1:0]              regdata;
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reg     [width-1:0]              aligned;
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//
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// Alignment
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//
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always @(addr or memdata) begin
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        case(addr) // synopsys infer_mux
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                2'b00:
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                        aligned = memdata;
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                2'b01:
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                        aligned = {memdata[23:0], 8'b0};
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                2'b10:
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                        aligned = {memdata[15:0], 16'b0};
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                2'b11:
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                        aligned = {memdata[7:0], 24'b0};
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        endcase
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end
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//
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// Bytes
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//
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always @(lsu_op or aligned) begin
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        case(lsu_op) // synopsys infer_mux
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                `LSUOP_LBZ: begin
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                                regdata[7:0] = aligned[31:24];
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                                regdata[31:8] = 24'b0;
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                        end
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                `LSUOP_LBS: begin
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                                regdata[7:0] = aligned[31:24];
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                                regdata[31:8] = {24{aligned[31]}};
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                        end
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                `LSUOP_LHZ: begin
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                                regdata[15:0] = aligned[31:16];
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                                regdata[31:16] = 16'b0;
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                        end
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                `LSUOP_LHS: begin
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                                regdata[15:0] = aligned[31:16];
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                                regdata[31:16] = {16{aligned[31]}};
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                        end
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                default:
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                                regdata = aligned;
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        endcase
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end
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`endif
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endmodule

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