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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// Faster implementation of mem2reg
//
`ifdef MEM2REG_FAST
 
`define SEL_00 2'b00
`define SEL_01 2'b01
`define SEL_10 2'b10
`define SEL_11 2'b11
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
reg     [1:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b01x, 2'b00}:
                        sel_byte0 = `SEL_11;
                {3'b01x, 2'b01}:
                        sel_byte0 = `SEL_10;
                {3'b01x, 2'b10}:
                        sel_byte0 = `SEL_01;
                {3'b01x, 2'b11}:
                        sel_byte0 = `SEL_00;
                {3'b10x, 2'b00}:
                        sel_byte0 = `SEL_10;
                {3'b10x, 2'b10}:
                        sel_byte0 = `SEL_00;
                default:
                        sel_byte0 = `SEL_00;
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx}:
                        sel_byte1 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte1 = `SEL_10;    // sign extend byte
                {3'b10x, 2'b00}:
                        sel_byte1 = `SEL_11;
                default:
                        sel_byte1 = `SEL_01;
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte2 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte2 = `SEL_01;    // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte2 = `SEL_11;    // sign extend halfword
                default:
                        sel_byte2 = `SEL_10;
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte3 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte3 = `SEL_01;    // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte3 = `SEL_10;    // sign extend halfword
                default:
                        sel_byte3 = `SEL_11;
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[7:0] = memdata[7:0];
                        end
                `SEL_01: begin
                                regdata[7:0] = memdata[15:8];
                        end
                `SEL_10: begin
                                regdata[7:0] = memdata[23:16];
                        end
                `SEL_11: begin
                                regdata[7:0] = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[15:8] = 8'b0;
                        end
                `SEL_01: begin
                                regdata[15:8] = memdata[15:8];
                        end
                `SEL_10: begin
                                regdata[15:8] = {8{memdata[7]}};
                        end
                `SEL_11: begin
                                regdata[15:8] = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[23:16] = 8'b0;
                        end
                `SEL_01: begin
                                regdata[23:16] = {8{memdata[7]}};
                        end
                `SEL_10: begin
                                regdata[23:16] = memdata[23:16];
                        end
                `SEL_11: begin
                                regdata[23:16] = {8{memdata[15]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[31:24] = 8'b0;
                        end
                `SEL_01: begin
                                regdata[31:24] = {8{memdata[7]}};
                        end
                `SEL_10: begin
                                regdata[31:24] = {8{memdata[15]}};
                        end
                `SEL_11: begin
                                regdata[31:24] = memdata[31:24];
                        end
        endcase
end
 
`else
 
//
// Slow implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
        case(addr) // synopsys infer_mux
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
        case(lsu_op) // synopsys infer_mux
                `LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [mem2reg.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:03 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`module mem2reg(addr, lsu_op, memdata, regdata);`
64
65			parameter width = `OPERAND_WIDTH;
66
67			`//`
68			`// I/O`
69			`//`
70			`input [1:0] addr;`
71			input [`LSUOP_WIDTH-1:0] lsu_op;
72			`input [width-1:0] memdata;`
73			`output [width-1:0] regdata;`
74
75
76			`//`
77			`// Faster implementation of mem2reg`
78			`//`
79			`ifdef MEM2REG_FAST
80
81			`define SEL_00 2'b00
82			`define SEL_01 2'b01
83			`define SEL_10 2'b10
84			`define SEL_11 2'b11
85
86			`reg [width-1:0] regdata;`
87			`reg [width-1:0] aligned;`
88			`reg [1:0] sel_byte0, sel_byte1,`
89			`sel_byte2, sel_byte3;`
90
91			`//`
92			`// Byte select 0`
93			`//`
94			`always @(addr or lsu_op) begin`
95			`casex({lsu_op[2:0], addr})`
96			`{3'b01x, 2'b00}:`
97			sel_byte0 = `SEL_11;
98			`{3'b01x, 2'b01}:`
99			sel_byte0 = `SEL_10;
100			`{3'b01x, 2'b10}:`
101			sel_byte0 = `SEL_01;
102			`{3'b01x, 2'b11}:`
103			sel_byte0 = `SEL_00;
104			`{3'b10x, 2'b00}:`
105			sel_byte0 = `SEL_10;
106			`{3'b10x, 2'b10}:`
107			sel_byte0 = `SEL_00;
108			`default:`
109			sel_byte0 = `SEL_00;
110			`endcase`
111			`end`
112
113			`//`
114			`// Byte select 1`
115			`//`
116			`always @(addr or lsu_op) begin`
117			`casex({lsu_op[2:0], addr})`
118			`{3'b010, 2'bxx}:`
119			sel_byte1 = `SEL_00; // zero extend
120			`{3'b011, 2'bxx}:`
121			sel_byte1 = `SEL_10; // sign extend byte
122			`{3'b10x, 2'b00}:`
123			sel_byte1 = `SEL_11;
124			`default:`
125			sel_byte1 = `SEL_01;
126			`endcase`
127			`end`
128
129			`//`
130			`// Byte select 2`
131			`//`
132			`always @(addr or lsu_op) begin`
133			`casex({lsu_op[2:0], addr})`
134			`{3'b010, 2'bxx},`
135			`{3'b100, 2'bxx}:`
136			sel_byte2 = `SEL_00; // zero extend
137			`{3'b011, 2'bxx}:`
138			sel_byte2 = `SEL_01; // sign extend byte
139			`{3'b101, 2'bxx}:`
140			sel_byte2 = `SEL_11; // sign extend halfword
141			`default:`
142			sel_byte2 = `SEL_10;
143			`endcase`
144			`end`
145
146			`//`
147			`// Byte select 3`
148			`//`
149			`always @(addr or lsu_op) begin`
150			`casex({lsu_op[2:0], addr})`
151			`{3'b010, 2'bxx},`
152			`{3'b100, 2'bxx}:`
153			sel_byte3 = `SEL_00; // zero extend
154			`{3'b011, 2'bxx}:`
155			sel_byte3 = `SEL_01; // sign extend byte
156			`{3'b101, 2'bxx}:`
157			sel_byte3 = `SEL_10; // sign extend halfword
158			`default:`
159			sel_byte3 = `SEL_11;
160			`endcase`
161			`end`
162
163			`//`
164			`// Byte 0`
165			`//`
166			`always @(sel_byte0 or memdata) begin`
167			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
168			`SEL_00: begin
169			`regdata[7:0] = memdata[7:0];`
170			`end`
171			`SEL_01: begin
172			`regdata[7:0] = memdata[15:8];`
173			`end`
174			`SEL_10: begin
175			`regdata[7:0] = memdata[23:16];`
176			`end`
177			`SEL_11: begin
178			`regdata[7:0] = memdata[31:24];`
179			`end`
180			`endcase`
181			`end`
182
183			`//`
184			`// Byte 1`
185			`//`
186			`always @(sel_byte1 or memdata) begin`
187			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
188			`SEL_00: begin
189			`regdata[15:8] = 8'b0;`
190			`end`
191			`SEL_01: begin
192			`regdata[15:8] = memdata[15:8];`
193			`end`
194			`SEL_10: begin
195			`regdata[15:8] = {8{memdata[7]}};`
196			`end`
197			`SEL_11: begin
198			`regdata[15:8] = memdata[31:24];`
199			`end`
200			`endcase`
201			`end`
202
203			`//`
204			`// Byte 2`
205			`//`
206			`always @(sel_byte2 or memdata) begin`
207			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
208			`SEL_00: begin
209			`regdata[23:16] = 8'b0;`
210			`end`
211			`SEL_01: begin
212			`regdata[23:16] = {8{memdata[7]}};`
213			`end`
214			`SEL_10: begin
215			`regdata[23:16] = memdata[23:16];`
216			`end`
217			`SEL_11: begin
218			`regdata[23:16] = {8{memdata[15]}};`
219			`end`
220			`endcase`
221			`end`
222
223			`//`
224			`// Byte 3`
225			`//`
226			`always @(sel_byte3 or memdata) begin`
227			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
228			`SEL_00: begin
229			`regdata[31:24] = 8'b0;`
230			`end`
231			`SEL_01: begin
232			`regdata[31:24] = {8{memdata[7]}};`
233			`end`
234			`SEL_10: begin
235			`regdata[31:24] = {8{memdata[15]}};`
236			`end`
237			`SEL_11: begin
238			`regdata[31:24] = memdata[31:24];`
239			`end`
240			`endcase`
241			`end`
242
243			`else
244
245			`//`
246			`// Slow implementation of mem2reg`
247			`//`
248
249			`reg [width-1:0] regdata;`
250			`reg [width-1:0] aligned;`
251
252			`//`
253			`// Alignment`
254			`//`
255			`always @(addr or memdata) begin`
256			`case(addr) // synopsys infer_mux`
257			`2'b00:`
258			`aligned = memdata;`
259			`2'b01:`
260			`aligned = {memdata[23:0], 8'b0};`
261			`2'b10:`
262			`aligned = {memdata[15:0], 16'b0};`
263			`2'b11:`
264			`aligned = {memdata[7:0], 24'b0};`
265			`endcase`
266			`end`
267
268			`//`
269			`// Bytes`
270			`//`
271			`always @(lsu_op or aligned) begin`
272			`case(lsu_op) // synopsys infer_mux`
273			`LSUOP_LBZ: begin
274			`regdata[7:0] = aligned[31:24];`
275			`regdata[31:8] = 24'b0;`
276			`end`
277			`LSUOP_LBS: begin
278			`regdata[7:0] = aligned[31:24];`
279			`regdata[31:8] = {24{aligned[31]}};`
280			`end`
281			`LSUOP_LHZ: begin
282			`regdata[15:0] = aligned[31:16];`
283			`regdata[31:16] = 16'b0;`
284			`end`
285			`LSUOP_LHS: begin
286			`regdata[15:0] = aligned[31:16];`
287			`regdata[31:16] = {16{aligned[31]}};`
288			`end`
289			`default:`
290			`regdata = aligned;`
291			`endcase`
292			`end`
293
294			`endif
295
296			`endmodule`