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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.4  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module or1200(
        // System
        clk, rst, pic_ints, clkdiv_by_2,
 
        // Instruction WISHBONE INTERFACE
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
 
        // Data WISHBONE INTERFACE
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
 
        // External Debug Interface
        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
 
        // Power Management
        pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
        pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
 
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
parameter ppic_ints = `PIC_INTS;
 
//
// I/O
//
 
//
// System
//
input                   clk;
input                   rst;
input                   clkdiv_by_2;
input   [ppic_ints-1:0]  pic_ints;
 
//
// Instruction WISHBONE interface
//
input                   iwb_clk_i;      // clock input
input                   iwb_rst_i;      // reset input
input                   iwb_ack_i;      // normal termination
input                   iwb_err_i;      // termination w/ error
input                   iwb_rty_i;      // termination w/ retry
input   [dw-1:0] iwb_dat_i;      // input data bus
output                  iwb_cyc_o;      // cycle valid output
output  [aw-1:0] iwb_adr_o;      // address bus outputs
output                  iwb_stb_o;      // strobe output
output                  iwb_we_o;       // indicates write transfer
output  [3:0]            iwb_sel_o;      // byte select outputs
output  [dw-1:0] iwb_dat_o;      // output data bus
 
//
// Data WISHBONE interface
//
input                   dwb_clk_i;      // clock input
input                   dwb_rst_i;      // reset input
input                   dwb_ack_i;      // normal termination
input                   dwb_err_i;      // termination w/ error
input                   dwb_rty_i;      // termination w/ retry
input   [dw-1:0] dwb_dat_i;      // input data bus
output                  dwb_cyc_o;      // cycle valid output
output  [aw-1:0] dwb_adr_o;      // address bus outputs
output                  dwb_stb_o;      // strobe output
output                  dwb_we_o;       // indicates write transfer
output  [3:0]            dwb_sel_o;      // byte select outputs
output  [dw-1:0] dwb_dat_o;      // output data bus
 
//
// External Debug Interface
//
input                   dbg_stall_i;    // External Stall Input
input   [dw-1:0] dbg_dat_i;      // External Data Input
input   [aw-1:0] dbg_adr_i;      // External Address Input
input   [2:0]            dbg_op_i;       // External Operation Select Input
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
output                  dbg_bp_o;       // Breakpoint Output
output  [dw-1:0] dbg_dat_o;      // External Data Output
 
//
// Power Management
//
input                   pm_cpustall;
output  [3:0]            pm_clksd;
output                  pm_dc_gate;
output                  pm_ic_gate;
output                  pm_dmmu_gate;
output                  pm_immu_gate;
output                  pm_tt_gate;
output                  pm_cpu_gate;
output                  pm_wakeup;
output                  pm_lvolt;
 
 
//
// Internal wires and regs
//
 
//
// DC to BIU
//
wire                    dcbiu_rdy;
wire    [dw-1:0]         dcbiu_from_biu;
wire    [dw-1:0]         dcbiu_to_biu;
wire    [aw-1:0]         dcbiu_addr;
wire                    dcbiu_read;
wire                    dcbiu_write;
wire    [3:0]            dcbiu_sel;
 
//
// IC to BIU
//
wire                    icbiu_rdy;
wire    [dw-1:0] icbiu_from_biu;
wire    [aw-1:0] icbiu_addr;
wire                    icbiu_read;
wire    [3:0]            icbiu_sel;
 
//
// CPU's SPR access to various RISC units (shared wires)
//
wire                    supv;
wire    [aw-1:0] spr_addr;
wire    [dw-1:0] spr_dat_cpu;
wire    [31:0]           spr_cs;
wire                    spr_we;
 
//
// DMMU and CPU
//
wire                    dmmu_en;
wire                    dmmuexcept_miss;
wire                    dmmuexcept_fault;
wire    [31:0]           spr_dat_dmmu;
 
//
// DMMU and DC
//
wire    [aw-1:0] dcdmmu_paddr;
 
//
// DC and CPU's LSU
//
wire                    dclsu_stall;
wire                    dclsu_unstall;
wire    [aw-1:0] dclsu_addr;
wire    [aw-1:0] dclsu_from_dc;
wire    [aw-1:0] dclsu_to_dc;
wire    [`LSUOP_WIDTH-1:0] dclsu_lsuop;
wire                    dc_en;
 
//
// IMMU and CPU
//
wire                    immu_en;
wire                    immuexcept_miss;
wire                    immuexcept_fault;
wire    [31:0]           spr_dat_immu;
 
//
// IC and CPU's ifetch
//
wire                    icfetch_stall;
wire    [aw-1:0] icfetch_addr;
wire    [dw-1:0] icfetch_dataout;
wire    [`FETCHOP_WIDTH-1:0] icfetch_op;
wire                    ic_en;
 
//
// IMMU and IC
//
wire    [aw-1:0] icimmu_paddr;
 
//
// Connection between CPU and PIC
//
wire    [dw-1:0] spr_dat_pic;
wire                    pic_wakeup;
wire                    int_low;
wire                    int_high;
wire                    int_high_tt;
 
//
// Connection between CPU and PM
//
wire    [dw-1:0] spr_dat_pm;
 
//
// CPU and TT
//
wire    [dw-1:0] spr_dat_tt;
wire                    tt_int;
 
//
// Trace port and caches/MMUs
//
wire    [dw-1:0] spr_dat_du;
wire                    du_stall;
wire    [dw-1:0] du_addr;
wire    [dw-1:0] du_dat_du;
wire                    du_read;
wire                    du_write;
wire    [`EXCEPT_WIDTH-1:0] du_except;
 
wire                    ex_freeze;
wire    [`BRANCHOP_WIDTH-1:0]    branch_op;
 
//
// Assignments
//
assign int_high_tt = int_high | tt_int;
 
//
// Instantiation of Instruction WISHBONE BIU
//
wb_biu iwb_biu(
        // WISHBONE interface
        .wb_clk_i(iwb_clk_i),
        .wb_rst_i(iwb_rst_i),
        .wb_ack_i(iwb_ack_i),
        .wb_err_i(iwb_err_i),
        .wb_rty_i(iwb_rty_i),
        .wb_dat_i(iwb_dat_i),
        .wb_cyc_o(iwb_cyc_o),
        .wb_adr_o(iwb_adr_o),
        .wb_stb_o(iwb_stb_o),
        .wb_we_o(iwb_we_o),
        .wb_sel_o(iwb_sel_o),
        .wb_dat_o(iwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(32'b0),
        .biu_addr(icbiu_addr),
        .biu_read(icbiu_read),
        .biu_write(1'b0),
        .biu_rdy(icbiu_rdy),
        .biu_from_biu(icbiu_from_biu),
        .biu_sel(icbiu_sel)
);
 
//
// Instantiation of Data WISHBONE BIU
//
wb_biu dwb_biu(
        // WISHBONE interface
        .wb_clk_i(dwb_clk_i),
        .wb_rst_i(dwb_rst_i),
        .wb_ack_i(dwb_ack_i),
        .wb_err_i(dwb_err_i),
        .wb_rty_i(dwb_rty_i),
        .wb_dat_i(dwb_dat_i),
        .wb_cyc_o(dwb_cyc_o),
        .wb_adr_o(dwb_adr_o),
        .wb_stb_o(dwb_stb_o),
        .wb_we_o(dwb_we_o),
        .wb_sel_o(dwb_sel_o),
        .wb_dat_o(dwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(dcbiu_to_biu),
        .biu_addr(dcbiu_addr),
        .biu_read(dcbiu_read),
        .biu_write(dcbiu_write),
        .biu_rdy(dcbiu_rdy),
        .biu_from_biu(dcbiu_from_biu),
        .biu_sel(dcbiu_sel)
);
 
//
// Instantiation of IMMU
//
immu immu(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // Fetch i/f
        .immu_en(immu_en),
        .supv(supv),
        .immufetch_vaddr(icfetch_addr),
        .immufetch_op(icfetch_op),
        .immufetch_stall(),
 
        // Except I/F
        .immuexcept_miss(immuexcept_miss),
        .immuexcept_fault(immuexcept_fault),
 
        // SPR access
        .spr_cs(spr_cs[`SPR_GROUP_IMMU]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_immu),
 
        // IC i/f
        .icimmu_paddr(icimmu_paddr)
);
 
//
// Instantiation of Instruction Cache
//
ic ic(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect IC to CPU's ifetch
        .icfetch_addr(icimmu_paddr),
        .icfetch_op(icfetch_op),
        .icfetch_dataout(icfetch_dataout),
        .icfetch_stall(icfetch_stall),
        .ic_en(ic_en),
 
        // SPR access
        .spr_cs(spr_cs[`SPR_GROUP_IC]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
 
        // These connect IC to BIU
        .icbiu_rdy(icbiu_rdy),
        .icbiu_datain(icbiu_from_biu),
        .icbiu_addr(icbiu_addr),
        .icbiu_read(icbiu_read),
        .icbiu_sel(icbiu_sel)
);
 
//
// Instantiation of Instruction Cache
//
cpu cpu(
        .clk(clk),
        .rst(rst),
 
        // Connection IC and IFETCHER inside CPU
        .ic_insn(icfetch_dataout),
        .ic_addr(icfetch_addr),
        .ic_stall(icfetch_stall),
        .ic_fetchop(icfetch_op),
        .ic_en(ic_en),
 
        // Connection CPU to external Trace port
        .ex_freeze(ex_freeze),
        .branch_op(branch_op),
        .du_stall(du_stall),
        .du_addr(du_addr),
        .du_dat_du(du_dat_du),
        .du_read(du_read),
        .du_write(du_write),
        .du_except(du_except),
 
        // Connection IMMU and CPU internally
        .immu_en(immu_en),
        .immuexcept_miss(immuexcept_miss),
        .immuexcept_fault(immuexcept_fault),
 
        // Connection DMMU and CPU internally
        .dmmu_en(dmmu_en),
        .dmmuexcept_miss(dmmuexcept_miss),
        .dmmuexcept_fault(dmmuexcept_fault),
 
        // Connection DC and CPU's LSU
        .dclsu_stall(dclsu_stall),
        .dclsu_unstall(dclsu_unstall),
        .dclsu_addr(dclsu_addr),
        .dclsu_datain(dclsu_from_dc),
        .dclsu_dataout(dclsu_to_dc),
        .dclsu_lsuop(dclsu_lsuop),
        .dc_en(dc_en),
 
        // Connection PIC and CPU's EXCEPT
        .int_high(int_high_tt),
        .int_low(int_low),
 
        // SPRs
        .supv(supv),
        .spr_addr(spr_addr),
        .spr_dataout(spr_dat_cpu),
        .spr_dat_pic(spr_dat_pic),
        .spr_dat_tt(spr_dat_tt),
        .spr_dat_pm(spr_dat_pm),
        .spr_dat_dmmu(spr_dat_dmmu),
        .spr_dat_immu(spr_dat_immu),
        .spr_dat_du(spr_dat_du),
        .spr_cs(spr_cs),
        .spr_we(spr_we)
);
 
//
// Instantiation of DMMU
//
dmmu dmmu(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // LSU i/f
        .dmmu_en(dmmu_en),
        .supv(supv),
        .dmmulsu_vaddr(dclsu_addr),
        .dmmulsu_lsuop(dclsu_lsuop),
        .dmmulsu_stall(),
 
        // Except I/F
        .dmmuexcept_miss(dmmuexcept_miss),
        .dmmuexcept_fault(dmmuexcept_fault),
 
        // SPR access
        .spr_cs(spr_cs[`SPR_GROUP_DMMU]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_dmmu),
 
        // DC i/f
        .dcdmmu_paddr(dcdmmu_paddr)
);
 
//
// Instantiation of Data Cache
//
dc dc(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect DC to CPU's LSU
        .dclsu_addr(dcdmmu_paddr),
        .dclsu_lsuop(dclsu_lsuop),
        .dclsu_datain(dclsu_to_dc),
        .dclsu_dataout(dclsu_from_dc),
        .dclsu_stall(dclsu_stall),
        .dclsu_unstall(dclsu_unstall),
        .dc_en(dc_en),
 
        // SPR access
        .spr_cs(spr_cs[`SPR_GROUP_DC]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
 
        // These connect DC to BIU
        .dcbiu_rdy(dcbiu_rdy),
        .dcbiu_datain(dcbiu_from_biu),
        .dcbiu_dataout(dcbiu_to_biu),
        .dcbiu_addr(dcbiu_addr),
        .dcbiu_read(dcbiu_read),
        .dcbiu_write(dcbiu_write),
        .dcbiu_sel(dcbiu_sel)
);
 
//
// Instantiation of Debug Unit
//
du du(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .dclsu_lsuop(dclsu_lsuop),
        .icfetch_op(icfetch_op),
        .ex_freeze(ex_freeze),
        .branch_op(branch_op),
 
        // DU's access to SPR unit
        .du_stall(du_stall),
        .du_addr(du_addr),
        .du_dat_i(spr_dat_cpu),
        .du_dat_o(du_dat_du),
        .du_read(du_read),
        .du_write(du_write),
        .du_except(du_except),
 
        // Access to DU's SPRs
        .spr_cs(spr_cs[`SPR_GROUP_DU]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_du),
 
        // External Debug Interface
        .dbg_stall_i(dbg_stall_i),
        .dbg_dat_i(dbg_dat_i),
        .dbg_adr_i(dbg_adr_i),
        .dbg_op_i(dbg_op_i),
        .dbg_ewt_i(dbg_ewt_i),
        .dbg_lss_o(dbg_lss_o),
        .dbg_is_o(dbg_is_o),
        .dbg_wp_o(dbg_wp_o),
        .dbg_bp_o(dbg_bp_o),
        .dbg_dat_o(dbg_dat_o)
);
 
//
// Programmable interrupt controller
//
pic pic(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_PIC]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pic),
        .pic_wakeup(pic_wakeup),
        .int_low(int_low),
        .int_high(int_high),
 
        // PIC Interface
        .pic_int(pic_ints)
);
 
//
// Instantiation of Tick timer
//
tt tt(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_TT]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_tt),
        .int(tt_int)
);
 
//
// Instantiation of Power Management
//
pm pm(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .pic_wakeup(pic_wakeup),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pm),
 
        // Power Management Interface
        .pm_clksd(pm_clksd),
        .pm_cpustall(pm_cpustall),
        .pm_dc_gate(pm_dc_gate),
        .pm_ic_gate(pm_ic_gate),
        .pm_dmmu_gate(pm_dmmu_gate),
        .pm_immu_gate(pm_immu_gate),
        .pm_tt_gate(pm_tt_gate),
        .pm_cpu_gate(pm_cpu_gate),
        .pm_wakeup(pm_wakeup),
        .pm_lvolt(pm_lvolt)
);
 
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [or1200.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200 Top Level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OR1200 Top Level ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.4 2001/08/13 03:36:20 lampret`
51			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
52			`//`
53			`// Revision 1.3 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`// Revision 1.2 2001/07/22 03:31:54 lampret`
57			`// Fixed RAM's oen bug. Cache bypass under development.`
58			`//`
59			`// Revision 1.1 2001/07/20 00:46:21 lampret`
60			`// Development version of RTL. Libraries are missing.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "defines.v"
68
69			`module or1200(`
70			`// System`
71			`clk, rst, pic_ints, clkdiv_by_2,`
72
73			`// Instruction WISHBONE INTERFACE`
74			`iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,`
75			`iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,`
76
77			`// Data WISHBONE INTERFACE`
78			`dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,`
79			`dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,`
80
81			`// External Debug Interface`
82			`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
83			`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,`
84
85			`// Power Management`
86			`pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,`
87			`pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt`
88
89			`);`
90
91			parameter dw = `OPERAND_WIDTH;
92			parameter aw = `OPERAND_WIDTH;
93			parameter ppic_ints = `PIC_INTS;
94
95			`//`
96			`// I/O`
97			`//`
98
99			`//`
100			`// System`
101			`//`
102			`input clk;`
103			`input rst;`
104			`input clkdiv_by_2;`
105			`input [ppic_ints-1:0] pic_ints;`
106
107			`//`
108			`// Instruction WISHBONE interface`
109			`//`
110			`input iwb_clk_i; // clock input`
111			`input iwb_rst_i; // reset input`
112			`input iwb_ack_i; // normal termination`
113			`input iwb_err_i; // termination w/ error`
114			`input iwb_rty_i; // termination w/ retry`
115			`input [dw-1:0] iwb_dat_i; // input data bus`
116			`output iwb_cyc_o; // cycle valid output`
117			`output [aw-1:0] iwb_adr_o; // address bus outputs`
118			`output iwb_stb_o; // strobe output`
119			`output iwb_we_o; // indicates write transfer`
120			`output [3:0] iwb_sel_o; // byte select outputs`
121			`output [dw-1:0] iwb_dat_o; // output data bus`
122
123			`//`
124			`// Data WISHBONE interface`
125			`//`
126			`input dwb_clk_i; // clock input`
127			`input dwb_rst_i; // reset input`
128			`input dwb_ack_i; // normal termination`
129			`input dwb_err_i; // termination w/ error`
130			`input dwb_rty_i; // termination w/ retry`
131			`input [dw-1:0] dwb_dat_i; // input data bus`
132			`output dwb_cyc_o; // cycle valid output`
133			`output [aw-1:0] dwb_adr_o; // address bus outputs`
134			`output dwb_stb_o; // strobe output`
135			`output dwb_we_o; // indicates write transfer`
136			`output [3:0] dwb_sel_o; // byte select outputs`
137			`output [dw-1:0] dwb_dat_o; // output data bus`
138
139			`//`
140			`// External Debug Interface`
141			`//`
142			`input dbg_stall_i; // External Stall Input`
143			`input [dw-1:0] dbg_dat_i; // External Data Input`
144			`input [aw-1:0] dbg_adr_i; // External Address Input`
145			`input [2:0] dbg_op_i; // External Operation Select Input`
146			`input dbg_ewt_i; // External Watchpoint Trigger Input`
147			`output [3:0] dbg_lss_o; // External Load/Store Unit Status`
148			`output [1:0] dbg_is_o; // External Insn Fetch Status`
149			`output [10:0] dbg_wp_o; // Watchpoints Outputs`
150			`output dbg_bp_o; // Breakpoint Output`
151			`output [dw-1:0] dbg_dat_o; // External Data Output`
152
153			`//`
154			`// Power Management`
155			`//`
156			`input pm_cpustall;`
157			`output [3:0] pm_clksd;`
158			`output pm_dc_gate;`
159			`output pm_ic_gate;`
160			`output pm_dmmu_gate;`
161			`output pm_immu_gate;`
162			`output pm_tt_gate;`
163			`output pm_cpu_gate;`
164			`output pm_wakeup;`
165			`output pm_lvolt;`
166
167
168			`//`
169			`// Internal wires and regs`
170			`//`
171
172			`//`
173			`// DC to BIU`
174			`//`
175			`wire dcbiu_rdy;`
176			`wire [dw-1:0] dcbiu_from_biu;`
177			`wire [dw-1:0] dcbiu_to_biu;`
178			`wire [aw-1:0] dcbiu_addr;`
179			`wire dcbiu_read;`
180			`wire dcbiu_write;`
181			`wire [3:0] dcbiu_sel;`
182
183			`//`
184			`// IC to BIU`
185			`//`
186			`wire icbiu_rdy;`
187			`wire [dw-1:0] icbiu_from_biu;`
188			`wire [aw-1:0] icbiu_addr;`
189			`wire icbiu_read;`
190			`wire [3:0] icbiu_sel;`
191
192			`//`
193			`// CPU's SPR access to various RISC units (shared wires)`
194			`//`
195			`wire supv;`
196			`wire [aw-1:0] spr_addr;`
197			`wire [dw-1:0] spr_dat_cpu;`
198			`wire [31:0] spr_cs;`
199			`wire spr_we;`
200
201			`//`
202			`// DMMU and CPU`
203			`//`
204			`wire dmmu_en;`
205			`wire dmmuexcept_miss;`
206			`wire dmmuexcept_fault;`
207			`wire [31:0] spr_dat_dmmu;`
208
209			`//`
210			`// DMMU and DC`
211			`//`
212			`wire [aw-1:0] dcdmmu_paddr;`
213
214			`//`
215			`// DC and CPU's LSU`
216			`//`
217			`wire dclsu_stall;`
218			`wire dclsu_unstall;`
219			`wire [aw-1:0] dclsu_addr;`
220			`wire [aw-1:0] dclsu_from_dc;`
221			`wire [aw-1:0] dclsu_to_dc;`
222			wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
223			`wire dc_en;`
224
225			`//`
226			`// IMMU and CPU`
227			`//`
228			`wire immu_en;`
229			`wire immuexcept_miss;`
230			`wire immuexcept_fault;`
231			`wire [31:0] spr_dat_immu;`
232
233			`//`
234			`// IC and CPU's ifetch`
235			`//`
236			`wire icfetch_stall;`
237			`wire [aw-1:0] icfetch_addr;`
238			`wire [dw-1:0] icfetch_dataout;`
239			wire [`FETCHOP_WIDTH-1:0] icfetch_op;
240			`wire ic_en;`
241
242			`//`
243			`// IMMU and IC`
244			`//`
245			`wire [aw-1:0] icimmu_paddr;`
246
247			`//`
248			`// Connection between CPU and PIC`
249			`//`
250			`wire [dw-1:0] spr_dat_pic;`
251			`wire pic_wakeup;`
252			`wire int_low;`
253			`wire int_high;`
254			`wire int_high_tt;`
255
256			`//`
257			`// Connection between CPU and PM`
258			`//`
259			`wire [dw-1:0] spr_dat_pm;`
260
261			`//`
262			`// CPU and TT`
263			`//`
264			`wire [dw-1:0] spr_dat_tt;`
265			`wire tt_int;`
266
267			`//`
268			`// Trace port and caches/MMUs`
269			`//`
270			`wire [dw-1:0] spr_dat_du;`
271			`wire du_stall;`
272			`wire [dw-1:0] du_addr;`
273			`wire [dw-1:0] du_dat_du;`
274			`wire du_read;`
275			`wire du_write;`
276			wire [`EXCEPT_WIDTH-1:0] du_except;
277
278			`wire ex_freeze;`
279			wire [`BRANCHOP_WIDTH-1:0] branch_op;
280
281			`//`
282			`// Assignments`
283			`//`
284			`assign int_high_tt = int_high \| tt_int;`
285
286			`//`
287			`// Instantiation of Instruction WISHBONE BIU`
288			`//`
289			`wb_biu iwb_biu(`
290			`// WISHBONE interface`
291			`.wb_clk_i(iwb_clk_i),`
292			`.wb_rst_i(iwb_rst_i),`
293			`.wb_ack_i(iwb_ack_i),`
294			`.wb_err_i(iwb_err_i),`
295			`.wb_rty_i(iwb_rty_i),`
296			`.wb_dat_i(iwb_dat_i),`
297			`.wb_cyc_o(iwb_cyc_o),`
298			`.wb_adr_o(iwb_adr_o),`
299			`.wb_stb_o(iwb_stb_o),`
300			`.wb_we_o(iwb_we_o),`
301			`.wb_sel_o(iwb_sel_o),`
302			`.wb_dat_o(iwb_dat_o),`
303
304			`// Internal RISC bus`
305			`.biu_to_biu(32'b0),`
306			`.biu_addr(icbiu_addr),`
307			`.biu_read(icbiu_read),`
308			`.biu_write(1'b0),`
309			`.biu_rdy(icbiu_rdy),`
310			`.biu_from_biu(icbiu_from_biu),`
311			`.biu_sel(icbiu_sel)`
312			`);`
313
314			`//`
315			`// Instantiation of Data WISHBONE BIU`
316			`//`
317			`wb_biu dwb_biu(`
318			`// WISHBONE interface`
319			`.wb_clk_i(dwb_clk_i),`
320			`.wb_rst_i(dwb_rst_i),`
321			`.wb_ack_i(dwb_ack_i),`
322			`.wb_err_i(dwb_err_i),`
323			`.wb_rty_i(dwb_rty_i),`
324			`.wb_dat_i(dwb_dat_i),`
325			`.wb_cyc_o(dwb_cyc_o),`
326			`.wb_adr_o(dwb_adr_o),`
327			`.wb_stb_o(dwb_stb_o),`
328			`.wb_we_o(dwb_we_o),`
329			`.wb_sel_o(dwb_sel_o),`
330			`.wb_dat_o(dwb_dat_o),`
331
332			`// Internal RISC bus`
333			`.biu_to_biu(dcbiu_to_biu),`
334			`.biu_addr(dcbiu_addr),`
335			`.biu_read(dcbiu_read),`
336			`.biu_write(dcbiu_write),`
337			`.biu_rdy(dcbiu_rdy),`
338			`.biu_from_biu(dcbiu_from_biu),`
339			`.biu_sel(dcbiu_sel)`
340			`);`
341
342			`//`
343			`// Instantiation of IMMU`
344			`//`
345			`immu immu(`
346			`// Rst and clk`
347			`.clk(clk),`
348			`.rst(rst),`
349
350			`// Fetch i/f`
351			`.immu_en(immu_en),`
352			`.supv(supv),`
353			`.immufetch_vaddr(icfetch_addr),`
354			`.immufetch_op(icfetch_op),`
355			`.immufetch_stall(),`
356
357			`// Except I/F`
358			`.immuexcept_miss(immuexcept_miss),`
359			`.immuexcept_fault(immuexcept_fault),`
360
361			`// SPR access`
362			.spr_cs(spr_cs[`SPR_GROUP_IMMU]),
363			`.spr_write(spr_we),`
364			`.spr_addr(spr_addr),`
365			`.spr_dat_i(spr_dat_cpu),`
366			`.spr_dat_o(spr_dat_immu),`
367
368			`// IC i/f`
369			`.icimmu_paddr(icimmu_paddr)`
370			`);`
371
372			`//`
373			`// Instantiation of Instruction Cache`
374			`//`
375			`ic ic(`
376			`.clk(clk),`
377			`.rst(rst),`
378			`.clkdiv_by_2(clkdiv_by_2),`
379
380			`// These connect IC to CPU's ifetch`
381			`.icfetch_addr(icimmu_paddr),`
382			`.icfetch_op(icfetch_op),`
383			`.icfetch_dataout(icfetch_dataout),`
384			`.icfetch_stall(icfetch_stall),`
385			`.ic_en(ic_en),`
386
387			`// SPR access`
388			.spr_cs(spr_cs[`SPR_GROUP_IC]),
389			`.spr_write(spr_we),`
390			`.spr_addr(spr_addr),`
391			`.spr_dat_i(spr_dat_cpu),`
392
393			`// These connect IC to BIU`
394			`.icbiu_rdy(icbiu_rdy),`
395			`.icbiu_datain(icbiu_from_biu),`
396			`.icbiu_addr(icbiu_addr),`
397			`.icbiu_read(icbiu_read),`
398			`.icbiu_sel(icbiu_sel)`
399			`);`
400
401			`//`
402			`// Instantiation of Instruction Cache`
403			`//`
404			`cpu cpu(`
405			`.clk(clk),`
406			`.rst(rst),`
407
408			`// Connection IC and IFETCHER inside CPU`
409			`.ic_insn(icfetch_dataout),`
410			`.ic_addr(icfetch_addr),`
411			`.ic_stall(icfetch_stall),`
412			`.ic_fetchop(icfetch_op),`
413			`.ic_en(ic_en),`
414
415			`// Connection CPU to external Trace port`
416			`.ex_freeze(ex_freeze),`
417			`.branch_op(branch_op),`
418			`.du_stall(du_stall),`
419			`.du_addr(du_addr),`
420			`.du_dat_du(du_dat_du),`
421			`.du_read(du_read),`
422			`.du_write(du_write),`
423			`.du_except(du_except),`
424
425			`// Connection IMMU and CPU internally`
426			`.immu_en(immu_en),`
427			`.immuexcept_miss(immuexcept_miss),`
428			`.immuexcept_fault(immuexcept_fault),`
429
430			`// Connection DMMU and CPU internally`
431			`.dmmu_en(dmmu_en),`
432			`.dmmuexcept_miss(dmmuexcept_miss),`
433			`.dmmuexcept_fault(dmmuexcept_fault),`
434
435			`// Connection DC and CPU's LSU`
436			`.dclsu_stall(dclsu_stall),`
437			`.dclsu_unstall(dclsu_unstall),`
438			`.dclsu_addr(dclsu_addr),`
439			`.dclsu_datain(dclsu_from_dc),`
440			`.dclsu_dataout(dclsu_to_dc),`
441			`.dclsu_lsuop(dclsu_lsuop),`
442			`.dc_en(dc_en),`
443
444			`// Connection PIC and CPU's EXCEPT`
445			`.int_high(int_high_tt),`
446			`.int_low(int_low),`
447
448			`// SPRs`
449			`.supv(supv),`
450			`.spr_addr(spr_addr),`
451			`.spr_dataout(spr_dat_cpu),`
452			`.spr_dat_pic(spr_dat_pic),`
453			`.spr_dat_tt(spr_dat_tt),`
454			`.spr_dat_pm(spr_dat_pm),`
455			`.spr_dat_dmmu(spr_dat_dmmu),`
456			`.spr_dat_immu(spr_dat_immu),`
457			`.spr_dat_du(spr_dat_du),`
458			`.spr_cs(spr_cs),`
459			`.spr_we(spr_we)`
460			`);`
461
462			`//`
463			`// Instantiation of DMMU`
464			`//`
465			`dmmu dmmu(`
466			`// Rst and clk`
467			`.clk(clk),`
468			`.rst(rst),`
469
470			`// LSU i/f`
471			`.dmmu_en(dmmu_en),`
472			`.supv(supv),`
473			`.dmmulsu_vaddr(dclsu_addr),`
474			`.dmmulsu_lsuop(dclsu_lsuop),`
475			`.dmmulsu_stall(),`
476
477			`// Except I/F`
478			`.dmmuexcept_miss(dmmuexcept_miss),`
479			`.dmmuexcept_fault(dmmuexcept_fault),`
480
481			`// SPR access`
482			.spr_cs(spr_cs[`SPR_GROUP_DMMU]),
483			`.spr_write(spr_we),`
484			`.spr_addr(spr_addr),`
485			`.spr_dat_i(spr_dat_cpu),`
486			`.spr_dat_o(spr_dat_dmmu),`
487
488			`// DC i/f`
489			`.dcdmmu_paddr(dcdmmu_paddr)`
490			`);`
491
492			`//`
493			`// Instantiation of Data Cache`
494			`//`
495			`dc dc(`
496			`.clk(clk),`
497			`.rst(rst),`
498			`.clkdiv_by_2(clkdiv_by_2),`
499
500			`// These connect DC to CPU's LSU`
501			`.dclsu_addr(dcdmmu_paddr),`
502			`.dclsu_lsuop(dclsu_lsuop),`
503			`.dclsu_datain(dclsu_to_dc),`
504			`.dclsu_dataout(dclsu_from_dc),`
505			`.dclsu_stall(dclsu_stall),`
506			`.dclsu_unstall(dclsu_unstall),`
507			`.dc_en(dc_en),`
508
509			`// SPR access`
510			.spr_cs(spr_cs[`SPR_GROUP_DC]),
511			`.spr_write(spr_we),`
512			`.spr_addr(spr_addr),`
513			`.spr_dat_i(spr_dat_cpu),`
514
515			`// These connect DC to BIU`
516			`.dcbiu_rdy(dcbiu_rdy),`
517			`.dcbiu_datain(dcbiu_from_biu),`
518			`.dcbiu_dataout(dcbiu_to_biu),`
519			`.dcbiu_addr(dcbiu_addr),`
520			`.dcbiu_read(dcbiu_read),`
521			`.dcbiu_write(dcbiu_write),`
522			`.dcbiu_sel(dcbiu_sel)`
523			`);`
524
525			`//`
526			`// Instantiation of Debug Unit`
527			`//`
528			`du du(`
529			`// RISC Internal Interface`
530			`.clk(clk),`
531			`.rst(rst),`
532			`.dclsu_lsuop(dclsu_lsuop),`
533			`.icfetch_op(icfetch_op),`
534			`.ex_freeze(ex_freeze),`
535			`.branch_op(branch_op),`
536
537			`// DU's access to SPR unit`
538			`.du_stall(du_stall),`
539			`.du_addr(du_addr),`
540			`.du_dat_i(spr_dat_cpu),`
541			`.du_dat_o(du_dat_du),`
542			`.du_read(du_read),`
543			`.du_write(du_write),`
544			`.du_except(du_except),`
545
546			`// Access to DU's SPRs`
547			.spr_cs(spr_cs[`SPR_GROUP_DU]),
548			`.spr_write(spr_we),`
549			`.spr_addr(spr_addr),`
550			`.spr_dat_i(spr_dat_cpu),`
551			`.spr_dat_o(spr_dat_du),`
552
553			`// External Debug Interface`
554			`.dbg_stall_i(dbg_stall_i),`
555			`.dbg_dat_i(dbg_dat_i),`
556			`.dbg_adr_i(dbg_adr_i),`
557			`.dbg_op_i(dbg_op_i),`
558			`.dbg_ewt_i(dbg_ewt_i),`
559			`.dbg_lss_o(dbg_lss_o),`
560			`.dbg_is_o(dbg_is_o),`
561			`.dbg_wp_o(dbg_wp_o),`
562			`.dbg_bp_o(dbg_bp_o),`
563			`.dbg_dat_o(dbg_dat_o)`
564			`);`
565
566			`//`
567			`// Programmable interrupt controller`
568			`//`
569			`pic pic(`
570			`// RISC Internal Interface`
571			`.clk(clk),`
572			`.rst(rst),`
573			.spr_cs(spr_cs[`SPR_GROUP_PIC]),
574			`.spr_write(spr_we),`
575			`.spr_addr(spr_addr),`
576			`.spr_dat_i(spr_dat_cpu),`
577			`.spr_dat_o(spr_dat_pic),`
578			`.pic_wakeup(pic_wakeup),`
579			`.int_low(int_low),`
580			`.int_high(int_high),`
581
582			`// PIC Interface`
583			`.pic_int(pic_ints)`
584			`);`
585
586			`//`
587			`// Instantiation of Tick timer`
588			`//`
589			`tt tt(`
590			`// RISC Internal Interface`
591			`.clk(clk),`
592			`.rst(rst),`
593			.spr_cs(spr_cs[`SPR_GROUP_TT]),
594			`.spr_write(spr_we),`
595			`.spr_addr(spr_addr),`
596			`.spr_dat_i(spr_dat_cpu),`
597			`.spr_dat_o(spr_dat_tt),`
598			`.int(tt_int)`
599			`);`
600
601			`//`
602			`// Instantiation of Power Management`
603			`//`
604			`pm pm(`
605			`// RISC Internal Interface`
606			`.clk(clk),`
607			`.rst(rst),`
608			`.pic_wakeup(pic_wakeup),`
609			`.spr_write(spr_we),`
610			`.spr_addr(spr_addr),`
611			`.spr_dat_i(spr_dat_cpu),`
612			`.spr_dat_o(spr_dat_pm),`
613
614			`// Power Management Interface`
615			`.pm_clksd(pm_clksd),`
616			`.pm_cpustall(pm_cpustall),`
617			`.pm_dc_gate(pm_dc_gate),`
618			`.pm_ic_gate(pm_ic_gate),`
619			`.pm_dmmu_gate(pm_dmmu_gate),`
620			`.pm_immu_gate(pm_immu_gate),`
621			`.pm_tt_gate(pm_tt_gate),`
622			`.pm_cpu_gate(pm_cpu_gate),`
623			`.pm_wakeup(pm_wakeup),`
624			`.pm_lvolt(pm_lvolt)`
625			`);`
626
627
628			`endmodule`