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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's WISHBONE BIU                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Implements WISHBONE interface                               ////
////                                                              ////
////  To Do:                                                      ////
////   - add support for wb_err_i                                 ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module wb_biu(
        // WISHBONE interface
        wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
        wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
 
        // Internal RISC bus
        biu_to_biu, biu_addr, biu_read, biu_write, biu_rdy, biu_from_biu, biu_sel
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// WISHBONE interface
//
input                   wb_clk_i;       // clock input
input                   wb_rst_i;       // reset input
input                   wb_ack_i;       // normal termination
input                   wb_err_i;       // termination w/ error
input                   wb_rty_i;       // termination w/ retry
input   [dw-1:0] wb_dat_i;       // input data bus
output                  wb_cyc_o;       // cycle valid output
output  [aw-1:0] wb_adr_o;       // address bus outputs
output                  wb_stb_o;       // strobe output
output                  wb_we_o;        // indicates write transfer
output  [3:0]            wb_sel_o;       // byte select outputs
output  [dw-1:0] wb_dat_o;       // output data bus
 
//
// Internal RISC interface
//
input   [dw-1:0] biu_to_biu;     // input data bus
input   [aw-1:0] biu_addr;       // address bus
input                   biu_read;       // read request
input                   biu_write;      // write request
output                  biu_rdy;        // data valid
output  [dw-1:0] biu_from_biu;   // output data bus
input   [3:0]            biu_sel;        // byte select inputs
 
//
// Registers
//
`ifdef OR1200_REGISTERED_OUTPUTS
reg     [aw-1:0] wb_adr_o;       // address bus outputs
reg                     wb_stb_o;       // strobe output
reg                     wb_we_o;        // indicates write transfer
reg     [3:0]            wb_sel_o;       // byte select outputs
reg     [dw-1:0] wb_dat_o;       // output data bus
`endif
 
//
// WISHBONE I/F <-> Internal RISC I/F conversion
//
 
//
// Address bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_adr_o <= #1 {aw{1'b0}};
        else
                wb_adr_o <= #1 biu_addr;
`else
assign wb_adr_o = biu_addr;
`endif
 
//
// Input data bus
//
assign biu_from_biu = wb_dat_i;
 
//
// Output data bus
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 {dw{1'b0}};
        else
                wb_dat_o <= #1 biu_to_biu;
`else
assign wb_dat_o = biu_to_biu;
`endif
 
//
// Acknowledgment of the data to the RISC
//
assign biu_rdy = wb_ack_i;
 
//
// WB cyc_o
//
assign wb_cyc_o = wb_stb_o;
 
//
// WB stb_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_stb_o <= #1 1'b0;
        else
                wb_stb_o <= #1 (biu_read | biu_write);
`else
assign wb_stb_o = (biu_read | biu_write);
`endif
 
//
// WB we_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_we_o <= #1 1'b0;
        else
                wb_we_o <= #1 biu_write;
`else
assign wb_we_o = biu_write;
`endif
 
//
// WB sel_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_sel_o <= #1 4'b0000;
        else
                wb_sel_o <= #1 biu_sel;
`else
assign wb_sel_o = biu_sel;
`endif
 
endmodule

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's WISHBONE BIU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implements WISHBONE interface ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - add support for wb_err_i ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.3 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.2 2001/07/22 03:31:54 lampret`
54			`// Fixed RAM's oen bug. Cache bypass under development.`
55			`//`
56			`// Revision 1.1 2001/07/20 00:46:23 lampret`
57			`// Development version of RTL. Libraries are missing.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "defines.v"
65
66			`module wb_biu(`
67			`// WISHBONE interface`
68			`wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,`
69			`wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,`
70
71			`// Internal RISC bus`
72			`biu_to_biu, biu_addr, biu_read, biu_write, biu_rdy, biu_from_biu, biu_sel`
73			`);`
74
75			parameter dw = `OPERAND_WIDTH;
76			parameter aw = `OPERAND_WIDTH;
77
78			`//`
79			`// WISHBONE interface`
80			`//`
81			`input wb_clk_i; // clock input`
82			`input wb_rst_i; // reset input`
83			`input wb_ack_i; // normal termination`
84			`input wb_err_i; // termination w/ error`
85			`input wb_rty_i; // termination w/ retry`
86			`input [dw-1:0] wb_dat_i; // input data bus`
87			`output wb_cyc_o; // cycle valid output`
88			`output [aw-1:0] wb_adr_o; // address bus outputs`
89			`output wb_stb_o; // strobe output`
90			`output wb_we_o; // indicates write transfer`
91			`output [3:0] wb_sel_o; // byte select outputs`
92			`output [dw-1:0] wb_dat_o; // output data bus`
93
94			`//`
95			`// Internal RISC interface`
96			`//`
97			`input [dw-1:0] biu_to_biu; // input data bus`
98			`input [aw-1:0] biu_addr; // address bus`
99			`input biu_read; // read request`
100			`input biu_write; // write request`
101			`output biu_rdy; // data valid`
102			`output [dw-1:0] biu_from_biu; // output data bus`
103			`input [3:0] biu_sel; // byte select inputs`
104
105			`//`
106			`// Registers`
107			`//`
108			`ifdef OR1200_REGISTERED_OUTPUTS
109			`reg [aw-1:0] wb_adr_o; // address bus outputs`
110			`reg wb_stb_o; // strobe output`
111			`reg wb_we_o; // indicates write transfer`
112			`reg [3:0] wb_sel_o; // byte select outputs`
113			`reg [dw-1:0] wb_dat_o; // output data bus`
114			`endif
115
116			`//`
117			`// WISHBONE I/F <-> Internal RISC I/F conversion`
118			`//`
119
120			`//`
121			`// Address bus`
122			`//`
123			`ifdef OR1200_REGISTERED_OUTPUTS
124			`always @(posedge wb_clk_i or posedge wb_rst_i)`
125			`if (wb_rst_i)`
126			`wb_adr_o <= #1 {aw{1'b0}};`
127			`else`
128			`wb_adr_o <= #1 biu_addr;`
129			`else
130			`assign wb_adr_o = biu_addr;`
131			`endif
132
133			`//`
134			`// Input data bus`
135			`//`
136			`assign biu_from_biu = wb_dat_i;`
137
138			`//`
139			`// Output data bus`
140			`//`
141			`ifdef OR1200_REGISTERED_OUTPUTS
142			`always @(posedge wb_clk_i or posedge wb_rst_i)`
143			`if (wb_rst_i)`
144			`wb_dat_o <= #1 {dw{1'b0}};`
145			`else`
146			`wb_dat_o <= #1 biu_to_biu;`
147			`else
148			`assign wb_dat_o = biu_to_biu;`
149			`endif
150
151			`//`
152			`// Acknowledgment of the data to the RISC`
153			`//`
154			`assign biu_rdy = wb_ack_i;`
155
156			`//`
157			`// WB cyc_o`
158			`//`
159			`assign wb_cyc_o = wb_stb_o;`
160
161			`//`
162			`// WB stb_o`
163			`//`
164			`ifdef OR1200_REGISTERED_OUTPUTS
165			`always @(posedge wb_clk_i or posedge wb_rst_i)`
166			`if (wb_rst_i)`
167			`wb_stb_o <= #1 1'b0;`
168			`else`
169			`wb_stb_o <= #1 (biu_read \| biu_write);`
170			`else
171			`assign wb_stb_o = (biu_read \| biu_write);`
172			`endif
173
174			`//`
175			`// WB we_o`
176			`//`
177			`ifdef OR1200_REGISTERED_OUTPUTS
178			`always @(posedge wb_clk_i or posedge wb_rst_i)`
179			`if (wb_rst_i)`
180			`wb_we_o <= #1 1'b0;`
181			`else`
182			`wb_we_o <= #1 biu_write;`
183			`else
184			`assign wb_we_o = biu_write;`
185			`endif
186
187			`//`
188			`// WB sel_o`
189			`//`
190			`ifdef OR1200_REGISTERED_OUTPUTS
191			`always @(posedge wb_clk_i or posedge wb_rst_i)`
192			`if (wb_rst_i)`
193			`wb_sel_o <= #1 4'b0000;`
194			`else`
195			`wb_sel_o <= #1 biu_sel;`
196			`else
197			`assign wb_sel_o = biu_sel;`
198			`endif
199
200			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [wb_biu.v] - Blame information for rev 1765