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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [rtl/] [verilog/] [ssvga/] [ssvga_top.v] - Blame information for rev 1765

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1 266 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Simple Small VGA IP Core                                    ////
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////                                                              ////
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////  This file is part of the Simple Small VGA project           ////
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////                                                              ////
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////                                                              ////
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////  Description                                                 ////
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////  Top level of SSVGA.                                         ////
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////                                                              ////
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////  To Do:                                                      ////
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////   Nothing                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/10/06 10:19:09  igorm
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// no message
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module ssvga_top(
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        // Clock and reset
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        wb_clk_i, wb_rst_i,
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        // WISHBONE Master I/F
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        wbm_cyc_o, wbm_stb_o, wbm_sel_o, wbm_we_o,
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        wbm_adr_o, wbm_dat_o, wbm_cab_o,
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        wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
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        // WISHBONE Slave I/F
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        wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,
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        wbs_adr_i, wbs_dat_i, wbs_cab_i,
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        wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
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70
        // Signals to VGA display
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        pad_hsync_o, pad_vsync_o, pad_rgb_o, led_o,
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        // clock x2 output for crtc iob connection
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        pix_clk, misc
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);
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77
//
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// I/O ports
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//
80
 
81
//
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// Clock and reset
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//
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input                   wb_clk_i;       // Pixel Clock
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input                   wb_rst_i;       // Reset
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87
//
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// WISHBONE Master I/F
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//
90
output                  wbm_cyc_o;
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output                  wbm_stb_o;
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output  [3:0]            wbm_sel_o;
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output                  wbm_we_o;
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output  [31:0]           wbm_adr_o;
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output  [31:0]           wbm_dat_o;
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output                  wbm_cab_o;
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input   [31:0]           wbm_dat_i;
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input                   wbm_ack_i;
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input                   wbm_err_i;
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input                   wbm_rty_i;
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102
//
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// WISHBONE Slave I/F
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//
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input                   wbs_cyc_i;
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input                   wbs_stb_i;
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input   [3:0]            wbs_sel_i;
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input                   wbs_we_i;
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input   [31:0]           wbs_adr_i;
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input   [31:0]           wbs_dat_i;
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input                   wbs_cab_i;
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output  [31:0]           wbs_dat_o;
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output                  wbs_ack_o;
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output                  wbs_err_o;
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output                  wbs_rty_o;
116
 
117
//
118
// VGA display
119
//
120
output                  pad_hsync_o;    // H sync
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output                  pad_vsync_o;    // V sync
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output  [15:0]           pad_rgb_o;      // Digital RGB data
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output                  led_o;
124
output          pix_clk ;       // pixel clock output
125
 
126
input   [15:0]   misc;
127
 
128
//
129
// Internal wires and regs
130
//
131
wire                    ssvga_en;       // Global enable
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wire                    fifo_full;      // FIFO full flag
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wire                    fifo_empty;     // FIFO empty flag
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wire            wbm_restart ; // indicator on when WISHBONE master should restart whole screen because of pixel buffer underrun
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wire                    crtc_hblank;    // H blank
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wire                    crtc_vblank;    // V blank
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wire                    fifo_wr_en;     // FIFO write enable
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wire                    fifo_rd_en;     // FIFO read enable
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wire    [31:0]           fifo_in;        // FIFO input data
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wire    [7:0]            fifo_out;       // FIFO output data
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//wire  [7:0]           pal_indx;       // Palette index
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wire                    pal_wr_en;      // Palette write enable
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wire                    pal_rd_en;      // Palette read enable
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wire    [15:0]  pal_pix_dat ; // pixel output from pallete RAM
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146
// clockx2 - buffered
147
wire    clk_2x_buf;
148
assign  pix_clk = clk_2x_buf ;
149
reg go ;
150
 
151
// rgb output assignment - when blank output transmits black pixels, otherwise it transmits pallete data
152
reg drive_blank_reg ;
153
//always@(posedge wb_clk_i or posedge wb_rst_i)
154
always@(posedge clk_2x_buf or posedge wb_rst_i)
155
begin
156
    if ( wb_rst_i )
157
        drive_blank_reg <= #1 1'b0 ;
158
    else
159
        drive_blank_reg <= #1 ( crtc_hblank || crtc_vblank || ~go ) ;
160
end
161
 
162
assign pad_rgb_o =  drive_blank_reg ? 16'h0000 : pal_pix_dat ;
163
//assign pad_rgb_o =  drive_blank_reg ? 16'h0000 : wbs_dat_i[15:0]; // for test
164
 
165
assign led_o = ssvga_en ;
166
 
167
//
168
// Read FIFO when blanks are not asserted and fifo has been filled once
169
//
170
always@(posedge wb_clk_i or posedge wb_rst_i)
171
begin
172
    if ( wb_rst_i )
173
        go <= #1 1'b0 ;
174
    else
175
    if ( ~ssvga_en )
176
        go <= #1 1'b0 ;
177
    else
178
        go <= #1 ( fifo_full & crtc_hblank & crtc_vblank ) || ( go && ~fifo_empty ) ;
179
end
180
 
181
assign fifo_rd_en = !crtc_hblank & !crtc_vblank & go ;
182
 
183
assign wbm_restart = go & fifo_empty ;
184
 
185
//
186
// Palette index is either color index from FIFO or
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// address from WISHBONE slave when writing into palette
188
//
189
//assign pal_indx = (pal_wr_en || pal_rd_en) ? wbs_adr_i[9:2] : fifo_out;
190
 
191
//
192
// Instantiation of WISHBONE Master block
193
//
194
wire [31:2] pix_start_addr ;
195
ssvga_wbm_if ssvga_wbm_if(
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197
        // Clock and reset
198
        .wb_clk_i(wb_clk_i),
199
        .wb_rst_i(wb_rst_i),
200
 
201
        // WISHBONE Master I/F
202
        .wbm_cyc_o(wbm_cyc_o),
203
        .wbm_stb_o(wbm_stb_o),
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        .wbm_sel_o(wbm_sel_o),
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        .wbm_we_o(wbm_we_o),
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        .wbm_adr_o(wbm_adr_o),
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        .wbm_dat_o(wbm_dat_o),
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        .wbm_cab_o(wbm_cab_o),
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        .wbm_dat_i(wbm_dat_i),
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        .wbm_ack_i(wbm_ack_i),
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        .wbm_err_i(wbm_err_i),
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        .wbm_rty_i(wbm_rty_i),
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        // FIFO control and other signals
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        .ssvga_en(ssvga_en),
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        .fifo_full(fifo_full),
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        .fifo_wr_en(fifo_wr_en),
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        .fifo_dat(fifo_in),
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    .pix_start_addr(pix_start_addr),
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    .resync(wbm_restart)
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);
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223
//
224
// Instantiation of WISHBONE Slave block
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//
226
wire [15:0] wbs_pal_data ;
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ssvga_wbs_if ssvga_wbs_if(
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        // Clock and reset
230
        .wb_clk_i(wb_clk_i),
231
        .wb_rst_i(wb_rst_i),
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233
        // WISHBONE Slave I/F
234
        .wbs_cyc_i(wbs_cyc_i),
235
        .wbs_stb_i(wbs_stb_i),
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        .wbs_sel_i(wbs_sel_i),
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        .wbs_we_i(wbs_we_i),
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        .wbs_adr_i(wbs_adr_i),
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        .wbs_dat_i(wbs_dat_i),
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        .wbs_cab_i(wbs_cab_i),
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        .wbs_dat_o(wbs_dat_o),
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        .wbs_ack_o(wbs_ack_o),
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        .wbs_err_o(wbs_err_o),
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        .wbs_rty_o(wbs_rty_o),
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246
        // Control for other SSVGA blocks
247
        .ssvga_en(ssvga_en),
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        .pal_wr_en(pal_wr_en),
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    .pal_rd_en(pal_rd_en),
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        .pal_dat(wbs_pal_data),
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    .pix_start_addr(pix_start_addr),
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        .misc(misc)
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);
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//
256
// Instantiation of line FIFO block
257
//
258
ssvga_fifo ssvga_fifo(
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        .wclk(wb_clk_i),
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        .rclk(clk_2x_buf),
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        .rst(wb_rst_i),
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        .wr_en(fifo_wr_en),
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        .rd_en(fifo_rd_en),
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        .dat_i(fifo_in),
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        .dat_o(fifo_out),
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        .full(fifo_full),
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        .empty(fifo_empty),
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    .ssvga_en(ssvga_en)
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);
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271
//
272
// Instantiation of 256x16 Palette block
273
//
274
RAMB4_S16_S16 ssvga_pallete
275
(
276
    .ADDRA(wbs_adr_i[9:2]),
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    .DIA(wbs_dat_i[15:0]),
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    .ENA(1'b1),
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    .RSTA(wb_rst_i),
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    .CLKA(wb_clk_i),
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    .WEA(pal_wr_en),
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    .DOA(wbs_pal_data),
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    .ADDRB(fifo_out),
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    .DIB(16'h0000),
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    .ENB(1'b1),
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    .RSTB(wb_rst_i),
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    .CLKB(clk_2x_buf),
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    .WEB(1'b0),
289
    .DOB(pal_pix_dat)
290
) ;
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292
/*generic_spram_256x16 ssvga_palette(
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        // Generic synchronous single-port RAM interface
294
        .clk(wb_clk_i),
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        .rst(wb_rst_i),
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        .ce(1'b1),
297
        .we(pal_wr_en),
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        .oe(1'b1),
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        .addr(pal_indx),
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        .di(wbs_dat_i[15:0]),
301
        .do(pad_rgb_o)
302
);
303
*/
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//
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// Instantiation of CRT controller block
306
//
307
wire    clk_buf;
308
wire    clk_2x;
309
assign clk_buf = wb_clk_i;
310
`ifdef TARGET_VIRTEX
311
BUFG BUFG_crt2(.O(clk_2x_buf), .I(clk_2x));
312
`else
313
assign clk_2x_buf = clk_2x;
314
`endif
315
 
316
`ifdef TARGET_VIRTEX
317
CLKDLL CLKDLL(
318
        .CLK0(),
319
        .CLK90(),
320
        .CLK180(),
321
        .CLK270(),
322
        .CLK2X(clk_2x),
323
        .CLKDV(),
324
        .LOCKED(),
325
        .CLKIN(clk_buf),
326
        .CLKFB(clk_2x_buf),
327
        .RST(1'b0)
328
);
329
`else
330
assign clk_2x = clk_buf;
331
`endif
332
 
333
ssvga_crtc ssvga_crtc(
334
        .clk(clk_2x_buf),
335
        .rst(wb_rst_i),
336
        .hsync(pad_hsync_o),
337
        .vsync(pad_vsync_o),
338
        .hblank(crtc_hblank),
339
        .vblank(crtc_vblank)
340
);
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endmodule

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