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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [syn/] [design_compiler/] [bin/] [top.scr] - Blame information for rev 1768

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Line No. Rev Author Line
1 268 lampret
/*
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 * User defines for synthesizing RTC IP core
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 *
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 */
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TOPLEVEL = xfpga_top
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include ../bin/select_tech.inc
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CLK = clk
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RST = rstn
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CLK_PERIOD = 5          /* 200 MHz */
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MAX_AREA = 0            /* Push hard */
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DO_UNGROUP = yes        /* yes, no */
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DO_VERIFY = yes         /* yes, no */
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/* Starting timestamp */
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sh date
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/* Set some basic variables related to environment */
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include ../bin/set_env.inc
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STAGE = final
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/* Load libraries */
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include ../bin/tech_ + TECH + .inc
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/* Load HDL source files */
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include ../bin/read_design.inc          > LOG_PATH + read_design_ + TOPLEVEL + .log
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/* Set design top */
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current_design TOPLEVEL
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/* Link all blocks and uniquify them */
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link
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uniquify
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check_design                    > LOG_PATH + check_design_ + TOPLEVEL + .log
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/* Apply constraints */
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if (TECH == "vs_umc18") {
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        include ../bin/cons_vs_umc18.inc
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} else if (TECH == "art_umc18") {
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        include ../bin/cons_art_umc18.inc
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} else {
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        echo "Error: Unsupported technology"
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        exit
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}
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/* Lets do basic synthesis */
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if (DO_UNGROUP == "yes") {
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        ungroup -all
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}
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compile -boundary_optimization -map_effort low
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/* Dump gate-level from incremental synthesis */
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include ../bin/save_design.inc
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/* Generate reports for incremental synthesis */
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include ../bin/reports.inc
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/* Verify design */
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if (DO_VERIFY == "yes") {
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        compile -no_map -verify         > LOG_PATH + verify_ + TOPLEVEL + .log
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}
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/* Finish */
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sh date
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exit

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