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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`ALUOP_WIDTH-1:0]       alu_op;
input   [`SHROTOP_WIDTH-1:0]     shrot_op;
input   [`COMPOP_WIDTH-1:0]      comp_op;
output  [width-1:0]              result;
output                          flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg                             flagforw;
reg                             flag_we;
reg                             flag;
integer                         d1;
integer                         d2;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
wire                            a_eq_b;
wire                            a_lt_b;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin
        casex (alu_op)          // synopsys parallel_case full_case
                `ALUOP_SHROT : begin
                                result = shifted_rotated;
                                flag_we = 1'b0;
                end
                `ALUOP_ADD : begin
                                result = a + b;
                                flag_we = 1'b0;
                end
                `ALUOP_SUB : begin
                                result = a - b;
                                flag_we = 1'b0;
                end
                `ALUOP_XOR : begin
                                result = a ^ b;
                                flag_we = 1'b0;
                end
                `ALUOP_OR  : begin
                                result = a | b;
                                flag_we = 1'b0;
                end
                `ALUOP_IMM : begin
                                result = b;
                                flag_we = 1'b0;
                end
                `ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                        flag_we = 1'b0;
                                end
                                else begin
                                        result = b << 16;
                                        flag_we = 1'b0;
                                end
                end
                `ALUOP_MUL : begin
                                result = mult_mac_result;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
// synopsys translate_on
`endif
                                flag_we = 1'b0;
                end
// synopsys translate_off
`ifdef SIM_ALU_DIV
                `ALUOP_DIV : begin
                                d1 = a;
                                d2 = b;
                                $display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
                                if (d2)
                                        result = d1 / d2;
                                else
                                        result = 32'h00000000;
                                flag_we = 1'b0;
                end
`endif
`ifdef SIM_ALU_DIVU
                `ALUOP_DIVU : begin
                                if (b)
                                        result = a / b;
                                else
                                        result = 32'h00000000;
                                flag_we = 1'b0;
                end
`endif
// synopsys translate_on
                `ALUOP_COMP: begin
                                flag_we = 1'b1;
                                result = 32'd0;
                end
                default : begin // `ALUOP_AND
                                result = a & b;
                                flag_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
                `SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
`ifdef IMPL_ALU_ROTATE
                `SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `COP_SFEQ:
                        flagforw = a_eq_b;
                `COP_SFNE:
                        flagforw = ~a_eq_b;
                `COP_SFGT:
                        flagforw = ~(a_eq_b | a_lt_b);
                `COP_SFGE:
                        flagforw = ~a_lt_b;
                `COP_SFLT:
                        flagforw = a_lt_b;
                `COP_SFLE:
                        flagforw = a_eq_b | a_lt_b;
// synopsys translate_off
                default:
                        flagforw = 1'bx;
// synopsys translate_on
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef IMPL_ALU_COMP2
always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `COP_SFEQ:
                        flagforw = (comp_a == comp_b);
                `COP_SFNE:
                        flagforw = (comp_a != comp_b);
                `COP_SFGT:
                        flagforw = (comp_a > comp_b);
                `COP_SFGE:
                        flagforw = (comp_a >= comp_b);
                `COP_SFLT:
                        flagforw = (comp_a < comp_b);
                `COP_SFLE:
                        flagforw = (comp_a <= comp_b);
// synopsys translate_off
                default:
                        flagforw = 1'bx;
// synopsys translate_on
        endcase
end
`endif
 
//
// Flag bit
//
always @(posedge clk or posedge rst) begin
        if (rst)
                flag <= #1 1'b0;
        else if (flag_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);
// synopsys translate_on
`endif
                flag <= #1 flagforw;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	217	lampret	`// $Log: not supported by cvs2svn $`
47	218	lampret	`// Revision 1.8 2001/10/19 23:28:45 lampret`
48			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
49			`//`
50	217	lampret	`// Revision 1.7 2001/10/14 13:12:09 lampret`
51			`// MP3 version.`
52	218	lampret	`//`
53			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
54			`// no message`
55			`//`
56			`// Revision 1.2 2001/08/09 13:39:33 lampret`
57			`// Major clean-up.`
58			`//`
59			`// Revision 1.1 2001/07/20 00:46:03 lampret`
60			`// Development version of RTL. Libraries are missing.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "defines.v"
68
69			`module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);`
70
71			parameter width = `OPERAND_WIDTH;
72
73			`//`
74			`// I/O`
75			`//`
76			`input clk;`
77			`input rst;`
78			`input [width-1:0] a;`
79			`input [width-1:0] b;`
80			`input [width-1:0] mult_mac_result;`
81			`input macrc_op;`
82			input [`ALUOP_WIDTH-1:0] alu_op;
83			input [`SHROTOP_WIDTH-1:0] shrot_op;
84			input [`COMPOP_WIDTH-1:0] comp_op;
85			`output [width-1:0] result;`
86			`output flag;`
87
88			`//`
89			`// Internal wires and regs`
90			`//`
91			`reg [width-1:0] result;`
92			`reg [width-1:0] shifted_rotated;`
93			`reg flagforw;`
94			`reg flag_we;`
95			`reg flag;`
96			`integer d1;`
97			`integer d2;`
98			`wire [width-1:0] comp_a;`
99			`wire [width-1:0] comp_b;`
100			`wire a_eq_b;`
101			`wire a_lt_b;`
102
103			`//`
104			`// Combinatorial logic`
105			`//`
106			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
107			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
108			`assign a_eq_b = (comp_a == comp_b);`
109			`assign a_lt_b = (comp_a < comp_b);`
110
111			`//`
112			`// Simulation check for bad ALU behavior`
113			`//`
114			`ifdef OR1200_WARNINGS
115			`// synopsys translate_off`
116			`always @(result) begin`
117			`if (result === 32'bx)`
118			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
119			`end`
120			`// synopsys translate_on`
121			`endif
122
123			`//`
124			`// Central part of the ALU`
125			`//`
126			`always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin`
127			`casex (alu_op) // synopsys parallel_case full_case`
128			`ALUOP_SHROT : begin
129			`result = shifted_rotated;`
130			`flag_we = 1'b0;`
131			`end`
132			`ALUOP_ADD : begin
133			`result = a + b;`
134			`flag_we = 1'b0;`
135			`end`
136			`ALUOP_SUB : begin
137			`result = a - b;`
138			`flag_we = 1'b0;`
139			`end`
140			`ALUOP_XOR : begin
141			`result = a ^ b;`
142			`flag_we = 1'b0;`
143			`end`
144			`ALUOP_OR : begin
145			`result = a \| b;`
146			`flag_we = 1'b0;`
147			`end`
148			`ALUOP_IMM : begin
149			`result = b;`
150			`flag_we = 1'b0;`
151			`end`
152			`ALUOP_MOVHI : begin
153			`if (macrc_op) begin`
154			`result = mult_mac_result;`
155			`flag_we = 1'b0;`
156			`end`
157			`else begin`
158			`result = b << 16;`
159			`flag_we = 1'b0;`
160			`end`
161			`end`
162			`ALUOP_MUL : begin
163			`result = mult_mac_result;`
164			`ifdef OR1200_VERBOSE
165			`// synopsys translate_off`
166			`$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);`
167			`// synopsys translate_on`
168			`endif
169			`flag_we = 1'b0;`
170			`end`
171			`// synopsys translate_off`
172			`ifdef SIM_ALU_DIV
173			`ALUOP_DIV : begin
174			`d1 = a;`
175			`d2 = b;`
176			`$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);`
177			`if (d2)`
178			`result = d1 / d2;`
179			`else`
180			`result = 32'h00000000;`
181			`flag_we = 1'b0;`
182			`end`
183			`endif
184			`ifdef SIM_ALU_DIVU
185			`ALUOP_DIVU : begin
186			`if (b)`
187			`result = a / b;`
188			`else`
189			`result = 32'h00000000;`
190			`flag_we = 1'b0;`
191			`end`
192			`endif
193			`// synopsys translate_on`
194			`ALUOP_COMP: begin
195			`flag_we = 1'b1;`
196			`result = 32'd0;`
197			`end`
198	217	lampret	default : begin // `ALUOP_AND
199	218	lampret	`result = a & b;`
200			`flag_we = 1'b0;`
201			`end`
202			`endcase`
203			`end`
204
205			`//`
206			`// Shifts and rotation`
207			`//`
208			`always @(shrot_op or a or b) begin`
209	217	lampret	`case (shrot_op) // synopsys parallel_case`
210	218	lampret	`SHROTOP_SLL :
211			`shifted_rotated = (a << b[4:0]);`
212			`SHROTOP_SRL :
213			`shifted_rotated = (a >> b[4:0]);`
214			`ifdef IMPL_ALU_ROTATE
215			`SHROTOP_ROR :
216			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
217			`endif
218			`default:`
219			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
220			`endcase`
221			`end`
222
223			`//`
224			`// First type of compare implementation`
225			`//`
226			`ifdef IMPL_ALU_COMP1
227			`always @(comp_op or a_eq_b or a_lt_b) begin`
228	217	lampret	`case(comp_op[2:0]) // synopsys parallel_case`
229	218	lampret	`COP_SFEQ:
230			`flagforw = a_eq_b;`
231			`COP_SFNE:
232			`flagforw = ~a_eq_b;`
233			`COP_SFGT:
234			`flagforw = ~(a_eq_b \| a_lt_b);`
235			`COP_SFGE:
236			`flagforw = ~a_lt_b;`
237			`COP_SFLT:
238			`flagforw = a_lt_b;`
239			`COP_SFLE:
240			`flagforw = a_eq_b \| a_lt_b;`
241			`// synopsys translate_off`
242			`default:`
243			`flagforw = 1'bx;`
244			`// synopsys translate_on`
245			`endcase`
246			`end`
247			`endif
248
249			`//`
250			`// Second type of compare implementation`
251			`//`
252			`ifdef IMPL_ALU_COMP2
253			`always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin`
254	217	lampret	`case(comp_op[2:0]) // synopsys parallel_case`
255	218	lampret	`COP_SFEQ:
256			`flagforw = (comp_a == comp_b);`
257			`COP_SFNE:
258			`flagforw = (comp_a != comp_b);`
259			`COP_SFGT:
260			`flagforw = (comp_a > comp_b);`
261			`COP_SFGE:
262			`flagforw = (comp_a >= comp_b);`
263			`COP_SFLT:
264			`flagforw = (comp_a < comp_b);`
265			`COP_SFLE:
266			`flagforw = (comp_a <= comp_b);`
267			`// synopsys translate_off`
268			`default:`
269			`flagforw = 1'bx;`
270			`// synopsys translate_on`
271			`endcase`
272			`end`
273			`endif
274
275			`//`
276			`// Flag bit`
277			`//`
278			`always @(posedge clk or posedge rst) begin`
279			`if (rst)`
280			`flag <= #1 1'b0;`
281			`else if (flag_we) begin`
282			`ifdef OR1200_VERBOSE
283			`// synopsys translate_off`
284			`$display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);`
285			`// synopsys translate_on`
286			`endif
287			`flag <= #1 flagforw;`
288			`end`
289			`end`
290
291			`endmodule`

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