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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`ALUOP_WIDTH-1:0]       alu_op;
input   [`SHROTOP_WIDTH-1:0]     shrot_op;
input   [`COMPOP_WIDTH-1:0]      comp_op;
output  [width-1:0]              result;
output                          flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg                             flagforw;
reg                             flag_we;
reg                             flag;
integer                         d1;
integer                         d2;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
wire                            a_eq_b;
wire                            a_lt_b;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin
        casex (alu_op)          // synopsys parallel_case full_case
                `ALUOP_SHROT : begin
                                result = shifted_rotated;
                                flag_we = 1'b0;
                end
                `ALUOP_ADD : begin
                                result = a + b;
                                flag_we = 1'b0;
                end
                `ALUOP_SUB : begin
                                result = a - b;
                                flag_we = 1'b0;
                end
                `ALUOP_XOR : begin
                                result = a ^ b;
                                flag_we = 1'b0;
                end
                `ALUOP_OR  : begin
                                result = a | b;
                                flag_we = 1'b0;
                end
                `ALUOP_IMM : begin
                                result = b;
                                flag_we = 1'b0;
                end
                `ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                        flag_we = 1'b0;
                                end
                                else begin
                                        result = b << 16;
                                        flag_we = 1'b0;
                                end
                end
                `ALUOP_MUL : begin
                                result = mult_mac_result;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
// synopsys translate_on
`endif
                                flag_we = 1'b0;
                end
// synopsys translate_off
`ifdef SIM_ALU_DIV
                `ALUOP_DIV : begin
                                d1 = a;
                                d2 = b;
                                $display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
                                if (d2)
                                        result = d1 / d2;
                                else
                                        result = 32'h00000000;
                                flag_we = 1'b0;
                end
`endif
`ifdef SIM_ALU_DIVU
                `ALUOP_DIVU : begin
                                if (b)
                                        result = a / b;
                                else
                                        result = 32'h00000000;
                                flag_we = 1'b0;
                end
`endif
// synopsys translate_on
                `ALUOP_COMP: begin
                                flag_we = 1'b1;
                                result = 32'd0;
                end
                default : begin // `ALUOP_AND
                                result = a & b;
                                flag_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
                `SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
`ifdef IMPL_ALU_ROTATE
                `SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `COP_SFEQ:
                        flagforw = a_eq_b;
                `COP_SFNE:
                        flagforw = ~a_eq_b;
                `COP_SFGT:
                        flagforw = ~(a_eq_b | a_lt_b);
                `COP_SFGE:
                        flagforw = ~a_lt_b;
                `COP_SFLT:
                        flagforw = a_lt_b;
                `COP_SFLE:
                        flagforw = a_eq_b | a_lt_b;
// synopsys translate_off
                default:
                        flagforw = 1'bx;
// synopsys translate_on
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef IMPL_ALU_COMP2
always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `COP_SFEQ:
                        flagforw = (comp_a == comp_b);
                `COP_SFNE:
                        flagforw = (comp_a != comp_b);
                `COP_SFGT:
                        flagforw = (comp_a > comp_b);
                `COP_SFGE:
                        flagforw = (comp_a >= comp_b);
                `COP_SFLT:
                        flagforw = (comp_a < comp_b);
                `COP_SFLE:
                        flagforw = (comp_a <= comp_b);
// synopsys translate_off
                default:
                        flagforw = 1'bx;
// synopsys translate_on
        endcase
end
`endif
 
//
// Flag bit
//
always @(posedge clk or posedge rst) begin
        if (rst)
                flag <= #1 1'b0;
        else if (flag_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);
// synopsys translate_on
`endif
                flag <= #1 flagforw;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	215	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	217	lampret	`// $Log: not supported by cvs2svn $`
47			`// Revision 1.7 2001/10/14 13:12:09 lampret`
48			`// MP3 version.`
49			`//`
50	215	lampret	`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
51			`// no message`
52			`//`
53			`// Revision 1.2 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`// Revision 1.1 2001/07/20 00:46:03 lampret`
57			`// Development version of RTL. Libraries are missing.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "defines.v"
65
66			`module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);`
67
68			parameter width = `OPERAND_WIDTH;
69
70			`//`
71			`// I/O`
72			`//`
73			`input clk;`
74			`input rst;`
75			`input [width-1:0] a;`
76			`input [width-1:0] b;`
77			`input [width-1:0] mult_mac_result;`
78			`input macrc_op;`
79			input [`ALUOP_WIDTH-1:0] alu_op;
80			input [`SHROTOP_WIDTH-1:0] shrot_op;
81			input [`COMPOP_WIDTH-1:0] comp_op;
82			`output [width-1:0] result;`
83			`output flag;`
84
85			`//`
86			`// Internal wires and regs`
87			`//`
88			`reg [width-1:0] result;`
89			`reg [width-1:0] shifted_rotated;`
90			`reg flagforw;`
91			`reg flag_we;`
92			`reg flag;`
93			`integer d1;`
94			`integer d2;`
95			`wire [width-1:0] comp_a;`
96			`wire [width-1:0] comp_b;`
97			`wire a_eq_b;`
98			`wire a_lt_b;`
99
100			`//`
101			`// Combinatorial logic`
102			`//`
103			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
104			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
105			`assign a_eq_b = (comp_a == comp_b);`
106			`assign a_lt_b = (comp_a < comp_b);`
107
108			`//`
109			`// Simulation check for bad ALU behavior`
110			`//`
111			`ifdef OR1200_WARNINGS
112			`// synopsys translate_off`
113			`always @(result) begin`
114			`if (result === 32'bx)`
115			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
116			`end`
117			`// synopsys translate_on`
118			`endif
119
120			`//`
121			`// Central part of the ALU`
122			`//`
123			`always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin`
124			`casex (alu_op) // synopsys parallel_case full_case`
125			`ALUOP_SHROT : begin
126			`result = shifted_rotated;`
127			`flag_we = 1'b0;`
128			`end`
129			`ALUOP_ADD : begin
130			`result = a + b;`
131			`flag_we = 1'b0;`
132			`end`
133			`ALUOP_SUB : begin
134			`result = a - b;`
135			`flag_we = 1'b0;`
136			`end`
137			`ALUOP_XOR : begin
138			`result = a ^ b;`
139			`flag_we = 1'b0;`
140			`end`
141			`ALUOP_OR : begin
142			`result = a \| b;`
143			`flag_we = 1'b0;`
144			`end`
145			`ALUOP_IMM : begin
146			`result = b;`
147			`flag_we = 1'b0;`
148			`end`
149			`ALUOP_MOVHI : begin
150			`if (macrc_op) begin`
151			`result = mult_mac_result;`
152			`flag_we = 1'b0;`
153			`end`
154			`else begin`
155			`result = b << 16;`
156			`flag_we = 1'b0;`
157			`end`
158			`end`
159			`ALUOP_MUL : begin
160			`result = mult_mac_result;`
161			`ifdef OR1200_VERBOSE
162			`// synopsys translate_off`
163			`$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);`
164			`// synopsys translate_on`
165			`endif
166			`flag_we = 1'b0;`
167			`end`
168			`// synopsys translate_off`
169			`ifdef SIM_ALU_DIV
170			`ALUOP_DIV : begin
171			`d1 = a;`
172			`d2 = b;`
173			`$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);`
174			`if (d2)`
175			`result = d1 / d2;`
176			`else`
177			`result = 32'h00000000;`
178			`flag_we = 1'b0;`
179			`end`
180			`endif
181			`ifdef SIM_ALU_DIVU
182			`ALUOP_DIVU : begin
183			`if (b)`
184			`result = a / b;`
185			`else`
186			`result = 32'h00000000;`
187			`flag_we = 1'b0;`
188			`end`
189			`endif
190			`// synopsys translate_on`
191			`ALUOP_COMP: begin
192			`flag_we = 1'b1;`
193			`result = 32'd0;`
194			`end`
195	217	lampret	default : begin // `ALUOP_AND
196			`result = a & b;`
197			`flag_we = 1'b0;`
198			`end`
199	215	lampret	`endcase`
200			`end`
201
202			`//`
203			`// Shifts and rotation`
204			`//`
205			`always @(shrot_op or a or b) begin`
206	217	lampret	`case (shrot_op) // synopsys parallel_case`
207	215	lampret	`SHROTOP_SLL :
208			`shifted_rotated = (a << b[4:0]);`
209			`SHROTOP_SRL :
210			`shifted_rotated = (a >> b[4:0]);`
211			`ifdef IMPL_ALU_ROTATE
212			`SHROTOP_ROR :
213			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
214			`endif
215			`default:`
216			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
217			`endcase`
218			`end`
219
220			`//`
221			`// First type of compare implementation`
222			`//`
223			`ifdef IMPL_ALU_COMP1
224			`always @(comp_op or a_eq_b or a_lt_b) begin`
225	217	lampret	`case(comp_op[2:0]) // synopsys parallel_case`
226	215	lampret	`COP_SFEQ:
227			`flagforw = a_eq_b;`
228			`COP_SFNE:
229			`flagforw = ~a_eq_b;`
230			`COP_SFGT:
231			`flagforw = ~(a_eq_b \| a_lt_b);`
232			`COP_SFGE:
233			`flagforw = ~a_lt_b;`
234			`COP_SFLT:
235			`flagforw = a_lt_b;`
236			`COP_SFLE:
237			`flagforw = a_eq_b \| a_lt_b;`
238			`// synopsys translate_off`
239			`default:`
240			`flagforw = 1'bx;`
241			`// synopsys translate_on`
242			`endcase`
243			`end`
244			`endif
245
246			`//`
247			`// Second type of compare implementation`
248			`//`
249			`ifdef IMPL_ALU_COMP2
250			`always @(comp_op or a_eq_b or a_lt_b or comp_a or comp_b) begin`
251	217	lampret	`case(comp_op[2:0]) // synopsys parallel_case`
252	215	lampret	`COP_SFEQ:
253			`flagforw = (comp_a == comp_b);`
254			`COP_SFNE:
255			`flagforw = (comp_a != comp_b);`
256			`COP_SFGT:
257			`flagforw = (comp_a > comp_b);`
258			`COP_SFGE:
259			`flagforw = (comp_a >= comp_b);`
260			`COP_SFLT:
261			`flagforw = (comp_a < comp_b);`
262			`COP_SFLE:
263			`flagforw = (comp_a <= comp_b);`
264			`// synopsys translate_off`
265			`default:`
266			`flagforw = 1'bx;`
267			`// synopsys translate_on`
268			`endcase`
269			`end`
270			`endif
271
272			`//`
273			`// Flag bit`
274			`//`
275			`always @(posedge clk or posedge rst) begin`
276			`if (rst)`
277			`flag <= #1 1'b0;`
278			`else if (flag_we) begin`
279			`ifdef OR1200_VERBOSE
280			`// synopsys translate_off`
281			`$display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);`
282			`// synopsys translate_on`
283			`endif
284			`flag <= #1 flagforw;`
285			`end`
286			`end`
287
288			`endmodule`

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