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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's CPU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "general.h"
`include "alu_defs.h"
 
module cpu(
        // Clk & Rst
        clk, rst,
 
        // Insn interface
        ic_insn, ic_pcaddr, ic_stall,
 
        // Trace port
        tp_dir_in, tp_sel, tp_in, tp_out,
 
        // Data interface
        dclsu_stall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop,
 
        // Interrupt exceptions
        int_high, int_low,
 
        // SPR interface
        spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm, spr_cs, spr_we,
 
        // Trace port
        tp2w, tp3w, tp4w, tpdw
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `REGFILE_ADDR_WIDTH;
 
//
// I/O ports
//
 
// Clk & Rst
input                   clk;
input                   rst;
 
// Insn interface
input [31:0]             ic_insn;
output [31:0]            ic_pcaddr;
input                   ic_stall;
 
// Trace
input                   tp_dir_in;
input [1:0]              tp_sel;
input [31:0]             tp_in;
output [31:0]            tp_out;
 
// Data interface
input                   dclsu_stall;
output [31:0]            dclsu_addr;
input [31:0]             dclsu_datain;
output [31:0]            dclsu_dataout;
output [`LSUOP_WIDTH-1:0] dclsu_lsuop;
 
// SPR interface
input [dw-1:0]           spr_dat_pic;
input [dw-1:0]           spr_dat_tt;
input [dw-1:0]           spr_dat_pm;
output [dw-1:0]          spr_addr;
output [dw-1:0]          spr_dataout;
output [31:0]            spr_cs;
output                  spr_we;
 
// Trace
output [`TP2W_WIDTH-1:0] tp2w;
output [`TP3W_WIDTH-1:0] tp3w;
output [`TP4W_WIDTH-1:0] tp4w;
output [31:0] tpdw;
wire [31:0] tpdw;
 
// Interrupt exceptions
input int_high, int_low;
 
//
// Internal wires
//
wire [31:0]              insn;
wire [31:0]              if_pc;
wire [31:2]             lr_sav;
wire [aw-1:0] #(1)       rf_addrw;
wire [aw-1:0]            rf_addra;
wire [aw-1:0]            rf_addrb;
wire [dw-1:0]            simm;
wire [dw-1:2]           branch_addrofs;
wire [`ALUOP_WIDTH-1:0] alu_op;
wire [`SHROTOP_WIDTH-1:0] shrot_op;
wire [`COMPOP_WIDTH-1:0] comp_op;
wire [`BRANCHOP_WIDTH-1:0] branch_op;
wire [`LSUOP_WIDTH-1:0]  lsu_op;
wire                    pipeline_freeze;
 
wire [`SEL_WIDTH-1:0]    sel_a;
wire [`SEL_WIDTH-1:0]    sel_b;
wire [`RFWBOP_WIDTH-1:0] #(1) rfwb_op;
 
wire [dw-1:0] #(1)       rf_dataw;
wire [dw-1:0]            rf_dataa;
wire [dw-1:0]            rf_datab;
wire [dw-1:0]            muxed_b;
wire [dw-1:0]            wb_forw;
wire                    wbforw_valid;
 
wire [dw-1:0]            operand_a;
wire [dw-1:0]            operand_b;
wire [dw-1:0]            alu_dataout;
wire [dw-1:0]            lsu_dataout;
wire [dw-1:0]            sprs_dataout;
wire [31:0]              lsu_addrofs;
wire [`MULTICYCLE_WIDTH-1:0] multicycle;
 
wire [`EXCEPT_WIDTH-1:0] except_type;
wire                    except_flushpipe;
wire                    branch_taken;
 
wire                    flag;
wire                    lsu_stall;
wire                    branch_stall;
 
wire                    epcr_we;
wire                    eear_we;
wire                    esr_we;
wire [31:0]              epcr;
wire [31:0]              eear;
wire [`SR_WIDTH-1:0]     esr;
wire [`SR_WIDTH-1:0]     sr;
wire                    except_start;
wire                    except_started;
wire [31:0]              wb_pc;
wire [31:0]              wb_insn;
wire [31:0]              tp_insn;
wire                    tp_wr_insn;
 
// Trace port
wire [31:0]              rfa_tqa;
wire [31:0]              rfb_tqa;
wire [`TP1R_WIDTH-1:0]   rfa_tmuxed;
wire [`TP1R_WIDTH-1:0]   rfb_tmuxed;
wire [`TP1W_WIDTH-1:0]   tp1w;
 
//
// Instantiation of exception block
//
except except(
        .clk(clk),
        .rst(rst),
        .sig_dtlbmiss(1'b0),
        .sig_dmmufault(1'b0),
        .sig_inthigh(int_high),
        .sig_syscall(1'b0),
        .sig_itlbmiss(1'b0),
        .sig_immufault(1'b0),
        .sig_intlow(int_low),
        .branch_taken(branch_taken),
        .pipeline_freeze(pipeline_freeze),
        .ic_stall(ic_stall),
        .if_pc(if_pc),
        .lr_sav(lr_sav),
        .except_flushpipe(except_flushpipe),
        .except_type(except_type),
        .except_start(except_start),
        .except_started(except_started),
        .wb_pc(wb_pc),
 
        .datain(operand_b),
        .epcr_we(epcr_we),
        .eear_we(eear_we),
        .esr_we(esr_we),
        .epcr(epcr),
        .eear(eear),
        .esr(esr),
 
        .lsu_addr(dclsu_addr),
        .sr(sr)
);
 
//
// Instantiation of instruction fetch block
//
ifetch ifetch(
        .clk(clk),
        .rst(rst),
        .ic_insn(ic_insn),
        .ic_pcaddr(ic_pcaddr),
        .ic_stall(ic_stall),
        .tp_insn(tp_insn),
        .tp_wr_insn(tp_wr_insn),
        .pipeline_freeze(pipeline_freeze),
        .if_insn(insn),
        .if_pc(if_pc),
        .branch_op(branch_op),
        .except_type(except_type),
        .except_start(except_start),
        .branch_addrofs(branch_addrofs),
        .lr_restor(operand_b),
        .flag(flag),
        .taken(branch_taken),
        .binsn_addr(lr_sav),
        .epcr(epcr)
);
 
//
// Instantiation of instruction decode/control logic
//
id id(
        .clk(clk),
        .rst(rst),
        .pipeline_freeze(pipeline_freeze),
        .except_flushpipe(except_flushpipe),
        .if_insn(insn),
        .branch_op(branch_op),
        .rf_addra(rf_addra),
        .rf_addrb(rf_addrb),
        .alu_op(alu_op),
        .shrot_op(shrot_op),
        .comp_op(comp_op),
        .rf_addrw(rf_addrw),
        .rfwb_op(rfwb_op),
        .wb_insn(wb_insn),
        .simm(simm),
        .branch_addrofs(branch_addrofs),
        .lsu_addrofs(lsu_addrofs),
        .sel_a(sel_a),
        .sel_b(sel_b),
        .lsu_op(lsu_op),
        .multicycle(multicycle),
        .branch_stall(branch_stall),
        .wbforw_valid(wbforw_valid)
);
 
//
// Instantiation of write-back muxes
//
wbmux wbmux(
        .clk(clk),
        .rst(rst),
        .pipeline_freeze(pipeline_freeze),
        .rfwb_op(rfwb_op),
        .muxin_a(alu_dataout),
        .muxin_b(lsu_dataout),
        .muxin_c(sprs_dataout),
        .muxin_d({lr_sav, 2'b0}),
        .muxout(rf_dataw),
        .muxreg(wb_forw),
        .muxreg_valid(wbforw_valid)
);
 
//
// Instantiation of register file
//
rf rf(
        .clk(clk),
        .rst(rst),
        .addrw(rf_addrw),
        .dataw(rf_dataw),
        .pipeline_freeze(pipeline_freeze),
        .we(rfwb_op[0]),
        .addra(rf_addra),
        .dataa(rf_dataa),
        .addrb(rf_addrb),
        .datab(rf_datab),
        .rfa_tqa(rfa_tqa),
        .rfb_tqa(rfb_tqa),
        .rfa_tmuxed(rfa_tmuxed),
        .rfb_tmuxed(rfb_tmuxed),
        .tp1w(tp1w),
        .tpdw(tpdw)
);
 
//
// Instantiation of operand muxes
//
operandmuxes operandmuxes(
        .clk(clk),
        .rst(rst),
        .pipeline_freeze(pipeline_freeze),
        .rf_dataa(rf_dataa),
        .rf_datab(rf_datab),
        .ex_forw(rf_dataw),
        .wb_forw(wb_forw),
        .simm(simm),
        .sel_a(sel_a),
        .sel_b(sel_b),
        .operand_a(operand_a),
        .operand_b(operand_b),
        .muxed_b(muxed_b)
);
 
//
// Instantiation of CPU's ALU
//
alu alu(
        .clk(clk),
        .rst(rst),
        .a(operand_a),
        .b(operand_b),
        .alu_op(alu_op),
        .shrot_op(shrot_op),
        .comp_op(comp_op),
        .result(alu_dataout),
        .flag(flag)
);
 
//
// Instantiation of CPU's SPRS block
//
sprs sprs(
        .clk(clk),
        .rst(rst),
        .a(operand_a),
        .b(operand_b),
        .alu_op(alu_op),
        .flag(flag),
        .dtlb_we(),
        .to_wbmux(sprs_dataout),
 
        .spr_addr(spr_addr),
        .spr_dat_pic(spr_dat_pic),
        .spr_dat_tt(spr_dat_tt),
        .spr_dat_pm(spr_dat_pm),
        .spr_dataout(spr_dataout),
        .spr_cs(spr_cs),
        .spr_we(spr_we),
 
        .epcr_we(epcr_we),
        .eear_we(eear_we),
        .esr_we(esr_we),
        .epcr(epcr),
        .eear(eear),
        .esr(esr),
        .except_start(except_start),
        .except_started(except_started),
 
        .sr(sr),
        .branch_op(branch_op)
);
 
//
// Instantiation of load/store unit
//
lsu lsu(
        .clk(clk),
        .rst(rst),
        .addrbase(operand_a),
        .addrofs(lsu_addrofs),
        .lsu_op(lsu_op),
        .lsu_datain(operand_b),
        .lsu_dataout(lsu_dataout),
        .lsu_stall(lsu_stall),
        .dc_stall(dclsu_stall),
        .dc_addr(dclsu_addr),
        .dc_datain(dclsu_datain),
        .dc_dataout(dclsu_dataout),
        .dc_lsuop(dclsu_lsuop)
);
 
//
// Instantiation of freeze logic
//
frz_logic frz_logic(
        .clk(clk),
        .rst(rst),
        .multicycle(multicycle),
        .except_flushpipe(except_flushpipe),
        .lsu_stall(lsu_stall),
        .ic_stall(ic_stall),
        .branch_stall(branch_stall),
        .pipeline_freeze(pipeline_freeze)
);
 
//
// Instantiation of Trace port
//
traceport traceport(
        // Trace port connection to outside world         
        .tp_dir_in(tp_dir_in),
        .tp_sel(tp_sel),
        .tp_in(tp_in),
        .tp_out(tp_out),
 
        // Trace sources coming from RISC core
        .rst(rst),
        .rfa_tqa(rfa_tqa),
        .rfb_tqa(rfb_tqa),
        .rfa_tmuxed(rfa_tmuxed),
        .rfb_tmuxed(rfb_tmuxed),
        .wb_pc(wb_pc),
        .wb_insn(wb_insn),
        .wb_forw(wb_forw),
 
        // To RISC core
        .wr_insn(tp_wr_insn),
        .insn(tp_insn),
        .tp1w(tp1w),
        .tp2w(tp2w),
        .tp3w(tp3w),
        .tp4w(tp4w),
        .tpdw(tpdw)
);
 
endmodule
 
 

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [cpu.v] - Blame information for rev 161

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's CPU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////`
10			`//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`//`
49
50			`include "general.h"
51			`include "alu_defs.h"
52
53			`module cpu(`
54			`// Clk & Rst`
55			`clk, rst,`
56
57			`// Insn interface`
58			`ic_insn, ic_pcaddr, ic_stall,`
59
60			`// Trace port`
61			`tp_dir_in, tp_sel, tp_in, tp_out,`
62
63			`// Data interface`
64			`dclsu_stall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop,`
65
66			`// Interrupt exceptions`
67			`int_high, int_low,`
68
69			`// SPR interface`
70			`spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm, spr_cs, spr_we,`
71
72			`// Trace port`
73			`tp2w, tp3w, tp4w, tpdw`
74			`);`
75
76			parameter dw = `OPERAND_WIDTH;
77			parameter aw = `REGFILE_ADDR_WIDTH;
78
79			`//`
80			`// I/O ports`
81			`//`
82
83			`// Clk & Rst`
84			`input clk;`
85			`input rst;`
86
87			`// Insn interface`
88			`input [31:0] ic_insn;`
89			`output [31:0] ic_pcaddr;`
90			`input ic_stall;`
91
92			`// Trace`
93			`input tp_dir_in;`
94			`input [1:0] tp_sel;`
95			`input [31:0] tp_in;`
96			`output [31:0] tp_out;`
97
98			`// Data interface`
99			`input dclsu_stall;`
100			`output [31:0] dclsu_addr;`
101			`input [31:0] dclsu_datain;`
102			`output [31:0] dclsu_dataout;`
103			output [`LSUOP_WIDTH-1:0] dclsu_lsuop;
104
105			`// SPR interface`
106			`input [dw-1:0] spr_dat_pic;`
107			`input [dw-1:0] spr_dat_tt;`
108			`input [dw-1:0] spr_dat_pm;`
109			`output [dw-1:0] spr_addr;`
110			`output [dw-1:0] spr_dataout;`
111			`output [31:0] spr_cs;`
112			`output spr_we;`
113
114			`// Trace`
115			output [`TP2W_WIDTH-1:0] tp2w;
116			output [`TP3W_WIDTH-1:0] tp3w;
117			output [`TP4W_WIDTH-1:0] tp4w;
118			`output [31:0] tpdw;`
119			`wire [31:0] tpdw;`
120
121			`// Interrupt exceptions`
122			`input int_high, int_low;`
123
124			`//`
125			`// Internal wires`
126			`//`
127			`wire [31:0] insn;`
128			`wire [31:0] if_pc;`
129			`wire [31:2] lr_sav;`
130			`wire [aw-1:0] #(1) rf_addrw;`
131			`wire [aw-1:0] rf_addra;`
132			`wire [aw-1:0] rf_addrb;`
133			`wire [dw-1:0] simm;`
134			`wire [dw-1:2] branch_addrofs;`
135			wire [`ALUOP_WIDTH-1:0] alu_op;
136			wire [`SHROTOP_WIDTH-1:0] shrot_op;
137			wire [`COMPOP_WIDTH-1:0] comp_op;
138			wire [`BRANCHOP_WIDTH-1:0] branch_op;
139			wire [`LSUOP_WIDTH-1:0] lsu_op;
140			`wire pipeline_freeze;`
141
142			wire [`SEL_WIDTH-1:0] sel_a;
143			wire [`SEL_WIDTH-1:0] sel_b;
144			wire [`RFWBOP_WIDTH-1:0] #(1) rfwb_op;
145
146			`wire [dw-1:0] #(1) rf_dataw;`
147			`wire [dw-1:0] rf_dataa;`
148			`wire [dw-1:0] rf_datab;`
149			`wire [dw-1:0] muxed_b;`
150			`wire [dw-1:0] wb_forw;`
151			`wire wbforw_valid;`
152
153			`wire [dw-1:0] operand_a;`
154			`wire [dw-1:0] operand_b;`
155			`wire [dw-1:0] alu_dataout;`
156			`wire [dw-1:0] lsu_dataout;`
157			`wire [dw-1:0] sprs_dataout;`
158			`wire [31:0] lsu_addrofs;`
159			wire [`MULTICYCLE_WIDTH-1:0] multicycle;
160
161			wire [`EXCEPT_WIDTH-1:0] except_type;
162			`wire except_flushpipe;`
163			`wire branch_taken;`
164
165			`wire flag;`
166			`wire lsu_stall;`
167			`wire branch_stall;`
168
169			`wire epcr_we;`
170			`wire eear_we;`
171			`wire esr_we;`
172			`wire [31:0] epcr;`
173			`wire [31:0] eear;`
174			wire [`SR_WIDTH-1:0] esr;
175			wire [`SR_WIDTH-1:0] sr;
176			`wire except_start;`
177			`wire except_started;`
178			`wire [31:0] wb_pc;`
179			`wire [31:0] wb_insn;`
180			`wire [31:0] tp_insn;`
181			`wire tp_wr_insn;`
182
183			`// Trace port`
184			`wire [31:0] rfa_tqa;`
185			`wire [31:0] rfb_tqa;`
186			wire [`TP1R_WIDTH-1:0] rfa_tmuxed;
187			wire [`TP1R_WIDTH-1:0] rfb_tmuxed;
188			wire [`TP1W_WIDTH-1:0] tp1w;
189
190			`//`
191			`// Instantiation of exception block`
192			`//`
193			`except except(`
194			`.clk(clk),`
195			`.rst(rst),`
196			`.sig_dtlbmiss(1'b0),`
197			`.sig_dmmufault(1'b0),`
198			`.sig_inthigh(int_high),`
199			`.sig_syscall(1'b0),`
200			`.sig_itlbmiss(1'b0),`
201			`.sig_immufault(1'b0),`
202			`.sig_intlow(int_low),`
203			`.branch_taken(branch_taken),`
204			`.pipeline_freeze(pipeline_freeze),`
205			`.ic_stall(ic_stall),`
206			`.if_pc(if_pc),`
207			`.lr_sav(lr_sav),`
208			`.except_flushpipe(except_flushpipe),`
209			`.except_type(except_type),`
210			`.except_start(except_start),`
211			`.except_started(except_started),`
212			`.wb_pc(wb_pc),`
213
214			`.datain(operand_b),`
215			`.epcr_we(epcr_we),`
216			`.eear_we(eear_we),`
217			`.esr_we(esr_we),`
218			`.epcr(epcr),`
219			`.eear(eear),`
220			`.esr(esr),`
221
222			`.lsu_addr(dclsu_addr),`
223			`.sr(sr)`
224			`);`
225
226			`//`
227			`// Instantiation of instruction fetch block`
228			`//`
229			`ifetch ifetch(`
230			`.clk(clk),`
231			`.rst(rst),`
232			`.ic_insn(ic_insn),`
233			`.ic_pcaddr(ic_pcaddr),`
234			`.ic_stall(ic_stall),`
235			`.tp_insn(tp_insn),`
236			`.tp_wr_insn(tp_wr_insn),`
237			`.pipeline_freeze(pipeline_freeze),`
238			`.if_insn(insn),`
239			`.if_pc(if_pc),`
240			`.branch_op(branch_op),`
241			`.except_type(except_type),`
242			`.except_start(except_start),`
243			`.branch_addrofs(branch_addrofs),`
244			`.lr_restor(operand_b),`
245			`.flag(flag),`
246			`.taken(branch_taken),`
247			`.binsn_addr(lr_sav),`
248			`.epcr(epcr)`
249			`);`
250
251			`//`
252			`// Instantiation of instruction decode/control logic`
253			`//`
254			`id id(`
255			`.clk(clk),`
256			`.rst(rst),`
257			`.pipeline_freeze(pipeline_freeze),`
258			`.except_flushpipe(except_flushpipe),`
259			`.if_insn(insn),`
260			`.branch_op(branch_op),`
261			`.rf_addra(rf_addra),`
262			`.rf_addrb(rf_addrb),`
263			`.alu_op(alu_op),`
264			`.shrot_op(shrot_op),`
265			`.comp_op(comp_op),`
266			`.rf_addrw(rf_addrw),`
267			`.rfwb_op(rfwb_op),`
268			`.wb_insn(wb_insn),`
269			`.simm(simm),`
270			`.branch_addrofs(branch_addrofs),`
271			`.lsu_addrofs(lsu_addrofs),`
272			`.sel_a(sel_a),`
273			`.sel_b(sel_b),`
274			`.lsu_op(lsu_op),`
275			`.multicycle(multicycle),`
276			`.branch_stall(branch_stall),`
277			`.wbforw_valid(wbforw_valid)`
278			`);`
279
280			`//`
281			`// Instantiation of write-back muxes`
282			`//`
283			`wbmux wbmux(`
284			`.clk(clk),`
285			`.rst(rst),`
286			`.pipeline_freeze(pipeline_freeze),`
287			`.rfwb_op(rfwb_op),`
288			`.muxin_a(alu_dataout),`
289			`.muxin_b(lsu_dataout),`
290			`.muxin_c(sprs_dataout),`
291			`.muxin_d({lr_sav, 2'b0}),`
292			`.muxout(rf_dataw),`
293			`.muxreg(wb_forw),`
294			`.muxreg_valid(wbforw_valid)`
295			`);`
296
297			`//`
298			`// Instantiation of register file`
299			`//`
300			`rf rf(`
301			`.clk(clk),`
302			`.rst(rst),`
303			`.addrw(rf_addrw),`
304			`.dataw(rf_dataw),`
305			`.pipeline_freeze(pipeline_freeze),`
306			`.we(rfwb_op[0]),`
307			`.addra(rf_addra),`
308			`.dataa(rf_dataa),`
309			`.addrb(rf_addrb),`
310			`.datab(rf_datab),`
311			`.rfa_tqa(rfa_tqa),`
312			`.rfb_tqa(rfb_tqa),`
313			`.rfa_tmuxed(rfa_tmuxed),`
314			`.rfb_tmuxed(rfb_tmuxed),`
315			`.tp1w(tp1w),`
316			`.tpdw(tpdw)`
317			`);`
318
319			`//`
320			`// Instantiation of operand muxes`
321			`//`
322			`operandmuxes operandmuxes(`
323			`.clk(clk),`
324			`.rst(rst),`
325			`.pipeline_freeze(pipeline_freeze),`
326			`.rf_dataa(rf_dataa),`
327			`.rf_datab(rf_datab),`
328			`.ex_forw(rf_dataw),`
329			`.wb_forw(wb_forw),`
330			`.simm(simm),`
331			`.sel_a(sel_a),`
332			`.sel_b(sel_b),`
333			`.operand_a(operand_a),`
334			`.operand_b(operand_b),`
335			`.muxed_b(muxed_b)`
336			`);`
337
338			`//`
339			`// Instantiation of CPU's ALU`
340			`//`
341			`alu alu(`
342			`.clk(clk),`
343			`.rst(rst),`
344			`.a(operand_a),`
345			`.b(operand_b),`
346			`.alu_op(alu_op),`
347			`.shrot_op(shrot_op),`
348			`.comp_op(comp_op),`
349			`.result(alu_dataout),`
350			`.flag(flag)`
351			`);`
352
353			`//`
354			`// Instantiation of CPU's SPRS block`
355			`//`
356			`sprs sprs(`
357			`.clk(clk),`
358			`.rst(rst),`
359			`.a(operand_a),`
360			`.b(operand_b),`
361			`.alu_op(alu_op),`
362			`.flag(flag),`
363			`.dtlb_we(),`
364			`.to_wbmux(sprs_dataout),`
365
366			`.spr_addr(spr_addr),`
367			`.spr_dat_pic(spr_dat_pic),`
368			`.spr_dat_tt(spr_dat_tt),`
369			`.spr_dat_pm(spr_dat_pm),`
370			`.spr_dataout(spr_dataout),`
371			`.spr_cs(spr_cs),`
372			`.spr_we(spr_we),`
373
374			`.epcr_we(epcr_we),`
375			`.eear_we(eear_we),`
376			`.esr_we(esr_we),`
377			`.epcr(epcr),`
378			`.eear(eear),`
379			`.esr(esr),`
380			`.except_start(except_start),`
381			`.except_started(except_started),`
382
383			`.sr(sr),`
384			`.branch_op(branch_op)`
385			`);`
386
387			`//`
388			`// Instantiation of load/store unit`
389			`//`
390			`lsu lsu(`
391			`.clk(clk),`
392			`.rst(rst),`
393			`.addrbase(operand_a),`
394			`.addrofs(lsu_addrofs),`
395			`.lsu_op(lsu_op),`
396			`.lsu_datain(operand_b),`
397			`.lsu_dataout(lsu_dataout),`
398			`.lsu_stall(lsu_stall),`
399			`.dc_stall(dclsu_stall),`
400			`.dc_addr(dclsu_addr),`
401			`.dc_datain(dclsu_datain),`
402			`.dc_dataout(dclsu_dataout),`
403			`.dc_lsuop(dclsu_lsuop)`
404			`);`
405
406			`//`
407			`// Instantiation of freeze logic`
408			`//`
409			`frz_logic frz_logic(`
410			`.clk(clk),`
411			`.rst(rst),`
412			`.multicycle(multicycle),`
413			`.except_flushpipe(except_flushpipe),`
414			`.lsu_stall(lsu_stall),`
415			`.ic_stall(ic_stall),`
416			`.branch_stall(branch_stall),`
417			`.pipeline_freeze(pipeline_freeze)`
418			`);`
419
420			`//`
421			`// Instantiation of Trace port`
422			`//`
423			`traceport traceport(`
424			`// Trace port connection to outside world`
425			`.tp_dir_in(tp_dir_in),`
426			`.tp_sel(tp_sel),`
427			`.tp_in(tp_in),`
428			`.tp_out(tp_out),`
429
430			`// Trace sources coming from RISC core`
431			`.rst(rst),`
432			`.rfa_tqa(rfa_tqa),`
433			`.rfb_tqa(rfb_tqa),`
434			`.rfa_tmuxed(rfa_tmuxed),`
435			`.rfb_tmuxed(rfb_tmuxed),`
436			`.wb_pc(wb_pc),`
437			`.wb_insn(wb_insn),`
438			`.wb_forw(wb_forw),`
439
440			`// To RISC core`
441			`.wr_insn(tp_wr_insn),`
442			`.insn(tp_insn),`
443			`.tp1w(tp1w),`
444			`.tp2w(tp2w),`
445			`.tp3w(tp3w),`
446			`.tp4w(tp4w),`
447			`.tpdw(tpdw)`
448			`);`
449
450			`endmodule`
451
452