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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's CPU                                                ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////

////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////

////                                                              ////

////  To Do:                                                      ////

////   - make it smaller and faster                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.4  2001/08/17 08:01:19  lampret

// IC enable/disable.

//

// Revision 1.3  2001/08/13 03:36:20  lampret

// Added cfg regs. Moved all defines into one defines.v file. More cleanup.

//

// Revision 1.2  2001/08/09 13:39:33  lampret

// Major clean-up.

//

// Revision 1.1  2001/07/20 00:46:03  lampret

// Development version of RTL. Libraries are missing.

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "defines.v"

module cpu(

        // Clk & Rst

        clk, rst,

        // Insn interface

        ic_insn, ic_addr, ic_stall, ic_fetchop, ic_en,

        immu_en, immuexcept_miss, immuexcept_fault,

        // Trace port

        tp_dir_in, tp_sel, tp_in, tp_out,

        // Data interface

        dclsu_stall, dclsu_unstall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, dc_en,

        dmmu_en, dmmuexcept_miss, dmmuexcept_fault,

        // Interrupt exceptions

        int_high, int_low,

        // SPR interface

        supv, spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm, spr_dat_dmmu, spr_cs, spr_we,

        // Trace port

        tp2w, tp3w

);

parameter dw = `OPERAND_WIDTH;

parameter aw = `REGFILE_ADDR_WIDTH;

//

// I/O ports

//

//

// Clk & Rst

//

input                           clk;

input                           rst;

//

// Insn (IC) interface

//

input   [31:0]                   ic_insn;

output  [31:0]                   ic_addr;

input                           ic_stall;

output  [`FETCHOP_WIDTH-1:0]     ic_fetchop;

output                          ic_en;

//

// Insn (IMMU) interface

//

input                           immuexcept_miss;

input                           immuexcept_fault;

output                          immu_en;

//

// Trace

//

input                           tp_dir_in;

input   [1:0]                    tp_sel;

input   [31:0]                   tp_in;

output  [31:0]                   tp_out;

output  [`TP2W_WIDTH-1:0]        tp2w;

output  [`TP3W_WIDTH-1:0]        tp3w;

//

// Data (DC) interface

//

input                           dclsu_stall;

input                           dclsu_unstall;

output  [31:0]                   dclsu_addr;

input   [31:0]                   dclsu_datain;

output  [31:0]                   dclsu_dataout;

output  [`LSUOP_WIDTH-1:0]       dclsu_lsuop;

output                          dc_en;

//

// Data (DMMU) interface

//

input                           dmmuexcept_miss;

input                           dmmuexcept_fault;

output                          dmmu_en;

//

// SPR interface

//

input                           supv;

input   [dw-1:0]         spr_dat_pic;

input   [dw-1:0]         spr_dat_tt;

input   [dw-1:0]         spr_dat_pm;

input   [dw-1:0]         spr_dat_dmmu;

output  [dw-1:0]         spr_addr;

output  [dw-1:0]         spr_dataout;

output  [31:0]                   spr_cs;

output                          spr_we;

//

// Interrupt exceptions

//

input                           int_high;

input                           int_low;

//

// Internal wires

//

wire    [31:0]                   insn;

wire    [31:0]                   if_pc;

wire    [31:2]                  lr_sav;

wire    [aw-1:0]         rf_addrw;

wire    [aw-1:0]                 rf_addra;

wire    [aw-1:0]                 rf_addrb;

wire    [dw-1:0]         simm;

wire    [dw-1:2]                branch_addrofs;

wire    [`ALUOP_WIDTH-1:0]       alu_op;

wire    [`SHROTOP_WIDTH-1:0]     shrot_op;

wire    [`COMPOP_WIDTH-1:0]      comp_op;

wire    [`BRANCHOP_WIDTH-1:0]    branch_op;

wire    [`LSUOP_WIDTH-1:0]       lsu_op;

wire                            pipeline_freeze;

wire    [`SEL_WIDTH-1:0] sel_a;

wire    [`SEL_WIDTH-1:0] sel_b;

wire    [`RFWBOP_WIDTH-1:0]      rfwb_op;

wire    [dw-1:0]         rf_dataw;

wire    [dw-1:0]         rf_dataa;

wire    [dw-1:0]         rf_datab;

wire    [dw-1:0]         muxed_b;

wire    [dw-1:0]         wb_forw;

wire                            wbforw_valid;

wire    [dw-1:0]         operand_a;

wire    [dw-1:0]         operand_b;

wire    [dw-1:0]         alu_dataout;

wire    [dw-1:0]         lsu_dataout;

wire    [dw-1:0]         sprs_dataout;

wire    [31:0]                   lsu_addrofs;

wire    [`MULTICYCLE_WIDTH-1:0]  multicycle;

wire    [`EXCEPT_WIDTH-1:0]      except_type;

wire                            except_flushpipe;

wire                            branch_taken;

wire                            flag;

wire                            lsu_stall;

wire                            branch_stall;

wire                            epcr_we;

wire                            eear_we;

wire                            esr_we;

wire    [31:0]                   epcr;

wire    [31:0]                   eear;

wire    [`SR_WIDTH-1:0]          esr;

wire    [`SR_WIDTH-1:0]          sr;

wire                            except_start;

wire                            except_started;

wire    [31:0]                   wb_pc;

wire    [31:0]                   wb_insn;

wire    [31:0]                   tp_insn;

wire                            tp_wr_insn;

wire    [15:0]                   spr_addrimm;

wire                            sig_syscall;

wire    [31:0]                   spr_dat_cfgr;

wire                            force_dslot_fetch;

wire                            if_stall;

//

// Trace port

//

wire    [31:0]                   rfa_tqa;

wire    [31:0]                   rfb_tqa;

wire    [`TP1R_WIDTH-1:0]        rfa_tmuxed;

wire    [`TP1R_WIDTH-1:0]        rfb_tmuxed;

wire    [`TP1W_WIDTH-1:0]        tp1w;

//

// Data cache enable

//

assign dc_en = sr[`SR_DCE];

//

// Instruction cache enable

//

//assign ic_en = 1'b1;

assign ic_en = sr[`SR_ICE];

//

// DMMU enable

//

assign dmmu_en = sr[`SR_DME];

//

// IMMU enable

//

assign immu_en = sr[`SR_IME];

//

// SUPV bit

//

assign supv = sr[`SR_SUPV];

//

// Instantiation of exception block

//

except except(

        .clk(clk),

        .rst(rst),

        .sig_dtlbmiss(dmmuexcept_miss),

        .sig_dmmufault(dmmuexcept_fault),

        .sig_inthigh(int_high),

        .sig_syscall(sig_syscall),

        .sig_itlbmiss(immuexcept_miss),

        .sig_immufault(immuexcept_fault),

        .sig_intlow(int_low),

        .branch_taken(branch_taken),

        .pipeline_freeze(pipeline_freeze),

        .if_stall(if_stall),

        .if_pc(if_pc),

        .lr_sav(lr_sav),

        .except_flushpipe(except_flushpipe),

        .except_type(except_type),

        .except_start(except_start),

        .except_started(except_started),

        .wb_pc(wb_pc),

        .datain(operand_b),

        .epcr_we(epcr_we),

        .eear_we(eear_we),

        .esr_we(esr_we),

        .epcr(epcr),

        .eear(eear),

        .esr(esr),

        .lsu_addr(dclsu_addr),

        .sr(sr)

);

//

// Instantiation of instruction fetch block

//

ifetch ifetch(

        .clk(clk),

        .rst(rst),

        .ic_insn(ic_insn),

        .ic_addr(ic_addr),

        .ic_stall(ic_stall),

        .ic_fetchop(ic_fetchop),

        .tp_insn(tp_insn),

        .tp_wr_insn(tp_wr_insn),

        .pipeline_freeze(pipeline_freeze),

        .if_insn(insn),

        .if_pc(if_pc),

        .branch_op(branch_op),

        .except_type(except_type),

        .except_start(except_start),

        .branch_addrofs(branch_addrofs),

        .lr_restor(operand_b),

        .flag(flag),

        .taken(branch_taken),

        .binsn_addr(lr_sav),

        .epcr(epcr),

        .force_dslot_fetch(force_dslot_fetch),

        .if_stall(if_stall),

        .branch_stall(branch_stall)

);

//

// Instantiation of instruction decode/control logic

//

id id(

        .clk(clk),

        .rst(rst),

        .pipeline_freeze(pipeline_freeze),

        .except_flushpipe(except_flushpipe),

        .if_insn(insn),

        .branch_op(branch_op),

        .rf_addra(rf_addra),

        .rf_addrb(rf_addrb),

        .alu_op(alu_op),

        .shrot_op(shrot_op),

        .comp_op(comp_op),

        .rf_addrw(rf_addrw),

        .rfwb_op(rfwb_op),

        .wb_insn(wb_insn),

        .simm(simm),

        .branch_addrofs(branch_addrofs),

        .lsu_addrofs(lsu_addrofs),

        .sel_a(sel_a),

        .sel_b(sel_b),

        .lsu_op(lsu_op),

        .multicycle(multicycle),

        .spr_addrimm(spr_addrimm),

        .wbforw_valid(wbforw_valid),

        .sig_syscall(sig_syscall),

        .force_dslot_fetch(force_dslot_fetch)

);

//

// Instantiation of write-back muxes

//

wbmux wbmux(

        .clk(clk),

        .rst(rst),

        .pipeline_freeze(pipeline_freeze),

        .rfwb_op(rfwb_op),

        .muxin_a(alu_dataout),

        .muxin_b(lsu_dataout),

        .muxin_c(sprs_dataout),

        .muxin_d({lr_sav, 2'b0}),

        .muxout(rf_dataw),

        .muxreg(wb_forw),

        .muxreg_valid(wbforw_valid)

);

//

// Instantiation of register file

//

rf rf(

        .clk(clk),

        .rst(rst),

        .addrw(rf_addrw),

        .dataw(rf_dataw),

        .pipeline_freeze(pipeline_freeze),

        .we(rfwb_op[0]),

        .addra(rf_addra),

        .dataa(rf_dataa),

        .addrb(rf_addrb),

        .datab(rf_datab),

        .rfa_tqa(rfa_tqa),

        .rfb_tqa(rfb_tqa),

        .rfa_tmuxed(rfa_tmuxed),

        .rfb_tmuxed(rfb_tmuxed),

        .tp1w(tp1w)

);

//

// Instantiation of operand muxes

//

operandmuxes operandmuxes(

        .clk(clk),

        .rst(rst),

        .pipeline_freeze(pipeline_freeze),

        .rf_dataa(rf_dataa),

        .rf_datab(rf_datab),

        .ex_forw(rf_dataw),

        .wb_forw(wb_forw),

        .simm(simm),

        .sel_a(sel_a),

        .sel_b(sel_b),

        .operand_a(operand_a),

        .operand_b(operand_b),

        .muxed_b(muxed_b)

);

//

// Instantiation of CPU's ALU

//

alu alu(

        .clk(clk),

        .rst(rst),

        .a(operand_a),

        .b(operand_b),

        .alu_op(alu_op),

        .shrot_op(shrot_op),

        .comp_op(comp_op),

        .result(alu_dataout),

        .flag(flag)

);

//

// Instantiation of CPU's SPRS block

//

sprs sprs(

        .clk(clk),

        .rst(rst),

        .addrbase(operand_a),

        .addrofs(spr_addrimm),

        .dat_i(operand_b),

        .alu_op(alu_op),

        .flag(flag),

        .to_wbmux(sprs_dataout),

        .spr_addr(spr_addr),

        .spr_dat_pic(spr_dat_pic),

        .spr_dat_tt(spr_dat_tt),

        .spr_dat_pm(spr_dat_pm),

        .spr_dat_cfgr(spr_dat_cfgr),

        .spr_dat_dmmu(spr_dat_dmmu),

        .spr_dataout(spr_dataout),

        .spr_cs(spr_cs),

        .spr_we(spr_we),

        .epcr_we(epcr_we),

        .eear_we(eear_we),

        .esr_we(esr_we),

        .epcr(epcr),

        .eear(eear),

        .esr(esr),

        .except_start(except_start),

        .except_started(except_started),

        .sr(sr),

        .branch_op(branch_op)

);

//

// Instantiation of load/store unit

//

lsu lsu(

        .clk(clk),

        .rst(rst),

        .addrbase(operand_a),

        .addrofs(lsu_addrofs),

        .lsu_op(lsu_op),

        .lsu_datain(operand_b),

        .lsu_dataout(lsu_dataout),

        .lsu_stall(lsu_stall),

        .dc_stall(dclsu_stall),

        .dc_addr(dclsu_addr),

        .dc_datain(dclsu_datain),

        .dc_dataout(dclsu_dataout),

        .dc_lsuop(dclsu_lsuop)

);

//

// Instantiation of freeze logic

//

frz_logic frz_logic(

        .clk(clk),

        .rst(rst),

        .multicycle(multicycle),

        .except_flushpipe(except_flushpipe),

        .lsu_stall(lsu_stall),

        .if_stall(if_stall),

        .dclsu_unstall(dclsu_unstall),

        .branch_stall(branch_stall),

        .force_dslot_fetch(force_dslot_fetch),

        .pipeline_freeze(pipeline_freeze)

);

//

// Instantiation of configuration registers

//

cfgr cfgr(

        .clk(clk),

        .rst(clk),

        .spr_addr(spr_addr),

        .spr_dat_o(spr_dat_cfgr)

);

//

// Instantiation of Trace port

//

traceport traceport(

        // Trace port connection to outside world         

        .tp_dir_in(tp_dir_in),

        .tp_sel(tp_sel),

        .tp_in(tp_in),

        .tp_out(tp_out),

        // Trace sources coming from RISC core

        .rst(rst),

        .rfa_tqa(rfa_tqa),

        .rfb_tqa(rfb_tqa),

        .rfa_tmuxed(rfa_tmuxed),

        .rfb_tmuxed(rfb_tmuxed),

        .wb_pc(wb_pc),

        .wb_insn(wb_insn),

        .wb_forw(wb_forw),

        // To RISC core

        .wr_insn(tp_wr_insn),

        .insn(tp_insn),

        .tp1w(tp1w),

        .tp2w(tp2w),

        .tp3w(tp3w),

        .tp4w(),

        .tpdw()

);

endmodule