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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data Cache top level                               ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of all DC blocks.                             ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/07/22 03:31:53  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
//
// Data cache
//
 
module dc(
        // Rst, clk and clock control
        clk, rst, clkdiv_by_2,
 
        // External i/f
        dcbiu_rdy, dcbiu_datain, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dcbiu_sel,
 
        // Inernal i/f
        dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall,
 
        // Trace
        tp2w
);
 
parameter dw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
input                           clkdiv_by_2;
 
//
// External I/F
//
input                           dcbiu_rdy;
input   [dw-1:0]         dcbiu_datain;
output  [31:0]                   dcbiu_addr;
output                          dcbiu_read;
output                          dcbiu_write;
output  [3:0]                    dcbiu_sel;
 
 
//
// Internal I/F
//
input                           dc_en;
input   [31:0]                   dclsu_addr;
input   [`LSUOP_WIDTH-1:0]       dclsu_lsuop;
input   [dw-1:0]         dclsu_datain;
output  [dw-1:0]         dclsu_dataout;
output  [dw-1:0]         dcbiu_dataout;
output                          dclsu_stall;
 
//
// Trace
//
input   [`TP2W_WIDTH-1:0]        tp2w;
 
//
// Internal wires and regs
//
wire    [18:0]                   tag;
wire    [dw-1:0]         to_dcram;
wire    [dw-1:0]         from_dcram;
wire    [dw-1:0]         to_mem2reg;
wire    [31:0]                   saved_addr;
wire                            refill;
wire    [3:0]                    dcram_we;
wire                            dctag_we;
wire    [dw-1:0]         lsu_datain_memaligned;
wire    [31:0]                   dc_addr;
wire                            refill_first;
wire                            refill_prepare;
wire                            refill_start;
wire                            refill_rest;
wire    [`LSUOP_WIDTH-1:0]       dcfsm_lsuop;
wire                            dcfsm_read;
wire                            dcfsm_write;
wire    [1:0]                    mem2reg_addr;
reg                             hit;
reg     [1:0]                    valid_div;
reg     [3:0]                    dcbiu_sel;
reg     [1:0]                    bypass_wait;
wire                            queue;
wire                            cntrbusy;
wire                            dcbiu_valid;
 
//
// Simple assignments
//
assign dcbiu_addr = dc_addr;
assign dctag_we = refill;
 
//
// Data to BIU is from DCRAM when DC is enabled or from LSU when
// DC is disabled
//
assign dcbiu_dataout = (dc_en) ? from_dcram : lsu_datain_memaligned;
 
//
// Bypases of the DC when DC is disabled
//
assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
assign dcbiu_read = (dc_en) ? dcfsm_read : (dclsu_lsuop && ~dclsu_lsuop[3]);
assign dcbiu_write = (dc_en) ? dcfsm_write : (dclsu_lsuop && dclsu_lsuop[3]);
always @(dc_en or dclsu_lsuop or dclsu_addr)
        casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})
                {1'b0, `LSUOP_SB, 2'b00} : dcbiu_sel <= #1 4'b1000;
                {1'b0, `LSUOP_SB, 2'b01} : dcbiu_sel <= #1 4'b0100;
                {1'b0, `LSUOP_SB, 2'b10} : dcbiu_sel <= #1 4'b0010;
                {1'b0, `LSUOP_SB, 2'b11} : dcbiu_sel <= #1 4'b0001;
                {1'b0, `LSUOP_SH, 2'b00} : dcbiu_sel <= #1 4'b1100;
                {1'b0, `LSUOP_SH, 2'b10} : dcbiu_sel <= #1 4'b0011;
                {1'b0, `LSUOP_SW, 2'b00} : dcbiu_sel <= #1 4'b1111;
                {1'b0, `LSUOP_LBZ, 2'b00}, {1'b0, `LSUOP_LBS, 2'b00} : dcbiu_sel <= #1 4'b1000;
                {1'b0, `LSUOP_LBZ, 2'b01}, {1'b0, `LSUOP_LBS, 2'b01} : dcbiu_sel <= #1 4'b0100;
                {1'b0, `LSUOP_LBZ, 2'b10}, {1'b0, `LSUOP_LBS, 2'b10} : dcbiu_sel <= #1 4'b0010;
                {1'b0, `LSUOP_LBZ, 2'b11}, {1'b0, `LSUOP_LBS, 2'b11} : dcbiu_sel <= #1 4'b0001;
                {1'b0, `LSUOP_LHZ, 2'b00}, {1'b0, `LSUOP_LHS, 2'b00} : dcbiu_sel <= #1 4'b1100;
                {1'b0, `LSUOP_LHZ, 2'b10}, {1'b0, `LSUOP_LHS, 2'b10} : dcbiu_sel <= #1 4'b0011;
                {1'b0, `LSUOP_LWZ, 2'b00}, {1'b0, `LSUOP_LWS, 2'b00} : dcbiu_sel <= #1 4'b1111;
                7'b1xxxxxx : dcbiu_sel <= #1 4'b1111;
                default : dcbiu_sel <= #1 4'b0000;
        endcase
 
assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];
 
//
// Wait for DC bypass acess
//
always @(posedge rst or posedge clk)
        if (rst)
                bypass_wait <= #1 2'b0;
        else if (dcbiu_valid)
                bypass_wait <= #1 2'b0;
        else if (dcbiu_read | dcbiu_write)
                bypass_wait <= #1 {bypass_wait, 1'b1};
        else
                bypass_wait <= #1 2'b00;
 
//
// Queue
//
assign queue = (refill && dcfsm_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;
 
//
// DC/LSU stall
//
assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid);
 
//
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
//
assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;
 
//
// Select between input data generated by LSU or by BIU
//
assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;
 
//
// Select between data generated by DCRAM or passed by BIU
//
assign to_mem2reg = (refill_first == 1'b1) | (~dc_en) ? dcbiu_datain : from_dcram;
 
//
// Tag comparison
//
always @(tag or saved_addr) begin
        if (tag == saved_addr[31:13])
                hit <= #1 1'b1;
        else
                hit <= #1 1'b0;
end
 
//
// Valid_div counts RISC clock cycles by modulo 4
//
always @(posedge clk or posedge rst)
        if (rst)
                valid_div <= #1 2'b0;
        else
                valid_div <= #1 valid_div + 'd1;
 
//
// dcbiu_valid is one RISC clock cycle long dcbiu_rdy.
// dcbiu_rdy is two or four RISC clock cycles long because memory
// controller works at 1/2 or 1/4 of RISC clock freq (at 1/2 if
// clkdiv_by_2 is asserted).
//
assign dcbiu_valid = dcbiu_rdy & (valid_div[1] | clkdiv_by_2) & valid_div[0];
 
//
// Generate refill_start that signals to frz_logic a cache linefill is about to begin
//
assign refill_start = (refill_prepare & ~hit) ? 1'b1 : 1'b0;
 
//
// Instantiation of DC Finite State Machine
//
dc_fsm dc_fsm(
        .clk(clk),
        .rst(rst),
        .lsu_op(dcfsm_lsuop),
        .miss(~hit),
        .biudata_valid(dcbiu_valid),
        .start_addr(dclsu_addr),
        .saved_addr(saved_addr),
        .refill(refill),
        .refill_first(refill_first),
        .refill_prepare(refill_prepare),
        .dcram_we(dcram_we),
        .biu_read(dcfsm_read),
        .biu_write(dcfsm_write),
        .refill_rest(refill_rest),
        .cntrbusy(cntrbusy)
);
 
//
// Instantiation of Regfile-to-memory aligner
//
reg2mem reg2mem(
        .addr(dc_addr[1:0]),
        .lsu_op(dclsu_lsuop),
        .regdata(dclsu_datain),
        .memdata(lsu_datain_memaligned)
);
 
//
// Instantiation of DC main memory
//
dc_ram dc_ram(
        .clk(clk),
        .rst(rst),
        .addr(dc_addr[12:2]),
        .we(dcram_we),
        .datain(to_dcram),
        .dataout(from_dcram)
);
 
//
// Instantiation of DC TAG memory
//
dc_tag dc_tag(
        .clk(clk),
        .rst(rst),
        .addr(dc_addr[12:4]),
        .we(dctag_we),
        .datain(dc_addr[31:13]),
        .dataout(tag)
);
 
//
// Instatiation of Memory-to-regfile aligner
//
mem2reg mem2reg(
        .addr(mem2reg_addr[1:0]),
        .lsu_op(dclsu_lsuop),
        .memdata(to_mem2reg),
        .regdata(dclsu_dataout)
);
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Data Cache top level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of all DC blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	168	lampret	`// Revision 1.2 2001/07/22 03:31:53 lampret`
48			`// Fixed RAM's oen bug. Cache bypass under development.`
49			`//`
50	166	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	166	lampret	`//`
54	161	lampret
55	168	lampret	`include "timescale.v"
56			`include "defines.v"
57	161	lampret
58	168	lampret	`//`
59	161	lampret	`// Data cache`
60	168	lampret	`//`
61	161	lampret
62	168	lampret	`module dc(`
63			`// Rst, clk and clock control`
64			`clk, rst, clkdiv_by_2,`
65
66			`// External i/f`
67			`dcbiu_rdy, dcbiu_datain, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dcbiu_sel,`
68
69			`// Inernal i/f`
70			`dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall,`
71
72			`// Trace`
73			`tp2w`
74	161	lampret	`);`
75
76			parameter dw = `OPERAND_WIDTH;
77
78	168	lampret	`//`
79			`// I/O`
80			`//`
81	161	lampret
82	168	lampret	`//`
83			`// Clock and reset`
84			`//`
85			`input clk;`
86			`input rst;`
87			`input clkdiv_by_2;`
88	161	lampret
89	168	lampret	`//`
90			`// External I/F`
91			`//`
92			`input dcbiu_rdy;`
93			`input [dw-1:0] dcbiu_datain;`
94			`output [31:0] dcbiu_addr;`
95			`output dcbiu_read;`
96			`output dcbiu_write;`
97			`output [3:0] dcbiu_sel;`
98	161	lampret
99
100	168	lampret	`//`
101			`// Internal I/F`
102			`//`
103			`input dc_en;`
104			`input [31:0] dclsu_addr;`
105			input [`LSUOP_WIDTH-1:0] dclsu_lsuop;
106			`input [dw-1:0] dclsu_datain;`
107			`output [dw-1:0] dclsu_dataout;`
108			`output [dw-1:0] dcbiu_dataout;`
109			`output dclsu_stall;`
110	161	lampret
111	168	lampret	`//`
112			`// Trace`
113			`//`
114			input [`TP2W_WIDTH-1:0] tp2w;
115	161	lampret
116	168	lampret	`//`
117			`// Internal wires and regs`
118			`//`
119			`wire [18:0] tag;`
120			`wire [dw-1:0] to_dcram;`
121			`wire [dw-1:0] from_dcram;`
122			`wire [dw-1:0] to_mem2reg;`
123			`wire [31:0] saved_addr;`
124			`wire refill;`
125			`wire [3:0] dcram_we;`
126			`wire dctag_we;`
127			`wire [dw-1:0] lsu_datain_memaligned;`
128			`wire [31:0] dc_addr;`
129			`wire refill_first;`
130			`wire refill_prepare;`
131			`wire refill_start;`
132			`wire refill_rest;`
133			wire [`LSUOP_WIDTH-1:0] dcfsm_lsuop;
134			`wire dcfsm_read;`
135			`wire dcfsm_write;`
136			`wire [1:0] mem2reg_addr;`
137			`reg hit;`
138			`reg [1:0] valid_div;`
139			`reg [3:0] dcbiu_sel;`
140			`reg [1:0] bypass_wait;`
141			`wire queue;`
142			`wire cntrbusy;`
143			`wire dcbiu_valid;`
144
145			`//`
146			`// Simple assignments`
147			`//`
148	161	lampret	`assign dcbiu_addr = dc_addr;`
149			`assign dctag_we = refill;`
150	168	lampret
151			`//`
152			`// Data to BIU is from DCRAM when DC is enabled or from LSU when`
153			`// DC is disabled`
154			`//`
155	166	lampret	`assign dcbiu_dataout = (dc_en) ? from_dcram : lsu_datain_memaligned;`
156	161	lampret
157	168	lampret	`//`
158			`// Bypases of the DC when DC is disabled`
159			`//`
160	166	lampret	assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
161			`assign dcbiu_read = (dc_en) ? dcfsm_read : (dclsu_lsuop && ~dclsu_lsuop[3]);`
162			`assign dcbiu_write = (dc_en) ? dcfsm_write : (dclsu_lsuop && dclsu_lsuop[3]);`
163			`always @(dc_en or dclsu_lsuop or dclsu_addr)`
164			`casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})`
165			{1'b0, `LSUOP_SB, 2'b00} : dcbiu_sel <= #1 4'b1000;
166			{1'b0, `LSUOP_SB, 2'b01} : dcbiu_sel <= #1 4'b0100;
167			{1'b0, `LSUOP_SB, 2'b10} : dcbiu_sel <= #1 4'b0010;
168			{1'b0, `LSUOP_SB, 2'b11} : dcbiu_sel <= #1 4'b0001;
169			{1'b0, `LSUOP_SH, 2'b00} : dcbiu_sel <= #1 4'b1100;
170			{1'b0, `LSUOP_SH, 2'b10} : dcbiu_sel <= #1 4'b0011;
171			{1'b0, `LSUOP_SW, 2'b00} : dcbiu_sel <= #1 4'b1111;
172			{1'b0, `LSUOP_LBZ, 2'b00}, {1'b0, `LSUOP_LBS, 2'b00} : dcbiu_sel <= #1 4'b1000;
173			{1'b0, `LSUOP_LBZ, 2'b01}, {1'b0, `LSUOP_LBS, 2'b01} : dcbiu_sel <= #1 4'b0100;
174			{1'b0, `LSUOP_LBZ, 2'b10}, {1'b0, `LSUOP_LBS, 2'b10} : dcbiu_sel <= #1 4'b0010;
175			{1'b0, `LSUOP_LBZ, 2'b11}, {1'b0, `LSUOP_LBS, 2'b11} : dcbiu_sel <= #1 4'b0001;
176			{1'b0, `LSUOP_LHZ, 2'b00}, {1'b0, `LSUOP_LHS, 2'b00} : dcbiu_sel <= #1 4'b1100;
177			{1'b0, `LSUOP_LHZ, 2'b10}, {1'b0, `LSUOP_LHS, 2'b10} : dcbiu_sel <= #1 4'b0011;
178			{1'b0, `LSUOP_LWZ, 2'b00}, {1'b0, `LSUOP_LWS, 2'b00} : dcbiu_sel <= #1 4'b1111;
179			`7'b1xxxxxx : dcbiu_sel <= #1 4'b1111;`
180			`default : dcbiu_sel <= #1 4'b0000;`
181			`endcase`
182	161	lampret
183	166	lampret	`assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];`
184
185	168	lampret	`//`
186	166	lampret	`// Wait for DC bypass acess`
187	168	lampret	`//`
188	166	lampret	`always @(posedge rst or posedge clk)`
189			`if (rst)`
190			`bypass_wait <= #1 2'b0;`
191			`else if (dcbiu_valid)`
192			`bypass_wait <= #1 2'b0;`
193			`else if (dcbiu_read \| dcbiu_write)`
194			`bypass_wait <= #1 {bypass_wait, 1'b1};`
195			`else`
196			`bypass_wait <= #1 2'b00;`
197
198	168	lampret	`//`
199			`// Queue`
200			`//`
201	166	lampret	`assign queue = (refill && dcfsm_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;`
202
203	168	lampret	`//`
204			`// DC/LSU stall`
205			`//`
206	166	lampret	`assign dclsu_stall = refill_start \| (refill_first & ~dcbiu_valid)\| refill_rest \| queue \| cntrbusy \| (~dc_en & bypass_wait[1] & ~dcbiu_valid);`
207	161	lampret
208	168	lampret	`//`
209	161	lampret	`// Select between claddr generated by DC FSM and addr[3:2] generated by LSU`
210	168	lampret	`//`
211	161	lampret	`assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;`
212
213	168	lampret	`//`
214	161	lampret	`// Select between input data generated by LSU or by BIU`
215	168	lampret	`//`
216	161	lampret	`assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;`
217
218	168	lampret	`//`
219	161	lampret	`// Select between data generated by DCRAM or passed by BIU`
220	168	lampret	`//`
221	166	lampret	`assign to_mem2reg = (refill_first == 1'b1) \| (~dc_en) ? dcbiu_datain : from_dcram;`
222	161	lampret
223	168	lampret	`//`
224	161	lampret	`// Tag comparison`
225	168	lampret	`//`
226	161	lampret	`always @(tag or saved_addr) begin`
227			`if (tag == saved_addr[31:13])`
228			`hit <= #1 1'b1;`
229			`else`
230			`hit <= #1 1'b0;`
231			`end`
232
233	168	lampret	`//`
234	161	lampret	`// Valid_div counts RISC clock cycles by modulo 4`
235	168	lampret	`//`
236	161	lampret	`always @(posedge clk or posedge rst)`
237			`if (rst)`
238			`valid_div <= #1 2'b0;`
239			`else`
240			`valid_div <= #1 valid_div + 'd1;`
241
242	168	lampret	`//`
243	161	lampret	`// dcbiu_valid is one RISC clock cycle long dcbiu_rdy.`
244			`// dcbiu_rdy is two or four RISC clock cycles long because memory`
245			`// controller works at 1/2 or 1/4 of RISC clock freq (at 1/2 if`
246			`// clkdiv_by_2 is asserted).`
247	168	lampret	`//`
248	161	lampret	`assign dcbiu_valid = dcbiu_rdy & (valid_div[1] \| clkdiv_by_2) & valid_div[0];`
249
250	168	lampret	`//`
251	161	lampret	`// Generate refill_start that signals to frz_logic a cache linefill is about to begin`
252	168	lampret	`//`
253	161	lampret	`assign refill_start = (refill_prepare & ~hit) ? 1'b1 : 1'b0;`
254
255	168	lampret	`//`
256			`// Instantiation of DC Finite State Machine`
257			`//`
258	161	lampret	`dc_fsm dc_fsm(`
259			`.clk(clk),`
260			`.rst(rst),`
261	166	lampret	`.lsu_op(dcfsm_lsuop),`
262	161	lampret	`.miss(~hit),`
263			`.biudata_valid(dcbiu_valid),`
264			`.start_addr(dclsu_addr),`
265			`.saved_addr(saved_addr),`
266			`.refill(refill),`
267			`.refill_first(refill_first),`
268			`.refill_prepare(refill_prepare),`
269			`.dcram_we(dcram_we),`
270	166	lampret	`.biu_read(dcfsm_read),`
271			`.biu_write(dcfsm_write),`
272	161	lampret	`.refill_rest(refill_rest),`
273			`.cntrbusy(cntrbusy)`
274			`);`
275
276	168	lampret	`//`
277			`// Instantiation of Regfile-to-memory aligner`
278			`//`
279	161	lampret	`reg2mem reg2mem(`
280			`.addr(dc_addr[1:0]),`
281			`.lsu_op(dclsu_lsuop),`
282			`.regdata(dclsu_datain),`
283			`.memdata(lsu_datain_memaligned)`
284			`);`
285
286	168	lampret	`//`
287			`// Instantiation of DC main memory`
288			`//`
289	161	lampret	`dc_ram dc_ram(`
290			`.clk(clk),`
291	168	lampret	`.rst(rst),`
292	161	lampret	`.addr(dc_addr[12:2]),`
293			`.we(dcram_we),`
294			`.datain(to_dcram),`
295	168	lampret	`.dataout(from_dcram)`
296	161	lampret	`);`
297
298	168	lampret	`//`
299			`// Instantiation of DC TAG memory`
300			`//`
301	161	lampret	`dc_tag dc_tag(`
302			`.clk(clk),`
303	168	lampret	`.rst(rst),`
304	161	lampret	`.addr(dc_addr[12:4]),`
305			`.we(dctag_we),`
306			`.datain(dc_addr[31:13]),`
307	168	lampret	`.dataout(tag)`
308	161	lampret	`);`
309
310	168	lampret	`//`
311			`// Instatiation of Memory-to-regfile aligner`
312			`//`
313	161	lampret	`mem2reg mem2reg(`
314	166	lampret	`.addr(mem2reg_addr[1:0]),`
315	161	lampret	`.lsu_op(dclsu_lsuop),`
316			`.memdata(to_mem2reg),`
317			`.regdata(dclsu_dataout)`
318			`);`
319
320			`endmodule`

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