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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data Cache top level                               ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of all DC blocks.                             ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:53  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Data cache
//
 
module dc(
        // Rst, clk and clock control
        clk, rst, clkdiv_by_2,
 
        // External i/f
        dcbiu_rdy, dcbiu_datain, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dcbiu_sel,
 
        // Internal i/f
        dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall, dclsu_unstall,
 
        // SPRs
        spr_cs, spr_write, spr_addr, spr_dat_i,
 
        // Trace
        tp2w
);
 
parameter dw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
input                           clkdiv_by_2;
 
//
// External I/F
//
input                           dcbiu_rdy;
input   [dw-1:0]         dcbiu_datain;
output  [31:0]                   dcbiu_addr;
output                          dcbiu_read;
output                          dcbiu_write;
output  [3:0]                    dcbiu_sel;
 
//
// Internal I/F
//
input                           dc_en;
input   [31:0]                   dclsu_addr;
input   [`LSUOP_WIDTH-1:0]       dclsu_lsuop;
input   [dw-1:0]         dclsu_datain;
output  [dw-1:0]         dclsu_dataout;
output  [dw-1:0]         dcbiu_dataout;
output                          dclsu_stall;
output                          dclsu_unstall;
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
 
//
// Trace
//
input   [`TP2W_WIDTH-1:0]        tp2w;
 
//
// Internal wires and regs
//
wire                            tag_v;
wire    [18:0]                   tag;
wire    [dw-1:0]         to_dcram;
wire    [dw-1:0]         from_dcram;
wire    [dw-1:0]         to_mem2reg;
wire    [31:0]                   saved_addr;
wire                            refill;
wire    [3:0]                    dcram_we;
wire                            dctag_we;
wire    [dw-1:0]         lsu_datain_memaligned;
wire    [31:0]                   dc_addr;
wire                            refill_first;
wire                            refill_prepare;
wire                            refill_start;
wire                            refill_rest;
wire    [`LSUOP_WIDTH-1:0]       dcfsm_lsuop;
wire                            dcfsm_read;
wire                            dcfsm_write;
wire    [1:0]                    mem2reg_addr;
reg                             hit;
reg     [1:0]                    valid_div;
reg     [3:0]                    dcbiu_sel;
reg     [1:0]                    bypass_wait;
wire                            queue;
wire                            cntrbusy;
wire                            dcbiu_valid;
wire    [12:4]                  dctag_addr;
wire                            dctag_en;
wire                            dctag_v;
wire                            dc_inv;
 
//
// Simple assignments
//
assign dcbiu_addr = dc_addr;
assign dclsu_unstall = dcbiu_rdy;
assign dc_inv = spr_cs & spr_write;
assign dctag_we = refill | dc_inv;
assign dctag_addr = dc_inv ? spr_dat_i[12:4] : dc_addr[12:4];
assign dctag_en = dc_inv | dc_en;
assign dctag_v = ~dc_inv;
 
//
// Data to BIU is from DCRAM when DC is enabled or from LSU when
// DC is disabled
//
assign dcbiu_dataout = (dc_en) ? from_dcram : lsu_datain_memaligned;
 
//
// Bypases of the DC when DC is disabled
//
assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
assign dcbiu_read = (dc_en) ? dcfsm_read : (dclsu_lsuop && ~dclsu_lsuop[3]);
assign dcbiu_write = (dc_en) ? dcfsm_write : (dclsu_lsuop && dclsu_lsuop[3]);
always @(dc_en or dclsu_lsuop or dclsu_addr)
        casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})
                {1'b0, `LSUOP_SB, 2'b00} : dcbiu_sel <= #1 4'b1000;
                {1'b0, `LSUOP_SB, 2'b01} : dcbiu_sel <= #1 4'b0100;
                {1'b0, `LSUOP_SB, 2'b10} : dcbiu_sel <= #1 4'b0010;
                {1'b0, `LSUOP_SB, 2'b11} : dcbiu_sel <= #1 4'b0001;
                {1'b0, `LSUOP_SH, 2'b00} : dcbiu_sel <= #1 4'b1100;
                {1'b0, `LSUOP_SH, 2'b10} : dcbiu_sel <= #1 4'b0011;
                {1'b0, `LSUOP_SW, 2'b00} : dcbiu_sel <= #1 4'b1111;
                {1'b0, `LSUOP_LBZ, 2'b00}, {1'b0, `LSUOP_LBS, 2'b00} : dcbiu_sel <= #1 4'b1000;
                {1'b0, `LSUOP_LBZ, 2'b01}, {1'b0, `LSUOP_LBS, 2'b01} : dcbiu_sel <= #1 4'b0100;
                {1'b0, `LSUOP_LBZ, 2'b10}, {1'b0, `LSUOP_LBS, 2'b10} : dcbiu_sel <= #1 4'b0010;
                {1'b0, `LSUOP_LBZ, 2'b11}, {1'b0, `LSUOP_LBS, 2'b11} : dcbiu_sel <= #1 4'b0001;
                {1'b0, `LSUOP_LHZ, 2'b00}, {1'b0, `LSUOP_LHS, 2'b00} : dcbiu_sel <= #1 4'b1100;
                {1'b0, `LSUOP_LHZ, 2'b10}, {1'b0, `LSUOP_LHS, 2'b10} : dcbiu_sel <= #1 4'b0011;
                {1'b0, `LSUOP_LWZ, 2'b00}, {1'b0, `LSUOP_LWS, 2'b00} : dcbiu_sel <= #1 4'b1111;
                7'b1xxxxxx : dcbiu_sel <= #1 4'b1111;
                default : dcbiu_sel <= #1 4'b0000;
        endcase
 
assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];
 
//
// Wait for DC bypass access
//
always @(posedge rst or posedge clk)
        if (rst)
                bypass_wait <= #1 2'b0;
        else if (dcbiu_valid)
                bypass_wait <= #1 2'b0;
        else if (dcbiu_read | dcbiu_write)
                bypass_wait <= #1 {bypass_wait, 1'b1};
        else
                bypass_wait <= #1 2'b00;
 
//
// Queue
//
assign queue = (refill && dcfsm_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;
 
//
// DC/LSU stall
//
//assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & bypass_wait[1] & ~dcbiu_valid);
assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy | (~dc_en & (dcbiu_read | dcbiu_write) & ~dcbiu_rdy);
 
//
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
//
assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;
 
//
// Select between input data generated by LSU or by BIU
//
assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;
 
//
// Select between data generated by DCRAM or passed by BIU
//
assign to_mem2reg = (refill_first == 1'b1) | (~dc_en) ? dcbiu_datain : from_dcram;
 
//
// Tag comparison
//
always @(tag or saved_addr) begin
        if ((tag == saved_addr[31:13]) && tag_v)
                hit <= #1 1'b1;
        else
                hit <= #1 1'b0;
end
 
//
// Valid_div counts RISC clock cycles by modulo 4
//
always @(posedge clk or posedge rst)
        if (rst)
                valid_div <= #1 2'b0;
        else
                valid_div <= #1 valid_div + 'd1;
 
//
// dcbiu_valid is one RISC clock cycle long dcbiu_rdy.
// dcbiu_rdy is two or four RISC clock cycles long because memory
// controller works at 1/2 or 1/4 of RISC clock freq (at 1/2 if
// clkdiv_by_2 is asserted).
//
assign dcbiu_valid = dcbiu_rdy & (valid_div[1] | clkdiv_by_2) & valid_div[0];
 
//
// Generate refill_start that signals to frz_logic a cache linefill is about to begin
//
assign refill_start = (refill_prepare & ~hit) ? 1'b1 : 1'b0;
 
//
// Instantiation of DC Finite State Machine
//
dc_fsm dc_fsm(
        .clk(clk),
        .rst(rst),
        .lsu_op(dcfsm_lsuop),
        .miss(~hit),
        .biudata_valid(dcbiu_valid),
        .start_addr(dclsu_addr),
        .saved_addr(saved_addr),
        .refill(refill),
        .refill_first(refill_first),
        .refill_prepare(refill_prepare),
        .dcram_we(dcram_we),
        .biu_read(dcfsm_read),
        .biu_write(dcfsm_write),
        .refill_rest(refill_rest),
        .cntrbusy(cntrbusy)
);
 
//
// Instantiation of Regfile-to-memory aligner
//
reg2mem reg2mem(
        .addr(dc_addr[1:0]),
        .lsu_op(dclsu_lsuop),
        .regdata(dclsu_datain),
        .memdata(lsu_datain_memaligned)
);
 
//
// Instantiation of DC main memory
//
dc_ram dc_ram(
        .clk(clk),
        .rst(rst),
        .addr(dc_addr[12:2]),
        .en(dc_en),
        .we(dcram_we),
        .datain(to_dcram),
        .dataout(from_dcram)
);
 
//
// Instantiation of DC TAG memory
//
dc_tag dc_tag(
        .clk(clk),
        .rst(rst),
        .addr(dctag_addr),
        .en(dctag_en),
        .we(dctag_we),
        .datain({dc_addr[31:13], dctag_v}),
        .tag_v(tag_v),
        .tag(tag)
);
 
//
// Instatiation of Memory-to-regfile aligner
//
mem2reg mem2reg(
        .addr(mem2reg_addr[1:0]),
        .lsu_op(dclsu_lsuop),
        .memdata(to_mem2reg),
        .regdata(dclsu_dataout)
);
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Data Cache top level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of all DC blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.4 2001/08/13 03:36:20 lampret`
48			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
49			`//`
50	170	lampret	`// Revision 1.3 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53	168	lampret	`// Revision 1.2 2001/07/22 03:31:53 lampret`
54			`// Fixed RAM's oen bug. Cache bypass under development.`
55			`//`
56	166	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
57			`// Development version of RTL. Libraries are missing.`
58	161	lampret	`//`
59	166	lampret	`//`
60	161	lampret
61	203	lampret	`// synopsys translate_off`
62	168	lampret	`include "timescale.v"
63	203	lampret	`// synopsys translate_on`
64	168	lampret	`include "defines.v"
65	161	lampret
66	168	lampret	`//`
67	161	lampret	`// Data cache`
68	168	lampret	`//`
69	161	lampret
70	168	lampret	`module dc(`
71			`// Rst, clk and clock control`
72			`clk, rst, clkdiv_by_2,`
73
74			`// External i/f`
75			`dcbiu_rdy, dcbiu_datain, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dcbiu_sel,`
76
77	170	lampret	`// Internal i/f`
78	203	lampret	`dc_en, dclsu_addr, dclsu_lsuop, dclsu_datain, dclsu_dataout, dclsu_stall, dclsu_unstall,`
79	168	lampret
80	205	lampret	`// SPRs`
81			`spr_cs, spr_write, spr_addr, spr_dat_i,`
82
83	168	lampret	`// Trace`
84			`tp2w`
85	161	lampret	`);`
86
87			parameter dw = `OPERAND_WIDTH;
88
89	168	lampret	`//`
90			`// I/O`
91			`//`
92	161	lampret
93	168	lampret	`//`
94			`// Clock and reset`
95			`//`
96			`input clk;`
97			`input rst;`
98			`input clkdiv_by_2;`
99	161	lampret
100	168	lampret	`//`
101			`// External I/F`
102			`//`
103			`input dcbiu_rdy;`
104			`input [dw-1:0] dcbiu_datain;`
105			`output [31:0] dcbiu_addr;`
106			`output dcbiu_read;`
107			`output dcbiu_write;`
108			`output [3:0] dcbiu_sel;`
109	161	lampret
110	168	lampret	`//`
111			`// Internal I/F`
112			`//`
113			`input dc_en;`
114			`input [31:0] dclsu_addr;`
115			input [`LSUOP_WIDTH-1:0] dclsu_lsuop;
116			`input [dw-1:0] dclsu_datain;`
117			`output [dw-1:0] dclsu_dataout;`
118			`output [dw-1:0] dcbiu_dataout;`
119			`output dclsu_stall;`
120	203	lampret	`output dclsu_unstall;`
121	161	lampret
122	168	lampret	`//`
123	205	lampret	`// SPR access`
124			`//`
125			`input spr_cs;`
126			`input spr_write;`
127			`input [31:0] spr_addr;`
128			`input [31:0] spr_dat_i;`
129
130			`//`
131	168	lampret	`// Trace`
132			`//`
133			input [`TP2W_WIDTH-1:0] tp2w;
134	161	lampret
135	168	lampret	`//`
136			`// Internal wires and regs`
137			`//`
138	205	lampret	`wire tag_v;`
139	168	lampret	`wire [18:0] tag;`
140			`wire [dw-1:0] to_dcram;`
141			`wire [dw-1:0] from_dcram;`
142			`wire [dw-1:0] to_mem2reg;`
143			`wire [31:0] saved_addr;`
144			`wire refill;`
145			`wire [3:0] dcram_we;`
146			`wire dctag_we;`
147			`wire [dw-1:0] lsu_datain_memaligned;`
148			`wire [31:0] dc_addr;`
149			`wire refill_first;`
150			`wire refill_prepare;`
151			`wire refill_start;`
152			`wire refill_rest;`
153			wire [`LSUOP_WIDTH-1:0] dcfsm_lsuop;
154			`wire dcfsm_read;`
155			`wire dcfsm_write;`
156			`wire [1:0] mem2reg_addr;`
157			`reg hit;`
158			`reg [1:0] valid_div;`
159			`reg [3:0] dcbiu_sel;`
160			`reg [1:0] bypass_wait;`
161			`wire queue;`
162			`wire cntrbusy;`
163			`wire dcbiu_valid;`
164	205	lampret	`wire [12:4] dctag_addr;`
165			`wire dctag_en;`
166			`wire dctag_v;`
167			`wire dc_inv;`
168	168	lampret
169			`//`
170			`// Simple assignments`
171			`//`
172	161	lampret	`assign dcbiu_addr = dc_addr;`
173	203	lampret	`assign dclsu_unstall = dcbiu_rdy;`
174	205	lampret	`assign dc_inv = spr_cs & spr_write;`
175			`assign dctag_we = refill \| dc_inv;`
176			`assign dctag_addr = dc_inv ? spr_dat_i[12:4] : dc_addr[12:4];`
177			`assign dctag_en = dc_inv \| dc_en;`
178			`assign dctag_v = ~dc_inv;`
179	168	lampret
180			`//`
181			`// Data to BIU is from DCRAM when DC is enabled or from LSU when`
182			`// DC is disabled`
183			`//`
184	166	lampret	`assign dcbiu_dataout = (dc_en) ? from_dcram : lsu_datain_memaligned;`
185	161	lampret
186	168	lampret	`//`
187			`// Bypases of the DC when DC is disabled`
188			`//`
189	166	lampret	assign dcfsm_lsuop = (dc_en) ? dclsu_lsuop : `LSUOP_NOP;
190			`assign dcbiu_read = (dc_en) ? dcfsm_read : (dclsu_lsuop && ~dclsu_lsuop[3]);`
191			`assign dcbiu_write = (dc_en) ? dcfsm_write : (dclsu_lsuop && dclsu_lsuop[3]);`
192			`always @(dc_en or dclsu_lsuop or dclsu_addr)`
193			`casex({dc_en, dclsu_lsuop, dclsu_addr[1:0]})`
194			{1'b0, `LSUOP_SB, 2'b00} : dcbiu_sel <= #1 4'b1000;
195			{1'b0, `LSUOP_SB, 2'b01} : dcbiu_sel <= #1 4'b0100;
196			{1'b0, `LSUOP_SB, 2'b10} : dcbiu_sel <= #1 4'b0010;
197			{1'b0, `LSUOP_SB, 2'b11} : dcbiu_sel <= #1 4'b0001;
198			{1'b0, `LSUOP_SH, 2'b00} : dcbiu_sel <= #1 4'b1100;
199			{1'b0, `LSUOP_SH, 2'b10} : dcbiu_sel <= #1 4'b0011;
200			{1'b0, `LSUOP_SW, 2'b00} : dcbiu_sel <= #1 4'b1111;
201			{1'b0, `LSUOP_LBZ, 2'b00}, {1'b0, `LSUOP_LBS, 2'b00} : dcbiu_sel <= #1 4'b1000;
202			{1'b0, `LSUOP_LBZ, 2'b01}, {1'b0, `LSUOP_LBS, 2'b01} : dcbiu_sel <= #1 4'b0100;
203			{1'b0, `LSUOP_LBZ, 2'b10}, {1'b0, `LSUOP_LBS, 2'b10} : dcbiu_sel <= #1 4'b0010;
204			{1'b0, `LSUOP_LBZ, 2'b11}, {1'b0, `LSUOP_LBS, 2'b11} : dcbiu_sel <= #1 4'b0001;
205			{1'b0, `LSUOP_LHZ, 2'b00}, {1'b0, `LSUOP_LHS, 2'b00} : dcbiu_sel <= #1 4'b1100;
206			{1'b0, `LSUOP_LHZ, 2'b10}, {1'b0, `LSUOP_LHS, 2'b10} : dcbiu_sel <= #1 4'b0011;
207			{1'b0, `LSUOP_LWZ, 2'b00}, {1'b0, `LSUOP_LWS, 2'b00} : dcbiu_sel <= #1 4'b1111;
208			`7'b1xxxxxx : dcbiu_sel <= #1 4'b1111;`
209			`default : dcbiu_sel <= #1 4'b0000;`
210			`endcase`
211	161	lampret
212	166	lampret	`assign mem2reg_addr = (dc_en) ? saved_addr[1:0] : dclsu_addr[1:0];`
213
214	168	lampret	`//`
215	170	lampret	`// Wait for DC bypass access`
216	168	lampret	`//`
217	166	lampret	`always @(posedge rst or posedge clk)`
218			`if (rst)`
219			`bypass_wait <= #1 2'b0;`
220			`else if (dcbiu_valid)`
221			`bypass_wait <= #1 2'b0;`
222			`else if (dcbiu_read \| dcbiu_write)`
223			`bypass_wait <= #1 {bypass_wait, 1'b1};`
224			`else`
225			`bypass_wait <= #1 2'b00;`
226
227	168	lampret	`//`
228			`// Queue`
229			`//`
230	166	lampret	`assign queue = (refill && dcfsm_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0;`
231
232	168	lampret	`//`
233			`// DC/LSU stall`
234			`//`
235	203	lampret	`//assign dclsu_stall = refill_start \| (refill_first & ~dcbiu_valid)\| refill_rest \| queue \| cntrbusy \| (~dc_en & bypass_wait[1] & ~dcbiu_valid);`
236			`assign dclsu_stall = refill_start \| (refill_first & ~dcbiu_valid)\| refill_rest \| queue \| cntrbusy \| (~dc_en & (dcbiu_read \| dcbiu_write) & ~dcbiu_rdy);`
237	161	lampret
238	168	lampret	`//`
239	161	lampret	`// Select between claddr generated by DC FSM and addr[3:2] generated by LSU`
240	168	lampret	`//`
241	161	lampret	`assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr;`
242
243	168	lampret	`//`
244	161	lampret	`// Select between input data generated by LSU or by BIU`
245	168	lampret	`//`
246	161	lampret	`assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned;`
247
248	168	lampret	`//`
249	161	lampret	`// Select between data generated by DCRAM or passed by BIU`
250	168	lampret	`//`
251	166	lampret	`assign to_mem2reg = (refill_first == 1'b1) \| (~dc_en) ? dcbiu_datain : from_dcram;`
252	161	lampret
253	168	lampret	`//`
254	161	lampret	`// Tag comparison`
255	168	lampret	`//`
256	161	lampret	`always @(tag or saved_addr) begin`
257	205	lampret	`if ((tag == saved_addr[31:13]) && tag_v)`
258	161	lampret	`hit <= #1 1'b1;`
259			`else`
260			`hit <= #1 1'b0;`
261			`end`
262
263	168	lampret	`//`
264	161	lampret	`// Valid_div counts RISC clock cycles by modulo 4`
265	168	lampret	`//`
266	161	lampret	`always @(posedge clk or posedge rst)`
267			`if (rst)`
268			`valid_div <= #1 2'b0;`
269			`else`
270			`valid_div <= #1 valid_div + 'd1;`
271
272	168	lampret	`//`
273	161	lampret	`// dcbiu_valid is one RISC clock cycle long dcbiu_rdy.`
274			`// dcbiu_rdy is two or four RISC clock cycles long because memory`
275			`// controller works at 1/2 or 1/4 of RISC clock freq (at 1/2 if`
276			`// clkdiv_by_2 is asserted).`
277	168	lampret	`//`
278	161	lampret	`assign dcbiu_valid = dcbiu_rdy & (valid_div[1] \| clkdiv_by_2) & valid_div[0];`
279
280	168	lampret	`//`
281	161	lampret	`// Generate refill_start that signals to frz_logic a cache linefill is about to begin`
282	168	lampret	`//`
283	161	lampret	`assign refill_start = (refill_prepare & ~hit) ? 1'b1 : 1'b0;`
284
285	168	lampret	`//`
286			`// Instantiation of DC Finite State Machine`
287			`//`
288	161	lampret	`dc_fsm dc_fsm(`
289			`.clk(clk),`
290			`.rst(rst),`
291	166	lampret	`.lsu_op(dcfsm_lsuop),`
292	161	lampret	`.miss(~hit),`
293			`.biudata_valid(dcbiu_valid),`
294			`.start_addr(dclsu_addr),`
295			`.saved_addr(saved_addr),`
296			`.refill(refill),`
297			`.refill_first(refill_first),`
298			`.refill_prepare(refill_prepare),`
299			`.dcram_we(dcram_we),`
300	166	lampret	`.biu_read(dcfsm_read),`
301			`.biu_write(dcfsm_write),`
302	161	lampret	`.refill_rest(refill_rest),`
303			`.cntrbusy(cntrbusy)`
304			`);`
305
306	168	lampret	`//`
307			`// Instantiation of Regfile-to-memory aligner`
308			`//`
309	161	lampret	`reg2mem reg2mem(`
310			`.addr(dc_addr[1:0]),`
311			`.lsu_op(dclsu_lsuop),`
312			`.regdata(dclsu_datain),`
313			`.memdata(lsu_datain_memaligned)`
314			`);`
315
316	168	lampret	`//`
317			`// Instantiation of DC main memory`
318			`//`
319	161	lampret	`dc_ram dc_ram(`
320			`.clk(clk),`
321	168	lampret	`.rst(rst),`
322	161	lampret	`.addr(dc_addr[12:2]),`
323	203	lampret	`.en(dc_en),`
324	161	lampret	`.we(dcram_we),`
325			`.datain(to_dcram),`
326	168	lampret	`.dataout(from_dcram)`
327	161	lampret	`);`
328
329	168	lampret	`//`
330			`// Instantiation of DC TAG memory`
331			`//`
332	161	lampret	`dc_tag dc_tag(`
333			`.clk(clk),`
334	168	lampret	`.rst(rst),`
335	205	lampret	`.addr(dctag_addr),`
336			`.en(dctag_en),`
337	161	lampret	`.we(dctag_we),`
338	205	lampret	`.datain({dc_addr[31:13], dctag_v}),`
339			`.tag_v(tag_v),`
340			`.tag(tag)`
341	161	lampret	`);`
342
343	168	lampret	`//`
344			`// Instatiation of Memory-to-regfile aligner`
345			`//`
346	161	lampret	`mem2reg mem2reg(`
347	166	lampret	`.addr(mem2reg_addr[1:0]),`
348	161	lampret	`.lsu_op(dclsu_lsuop),`
349			`.memdata(to_mem2reg),`
350			`.regdata(dclsu_dataout)`
351			`);`
352
353			`endmodule`

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