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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
`define DCFSM_IDLE      'd0
`define DCFSM_DOLOAD    'd1
`define DCFSM_LREFILL3  'd2
`define DCFSM_DOSTORE   'd3
`define DCFSM_SREFILL3  'd4
`define DCFSM_SMEMWR    'd5
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        lsu_op, miss, biudata_valid, start_addr, saved_addr,
        refill, refill_first, refill_prepare, dcram_we,
        biu_read, biu_write, refill_rest, cntrbusy
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           miss;
input                           biudata_valid;
input   [31:0]                   start_addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
output  [31:0]                   saved_addr;
output                          refill;
output                          refill_first;
output                          refill_prepare;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          refill_rest;
output                          cntrbusy;
 
//
// Internal wires and regs
//
wire                            dcache_off = 1'b0;
reg     [31:0]                   saved_addr;
reg                             refill;
reg     [3:0]                    dcram_we;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             refill_first;
reg                             refill_prepare;
reg                             biu_read;
reg                             biu_write;
reg                             refill_rest;
reg                             cntrbusy;
 
//
// Generation of DCRAM write enable
//
always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin
        if (refill_first || !refill)
                casex({lsu_op, start_addr[1:0]})
                        {`LSUOP_SB, 2'b00} : dcram_we <= #1 4'b1000 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b01} : dcram_we <= #1 4'b0100 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b10} : dcram_we <= #1 4'b0010 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b11} : dcram_we <= #1 4'b0001 ^ {4{refill_first}};
                        {`LSUOP_SH, 2'b00} : dcram_we <= #1 4'b1100 ^ {4{refill_first}};
                        {`LSUOP_SH, 2'b10} : dcram_we <= #1 4'b0011 ^ {4{refill_first}};
                        {`LSUOP_SW, 2'b00} : dcram_we <= #1 4'b1111 ^ {4{refill_first}};
                        {`LSUOP_LWZ, 2'bxx}, {`LSUOP_LHZ, 2'bxx}, {`LSUOP_LHS, 2'bxx},
                        {`LSUOP_LBS, 2'bxx}, {`LSUOP_LBZ, 2'bxx} : dcram_we <= #1 4'b0000 ^ {4{refill_first}};
                        default : dcram_we <= #1 4'b0000;
                endcase
        else
                dcram_we <= #1 {4{refill & biudata_valid & ~biu_write}};
end
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                refill <= #1 1'b0;
                state <= #1 3`DCFSM_IDLE;
                biu_read <= #1 1'b0;
                biu_write <= #1 1'b0;
                saved_addr <= #1 32'b0;
                refill_prepare <= #1 1'b0;
                refill_rest <= #1 1'b0;
                cntrbusy <= #1 1'b0;
        end
        else
        case (state)    // synopsys full_case parallel_case
                `DCFSM_IDLE :
                        casex(lsu_op)
                                `LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
                                        $display("%t: DC_FSM Load op %h  start_addr %h", $time, lsu_op, start_addr);
                                        state <= #1 3`DCFSM_DOLOAD;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                `LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
                                        $display("%t: DC_FSM Store op %h  start_addr %h", $time, lsu_op, start_addr);
                                        state <= #1 3`DCFSM_DOSTORE;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                default: begin
                                        state <= #1 3`DCFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                        endcase
                `DCFSM_DOLOAD:
                        if (dcache_off) begin
//                              $display("%t: DC_FSM DCache off", $time);
                                state <= #1 3`DCFSM_DOLOAD;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                biu_read <= #1 1'b1;
                                if (biudata_valid) begin
                                        state <= #1 3`DCFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                end
                        end else
                        if (miss) begin
                                $display("%t: DC_FSM Load miss", $time);
                                state <= #1 3`DCFSM_LREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
                                $display("%t: DC_FSM Load hit", $time);
                                state <= #1 3`DCFSM_IDLE;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
                `DCFSM_LREFILL3 : begin
                        if (biudata_valid && cnt) begin
                                $display("%t: DC_FSM Load refill %d", $time, cnt);
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
                                $display("%t: DC_FSM Load refill end", $time, cnt);
                                state <= #1 3`DCFSM_IDLE;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                biu_read <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
                `DCFSM_DOSTORE:
                        if (miss) begin
                                $display("%t: DC_FSM Store miss", $time);
                                state <= #1 3`DCFSM_SREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
                                $display("%t: DC_FSM Store hit", $time);
                                state <= #1 3`DCFSM_SMEMWR;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                biu_write <= #1 1'b1;
                                biu_read <= #1 1'b0;
                        end
                `DCFSM_SREFILL3 : begin
                        if (biudata_valid && cnt) begin
                                $display("%t: DC_FSM Store refill %d", $time, cnt);
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
                                $display("%t: DC_FSM Store refill almost done", $time);
                                state <= #1 3`DCFSM_SMEMWR;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                biu_write <= #1 1'b1;
                                biu_read <= #1 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
                `DCFSM_SMEMWR :
                        if (biudata_valid) begin
                                $display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);
                                state <= #1 3`DCFSM_IDLE;
                                refill <= #1 1'b0;
                                biu_write <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	168	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
48			`// Development version of RTL. Libraries are missing.`
49	161	lampret	`//`
50	168	lampret	`//`
51	161	lampret
52	168	lampret	`include "timescale.v"
53			`include "defines.v"
54	161	lampret
55			`define DCFSM_IDLE 'd0
56			`define DCFSM_DOLOAD 'd1
57			`define DCFSM_LREFILL3 'd2
58			`define DCFSM_DOSTORE 'd3
59			`define DCFSM_SREFILL3 'd4
60			`define DCFSM_SMEMWR 'd5
61
62	168	lampret	`//`
63	161	lampret	`// Data cache FSM for cache line of 16 bytes (4x singleword)`
64	168	lampret	`//`
65	161	lampret
66	168	lampret	`module dc_fsm(`
67			`// Clock and reset`
68			`clk, rst,`
69	161	lampret
70	168	lampret	`// Internal i/f to top level DC`
71			`lsu_op, miss, biudata_valid, start_addr, saved_addr,`
72			`refill, refill_first, refill_prepare, dcram_we,`
73			`biu_read, biu_write, refill_rest, cntrbusy`
74			`);`
75	161	lampret
76	168	lampret	`//`
77			`// I/O`
78			`//`
79			`input clk;`
80			`input rst;`
81			`input miss;`
82			`input biudata_valid;`
83			`input [31:0] start_addr;`
84			input [`LSUOP_WIDTH-1:0] lsu_op;
85			`output [31:0] saved_addr;`
86			`output refill;`
87			`output refill_first;`
88			`output refill_prepare;`
89			`output [3:0] dcram_we;`
90			`output biu_read;`
91			`output biu_write;`
92			`output refill_rest;`
93			`output cntrbusy;`
94	161	lampret
95	168	lampret	`//`
96			`// Internal wires and regs`
97			`//`
98			`wire dcache_off = 1'b0;`
99			`reg [31:0] saved_addr;`
100			`reg refill;`
101			`reg [3:0] dcram_we;`
102			`reg [2:0] state;`
103			`reg [2:0] cnt;`
104			`reg refill_first;`
105			`reg refill_prepare;`
106			`reg biu_read;`
107			`reg biu_write;`
108			`reg refill_rest;`
109			`reg cntrbusy;`
110	161	lampret
111	168	lampret	`//`
112			`// Generation of DCRAM write enable`
113			`//`
114	161	lampret	`always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin`
115			`if (refill_first \|\| !refill)`
116			`casex({lsu_op, start_addr[1:0]})`
117			{`LSUOP_SB, 2'b00} : dcram_we <= #1 4'b1000 ^ {4{refill_first}};
118			{`LSUOP_SB, 2'b01} : dcram_we <= #1 4'b0100 ^ {4{refill_first}};
119			{`LSUOP_SB, 2'b10} : dcram_we <= #1 4'b0010 ^ {4{refill_first}};
120			{`LSUOP_SB, 2'b11} : dcram_we <= #1 4'b0001 ^ {4{refill_first}};
121			{`LSUOP_SH, 2'b00} : dcram_we <= #1 4'b1100 ^ {4{refill_first}};
122			{`LSUOP_SH, 2'b10} : dcram_we <= #1 4'b0011 ^ {4{refill_first}};
123			{`LSUOP_SW, 2'b00} : dcram_we <= #1 4'b1111 ^ {4{refill_first}};
124			{`LSUOP_LWZ, 2'bxx}, {`LSUOP_LHZ, 2'bxx}, {`LSUOP_LHS, 2'bxx},
125			{`LSUOP_LBS, 2'bxx}, {`LSUOP_LBZ, 2'bxx} : dcram_we <= #1 4'b0000 ^ {4{refill_first}};
126			`default : dcram_we <= #1 4'b0000;`
127			`endcase`
128			`else`
129			`dcram_we <= #1 {4{refill & biudata_valid & ~biu_write}};`
130			`end`
131
132	168	lampret	`//`
133			`// Main DC FSM`
134			`//`
135	161	lampret	`always @(posedge clk or posedge rst) begin`
136			`if (rst) begin`
137			`refill <= #1 1'b0;`
138			state <= #1 3`DCFSM_IDLE;
139			`biu_read <= #1 1'b0;`
140			`biu_write <= #1 1'b0;`
141			`saved_addr <= #1 32'b0;`
142			`refill_prepare <= #1 1'b0;`
143			`refill_rest <= #1 1'b0;`
144			`cntrbusy <= #1 1'b0;`
145			`end`
146			`else`
147			`case (state) // synopsys full_case parallel_case`
148			`DCFSM_IDLE :
149			`casex(lsu_op)`
150			`LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
151			`$display("%t: DC_FSM Load op %h start_addr %h", $time, lsu_op, start_addr);`
152			state <= #1 3`DCFSM_DOLOAD;
153			`refill <= #1 1'b0;`
154			`saved_addr <= #1 start_addr;`
155			`refill_first <= #1 1'b0;`
156			`refill_prepare <= #1 1'b1;`
157			`biu_read <= #1 1'b0;`
158			`biu_write <= #1 1'b0;`
159			`refill_rest <= #1 1'b0;`
160			`cntrbusy <= #1 1'b0;`
161			`end`
162			`LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
163			`$display("%t: DC_FSM Store op %h start_addr %h", $time, lsu_op, start_addr);`
164			state <= #1 3`DCFSM_DOSTORE;
165			`refill <= #1 1'b0;`
166			`saved_addr <= #1 start_addr;`
167			`refill_first <= #1 1'b0;`
168			`refill_prepare <= #1 1'b1;`
169			`biu_read <= #1 1'b0;`
170			`biu_write <= #1 1'b0;`
171			`refill_rest <= #1 1'b0;`
172			`cntrbusy <= #1 1'b0;`
173			`end`
174			`default: begin`
175			state <= #1 3`DCFSM_IDLE;
176			`refill <= #1 1'b0;`
177			`refill_first <= #1 1'b0;`
178			`refill_prepare <= #1 1'b0;`
179			`refill_rest <= #1 1'b0;`
180			`biu_read <= #1 1'b0;`
181			`biu_write <= #1 1'b0;`
182			`cntrbusy <= #1 1'b0;`
183			`end`
184			`endcase`
185			`DCFSM_DOLOAD:
186			`if (dcache_off) begin`
187			`// $display("%t: DC_FSM DCache off", $time);`
188			state <= #1 3`DCFSM_DOLOAD;
189			`refill <= #1 1'b1;`
190			`refill_first <= #1 1'b1;`
191			`refill_prepare <= #1 1'b0;`
192			`refill_rest <= #1 1'b0;`
193			`biu_read <= #1 1'b1;`
194			`if (biudata_valid) begin`
195			state <= #1 3`DCFSM_IDLE;
196			`refill <= #1 1'b0;`
197			`refill_first <= #1 1'b0;`
198			`biu_read <= #1 1'b0;`
199			`saved_addr <= #1 start_addr;`
200			`end`
201			`end else`
202			`if (miss) begin`
203			`$display("%t: DC_FSM Load miss", $time);`
204			state <= #1 3`DCFSM_LREFILL3;
205			`refill <= #1 1'b1;`
206			`refill_first <= #1 1'b1;`
207			`refill_prepare <= #1 1'b0;`
208			`cnt <= #1 3'd3;`
209			`biu_read <= #1 1'b1;`
210			`end`
211			`else begin`
212			`$display("%t: DC_FSM Load hit", $time);`
213			state <= #1 3`DCFSM_IDLE;
214			`refill <= #1 1'b0;`
215			`refill_first <= #1 1'b0;`
216			`refill_prepare <= #1 1'b0;`
217			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
218			`end`
219			`DCFSM_LREFILL3 : begin
220			`if (biudata_valid && cnt) begin`
221			`$display("%t: DC_FSM Load refill %d", $time, cnt);`
222			`cnt <= #1 cnt - 'd1;`
223			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
224			`refill_first <= #1 1'b0;`
225			`end`
226			`else if (biudata_valid) begin`
227			`$display("%t: DC_FSM Load refill end", $time, cnt);`
228			state <= #1 3`DCFSM_IDLE;
229			`refill <= #1 1'b0;`
230			`refill_first <= #1 1'b0;`
231			`biu_read <= #1 1'b0;`
232			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
233			`end`
234			`refill_rest <= #1 ~refill_first & refill;`
235			`end`
236			`DCFSM_DOSTORE:
237			`if (miss) begin`
238			`$display("%t: DC_FSM Store miss", $time);`
239			state <= #1 3`DCFSM_SREFILL3;
240			`refill <= #1 1'b1;`
241			`refill_first <= #1 1'b1;`
242			`refill_prepare <= #1 1'b0;`
243			`cnt <= #1 3'd3;`
244			`biu_read <= #1 1'b1;`
245			`end`
246			`else begin`
247			`$display("%t: DC_FSM Store hit", $time);`
248			state <= #1 3`DCFSM_SMEMWR;
249			`refill <= #1 1'b1;`
250			`refill_first <= #1 1'b0;`
251			`refill_prepare <= #1 1'b0;`
252			`biu_write <= #1 1'b1;`
253			`biu_read <= #1 1'b0;`
254			`end`
255			`DCFSM_SREFILL3 : begin
256			`if (biudata_valid && cnt) begin`
257			`$display("%t: DC_FSM Store refill %d", $time, cnt);`
258			`cnt <= #1 cnt - 'd1;`
259			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
260			`refill_first <= #1 1'b0;`
261			`end`
262			`else if (biudata_valid) begin`
263			`$display("%t: DC_FSM Store refill almost done", $time);`
264			state <= #1 3`DCFSM_SMEMWR;
265			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
266			`biu_write <= #1 1'b1;`
267			`biu_read <= #1 1'b0;`
268			`end`
269			`refill_rest <= #1 ~refill_first & refill;`
270			`end`
271			`DCFSM_SMEMWR :
272			`if (biudata_valid) begin`
273			`$display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);`
274			state <= #1 3`DCFSM_IDLE;
275			`refill <= #1 1'b0;`
276			`biu_write <= #1 1'b0;`
277			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
278			`end`
279			`endcase`
280			`end`
281
282			`endmodule`

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