URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [dc_fsm.v] - Blame information for rev 203

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define DCFSM_IDLE      3'd0
`define DCFSM_DOLOAD    3'd1
`define DCFSM_LREFILL3  3'd2
`define DCFSM_DOSTORE   3'd3
`define DCFSM_SREFILL3  3'd4
`define DCFSM_SMEMWR    3'd5
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        lsu_op, miss, biudata_valid, start_addr, saved_addr,
        refill, refill_first, refill_prepare, dcram_we,
        biu_read, biu_write, refill_rest, cntrbusy
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           miss;
input                           biudata_valid;
input   [31:0]                   start_addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
output  [31:0]                   saved_addr;
output                          refill;
output                          refill_first;
output                          refill_prepare;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          refill_rest;
output                          cntrbusy;
 
//
// Internal wires and regs
//
wire                            dcache_off = 1'b0;
reg     [31:0]                   saved_addr;
reg                             refill;
reg     [3:0]                    dcram_we;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             refill_first;
reg                             refill_prepare;
reg                             biu_read;
reg                             biu_write;
reg                             refill_rest;
reg                             cntrbusy;
 
//
// Generation of DCRAM write enable
//
always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin
        if (refill_first || !refill)
                casex({lsu_op, start_addr[1:0]})
                        {`LSUOP_SB, 2'b00} : dcram_we <= #1 4'b1000 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b01} : dcram_we <= #1 4'b0100 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b10} : dcram_we <= #1 4'b0010 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b11} : dcram_we <= #1 4'b0001 ^ {4{refill_first}};
                        {`LSUOP_SH, 2'b00} : dcram_we <= #1 4'b1100 ^ {4{refill_first}};
                        {`LSUOP_SH, 2'b10} : dcram_we <= #1 4'b0011 ^ {4{refill_first}};
                        {`LSUOP_SW, 2'b00} : dcram_we <= #1 4'b1111 ^ {4{refill_first}};
                        {`LSUOP_LWZ, 2'bxx}, {`LSUOP_LHZ, 2'bxx}, {`LSUOP_LHS, 2'bxx},
                        {`LSUOP_LBS, 2'bxx}, {`LSUOP_LBZ, 2'bxx} : dcram_we <= #1 4'b0000 ^ {4{refill_first}};
                        default : dcram_we <= #1 4'b0000;
                endcase
        else
                dcram_we <= #1 {4{refill & biudata_valid & ~biu_write}};
end
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                refill <= #1 1'b0;
                state <= #1 `DCFSM_IDLE;
                biu_read <= #1 1'b0;
                biu_write <= #1 1'b0;
                saved_addr <= #1 32'b0;
                refill_prepare <= #1 1'b0;
                refill_rest <= #1 1'b0;
                cntrbusy <= #1 1'b0;
        end
        else
        case (state)    // synopsys full_case parallel_case
                `DCFSM_IDLE :
                        casex(lsu_op)
                                `LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                        $display("%t: DC_FSM Load op %h  start_addr %h", $time, lsu_op, start_addr);
// synopsys translate_on
`endif
                                        state <= #1 `DCFSM_DOLOAD;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                `LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                        $display("%t: DC_FSM Store op %h  start_addr %h", $time, lsu_op, start_addr);
// synopsys translate_on
`endif
                                        state <= #1 `DCFSM_DOSTORE;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                default: begin
                                        state <= #1 `DCFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                        endcase
                `DCFSM_DOLOAD:
                        if (dcache_off) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM DCache off", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_DOLOAD;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                biu_read <= #1 1'b1;
                                if (biudata_valid) begin
                                        state <= #1 `DCFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                end
                        end else
                        if (miss) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load miss", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_LREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load hit", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
                `DCFSM_LREFILL3 : begin
                        if (biudata_valid && cnt) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load refill %d", $time, cnt);
// synopsys translate_on
`endif
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load refill end", $time, cnt);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                biu_read <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
                `DCFSM_DOSTORE:
                        if (miss) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store miss", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store hit", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SMEMWR;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                biu_write <= #1 1'b1;
                                biu_read <= #1 1'b0;
                        end
                `DCFSM_SREFILL3 : begin
                        if (biudata_valid && cnt) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill %d", $time, cnt);
// synopsys translate_on
`endif
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill almost done", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SMEMWR;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                biu_write <= #1 1'b1;
                                biu_read <= #1 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
                `DCFSM_SMEMWR :
                        if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                biu_write <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.2 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	168	lampret	`//`
54	161	lampret
55	203	lampret	`// synopsys translate_off`
56	168	lampret	`include "timescale.v"
57	203	lampret	`// synopsys translate_on`
58	168	lampret	`include "defines.v"
59	161	lampret
60	203	lampret	`define DCFSM_IDLE 3'd0
61			`define DCFSM_DOLOAD 3'd1
62			`define DCFSM_LREFILL3 3'd2
63			`define DCFSM_DOSTORE 3'd3
64			`define DCFSM_SREFILL3 3'd4
65			`define DCFSM_SMEMWR 3'd5
66	161	lampret
67	168	lampret	`//`
68	161	lampret	`// Data cache FSM for cache line of 16 bytes (4x singleword)`
69	168	lampret	`//`
70	161	lampret
71	168	lampret	`module dc_fsm(`
72			`// Clock and reset`
73			`clk, rst,`
74	161	lampret
75	168	lampret	`// Internal i/f to top level DC`
76			`lsu_op, miss, biudata_valid, start_addr, saved_addr,`
77			`refill, refill_first, refill_prepare, dcram_we,`
78			`biu_read, biu_write, refill_rest, cntrbusy`
79			`);`
80	161	lampret
81	168	lampret	`//`
82			`// I/O`
83			`//`
84			`input clk;`
85			`input rst;`
86			`input miss;`
87			`input biudata_valid;`
88			`input [31:0] start_addr;`
89			input [`LSUOP_WIDTH-1:0] lsu_op;
90			`output [31:0] saved_addr;`
91			`output refill;`
92			`output refill_first;`
93			`output refill_prepare;`
94			`output [3:0] dcram_we;`
95			`output biu_read;`
96			`output biu_write;`
97			`output refill_rest;`
98			`output cntrbusy;`
99	161	lampret
100	168	lampret	`//`
101			`// Internal wires and regs`
102			`//`
103			`wire dcache_off = 1'b0;`
104			`reg [31:0] saved_addr;`
105			`reg refill;`
106			`reg [3:0] dcram_we;`
107			`reg [2:0] state;`
108			`reg [2:0] cnt;`
109			`reg refill_first;`
110			`reg refill_prepare;`
111			`reg biu_read;`
112			`reg biu_write;`
113			`reg refill_rest;`
114			`reg cntrbusy;`
115	161	lampret
116	168	lampret	`//`
117			`// Generation of DCRAM write enable`
118			`//`
119	161	lampret	`always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin`
120			`if (refill_first \|\| !refill)`
121			`casex({lsu_op, start_addr[1:0]})`
122			{`LSUOP_SB, 2'b00} : dcram_we <= #1 4'b1000 ^ {4{refill_first}};
123			{`LSUOP_SB, 2'b01} : dcram_we <= #1 4'b0100 ^ {4{refill_first}};
124			{`LSUOP_SB, 2'b10} : dcram_we <= #1 4'b0010 ^ {4{refill_first}};
125			{`LSUOP_SB, 2'b11} : dcram_we <= #1 4'b0001 ^ {4{refill_first}};
126			{`LSUOP_SH, 2'b00} : dcram_we <= #1 4'b1100 ^ {4{refill_first}};
127			{`LSUOP_SH, 2'b10} : dcram_we <= #1 4'b0011 ^ {4{refill_first}};
128			{`LSUOP_SW, 2'b00} : dcram_we <= #1 4'b1111 ^ {4{refill_first}};
129			{`LSUOP_LWZ, 2'bxx}, {`LSUOP_LHZ, 2'bxx}, {`LSUOP_LHS, 2'bxx},
130			{`LSUOP_LBS, 2'bxx}, {`LSUOP_LBZ, 2'bxx} : dcram_we <= #1 4'b0000 ^ {4{refill_first}};
131			`default : dcram_we <= #1 4'b0000;`
132			`endcase`
133			`else`
134			`dcram_we <= #1 {4{refill & biudata_valid & ~biu_write}};`
135			`end`
136
137	168	lampret	`//`
138			`// Main DC FSM`
139			`//`
140	161	lampret	`always @(posedge clk or posedge rst) begin`
141			`if (rst) begin`
142			`refill <= #1 1'b0;`
143	203	lampret	state <= #1 `DCFSM_IDLE;
144	161	lampret	`biu_read <= #1 1'b0;`
145			`biu_write <= #1 1'b0;`
146			`saved_addr <= #1 32'b0;`
147			`refill_prepare <= #1 1'b0;`
148			`refill_rest <= #1 1'b0;`
149			`cntrbusy <= #1 1'b0;`
150			`end`
151			`else`
152			`case (state) // synopsys full_case parallel_case`
153			`DCFSM_IDLE :
154			`casex(lsu_op)`
155			`LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
156	203	lampret	`ifdef OR1200_VERBOSE
157			`// synopsys translate_off`
158	161	lampret	`$display("%t: DC_FSM Load op %h start_addr %h", $time, lsu_op, start_addr);`
159	203	lampret	`// synopsys translate_on`
160			`endif
161			state <= #1 `DCFSM_DOLOAD;
162	161	lampret	`refill <= #1 1'b0;`
163			`saved_addr <= #1 start_addr;`
164			`refill_first <= #1 1'b0;`
165			`refill_prepare <= #1 1'b1;`
166			`biu_read <= #1 1'b0;`
167			`biu_write <= #1 1'b0;`
168			`refill_rest <= #1 1'b0;`
169			`cntrbusy <= #1 1'b0;`
170			`end`
171			`LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
172	203	lampret	`ifdef OR1200_VERBOSE
173			`// synopsys translate_off`
174	161	lampret	`$display("%t: DC_FSM Store op %h start_addr %h", $time, lsu_op, start_addr);`
175	203	lampret	`// synopsys translate_on`
176			`endif
177			state <= #1 `DCFSM_DOSTORE;
178	161	lampret	`refill <= #1 1'b0;`
179			`saved_addr <= #1 start_addr;`
180			`refill_first <= #1 1'b0;`
181			`refill_prepare <= #1 1'b1;`
182			`biu_read <= #1 1'b0;`
183			`biu_write <= #1 1'b0;`
184			`refill_rest <= #1 1'b0;`
185			`cntrbusy <= #1 1'b0;`
186			`end`
187			`default: begin`
188	203	lampret	state <= #1 `DCFSM_IDLE;
189	161	lampret	`refill <= #1 1'b0;`
190			`refill_first <= #1 1'b0;`
191			`refill_prepare <= #1 1'b0;`
192			`refill_rest <= #1 1'b0;`
193			`biu_read <= #1 1'b0;`
194			`biu_write <= #1 1'b0;`
195			`cntrbusy <= #1 1'b0;`
196			`end`
197			`endcase`
198			`DCFSM_DOLOAD:
199			`if (dcache_off) begin`
200	203	lampret	`ifdef OR1200_VERBOSE
201			`// synopsys translate_off`
202			`$display("%t: DC_FSM DCache off", $time);`
203			`// synopsys translate_on`
204			`endif
205			state <= #1 `DCFSM_DOLOAD;
206	161	lampret	`refill <= #1 1'b1;`
207			`refill_first <= #1 1'b1;`
208			`refill_prepare <= #1 1'b0;`
209			`refill_rest <= #1 1'b0;`
210			`biu_read <= #1 1'b1;`
211			`if (biudata_valid) begin`
212	203	lampret	state <= #1 `DCFSM_IDLE;
213	161	lampret	`refill <= #1 1'b0;`
214			`refill_first <= #1 1'b0;`
215			`biu_read <= #1 1'b0;`
216			`saved_addr <= #1 start_addr;`
217			`end`
218			`end else`
219			`if (miss) begin`
220	203	lampret	`ifdef OR1200_VERBOSE
221			`// synopsys translate_off`
222	161	lampret	`$display("%t: DC_FSM Load miss", $time);`
223	203	lampret	`// synopsys translate_on`
224			`endif
225			state <= #1 `DCFSM_LREFILL3;
226	161	lampret	`refill <= #1 1'b1;`
227			`refill_first <= #1 1'b1;`
228			`refill_prepare <= #1 1'b0;`
229			`cnt <= #1 3'd3;`
230			`biu_read <= #1 1'b1;`
231			`end`
232			`else begin`
233	203	lampret	`ifdef OR1200_VERBOSE
234			`// synopsys translate_off`
235	161	lampret	`$display("%t: DC_FSM Load hit", $time);`
236	203	lampret	`// synopsys translate_on`
237			`endif
238			state <= #1 `DCFSM_IDLE;
239	161	lampret	`refill <= #1 1'b0;`
240			`refill_first <= #1 1'b0;`
241			`refill_prepare <= #1 1'b0;`
242			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
243			`end`
244			`DCFSM_LREFILL3 : begin
245			`if (biudata_valid && cnt) begin`
246	203	lampret	`ifdef OR1200_VERBOSE
247			`// synopsys translate_off`
248	161	lampret	`$display("%t: DC_FSM Load refill %d", $time, cnt);`
249	203	lampret	`// synopsys translate_on`
250			`endif
251	161	lampret	`cnt <= #1 cnt - 'd1;`
252			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
253			`refill_first <= #1 1'b0;`
254			`end`
255			`else if (biudata_valid) begin`
256	203	lampret	`ifdef OR1200_VERBOSE
257			`// synopsys translate_off`
258	161	lampret	`$display("%t: DC_FSM Load refill end", $time, cnt);`
259	203	lampret	`// synopsys translate_on`
260			`endif
261			state <= #1 `DCFSM_IDLE;
262	161	lampret	`refill <= #1 1'b0;`
263			`refill_first <= #1 1'b0;`
264			`biu_read <= #1 1'b0;`
265			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
266			`end`
267			`refill_rest <= #1 ~refill_first & refill;`
268			`end`
269			`DCFSM_DOSTORE:
270			`if (miss) begin`
271	203	lampret	`ifdef OR1200_VERBOSE
272			`// synopsys translate_off`
273	161	lampret	`$display("%t: DC_FSM Store miss", $time);`
274	203	lampret	`// synopsys translate_on`
275			`endif
276			state <= #1 `DCFSM_SREFILL3;
277	161	lampret	`refill <= #1 1'b1;`
278			`refill_first <= #1 1'b1;`
279			`refill_prepare <= #1 1'b0;`
280			`cnt <= #1 3'd3;`
281			`biu_read <= #1 1'b1;`
282			`end`
283			`else begin`
284	203	lampret	`ifdef OR1200_VERBOSE
285			`// synopsys translate_off`
286	161	lampret	`$display("%t: DC_FSM Store hit", $time);`
287	203	lampret	`// synopsys translate_on`
288			`endif
289			state <= #1 `DCFSM_SMEMWR;
290	161	lampret	`refill <= #1 1'b1;`
291			`refill_first <= #1 1'b0;`
292			`refill_prepare <= #1 1'b0;`
293			`biu_write <= #1 1'b1;`
294			`biu_read <= #1 1'b0;`
295			`end`
296			`DCFSM_SREFILL3 : begin
297			`if (biudata_valid && cnt) begin`
298	203	lampret	`ifdef OR1200_VERBOSE
299			`// synopsys translate_off`
300	161	lampret	`$display("%t: DC_FSM Store refill %d", $time, cnt);`
301	203	lampret	`// synopsys translate_on`
302			`endif
303	161	lampret	`cnt <= #1 cnt - 'd1;`
304			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
305			`refill_first <= #1 1'b0;`
306			`end`
307			`else if (biudata_valid) begin`
308	203	lampret	`ifdef OR1200_VERBOSE
309			`// synopsys translate_off`
310	161	lampret	`$display("%t: DC_FSM Store refill almost done", $time);`
311	203	lampret	`// synopsys translate_on`
312			`endif
313			state <= #1 `DCFSM_SMEMWR;
314	161	lampret	`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
315			`biu_write <= #1 1'b1;`
316			`biu_read <= #1 1'b0;`
317			`end`
318			`refill_rest <= #1 ~refill_first & refill;`
319			`end`
320			`DCFSM_SMEMWR :
321			`if (biudata_valid) begin`
322	203	lampret	`ifdef OR1200_VERBOSE
323			`// synopsys translate_off`
324	161	lampret	`$display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);`
325	203	lampret	`// synopsys translate_on`
326			`endif
327			state <= #1 `DCFSM_IDLE;
328	161	lampret	`refill <= #1 1'b0;`
329			`biu_write <= #1 1'b0;`
330			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
331			`end`
332			`endcase`
333			`end`
334
335			`endmodule`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [dc_fsm.v] - Blame information for rev 203