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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define DCFSM_IDLE      3'd0
`define DCFSM_DOLOAD    3'd1
`define DCFSM_LREFILL3  3'd2
`define DCFSM_DOSTORE   3'd3
`define DCFSM_SREFILL3  3'd4
`define DCFSM_SMEMWR    3'd5
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        lsu_op, miss, biudata_valid, start_addr, saved_addr,
        refill, refill_first, refill_prepare, dcram_we,
        biu_read, biu_write, refill_rest, cntrbusy
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           miss;
input                           biudata_valid;
input   [31:0]                   start_addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
output  [31:0]                   saved_addr;
output                          refill;
output                          refill_first;
output                          refill_prepare;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          refill_rest;
output                          cntrbusy;
 
//
// Internal wires and regs
//
wire                            dcache_off = 1'b0;
reg     [31:0]                   saved_addr;
reg                             refill;
reg     [3:0]                    dcram_we;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             refill_first;
reg                             refill_prepare;
reg                             biu_read;
reg                             biu_write;
reg                             refill_rest;
reg                             cntrbusy;
 
//
// Generation of DCRAM write enable
//
always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin
        if (refill_first || !refill)
                casex({lsu_op, start_addr[1:0]})
                        {`LSUOP_SB, 2'b00} : dcram_we = 4'b1000 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b01} : dcram_we = 4'b0100 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b10} : dcram_we = 4'b0010 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b11} : dcram_we = 4'b0001 ^ {4{refill_first}};
                        {`LSUOP_SH, 2'b00} : dcram_we = 4'b1100 ^ {4{refill_first}};
                        {`LSUOP_SH, 2'b10} : dcram_we = 4'b0011 ^ {4{refill_first}};
                        {`LSUOP_SW, 2'b00} : dcram_we = 4'b1111 ^ {4{refill_first}};
                        {`LSUOP_LWZ, 2'bxx}, {`LSUOP_LHZ, 2'bxx}, {`LSUOP_LHS, 2'bxx},
                        {`LSUOP_LBS, 2'bxx}, {`LSUOP_LBZ, 2'bxx} : dcram_we = 4'b0000 ^ {4{refill_first}};
                        default : dcram_we = 4'b0000;
                endcase
        else
                dcram_we = {4{refill & biudata_valid & ~biu_write}};
end
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                refill <= #1 1'b0;
                state <= #1 `DCFSM_IDLE;
                cnt <= #1 3'b000;
                refill_first <= #1 1'b0;
                biu_read <= #1 1'b0;
                biu_write <= #1 1'b0;
                saved_addr <= #1 32'b0;
                refill_prepare <= #1 1'b0;
                refill_rest <= #1 1'b0;
                cntrbusy <= #1 1'b0;
        end
        else
        case (state)    // synopsys parallel_case
                `DCFSM_IDLE :
                        casex(lsu_op)
                                `LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                        $display("%t: DC_FSM Load op %h  start_addr %h", $time, lsu_op, start_addr);
// synopsys translate_on
`endif
                                        state <= #1 `DCFSM_DOLOAD;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                `LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                        $display("%t: DC_FSM Store op %h  start_addr %h", $time, lsu_op, start_addr);
// synopsys translate_on
`endif
                                        state <= #1 `DCFSM_DOSTORE;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                default: begin
                                        state <= #1 `DCFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                        endcase
                `DCFSM_DOLOAD:
                        if (dcache_off) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM DCache off", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_DOLOAD;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                biu_read <= #1 1'b1;
                                if (biudata_valid) begin
                                        state <= #1 `DCFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                end
                        end else
                        if (miss) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load miss", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_LREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load hit", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
                `DCFSM_LREFILL3 : begin
                        if (biudata_valid && (|cnt)) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load refill %d", $time, cnt);
// synopsys translate_on
`endif
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load refill end", $time, cnt);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                biu_read <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
                `DCFSM_DOSTORE:
                        if (miss) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store miss", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store hit", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SMEMWR;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                biu_write <= #1 1'b1;
                                biu_read <= #1 1'b0;
                        end
                `DCFSM_SREFILL3 : begin
                        if (biudata_valid && (|cnt)) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill %d", $time, cnt);
// synopsys translate_on
`endif
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill almost done", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SMEMWR;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                biu_write <= #1 1'b1;
                                biu_read <= #1 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
                `DCFSM_SMEMWR :
                        if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                biu_write <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	217	lampret	`// $Log: not supported by cvs2svn $`
47	218	lampret	`// Revision 1.8 2001/10/19 23:28:46 lampret`
48			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
49			`//`
50	217	lampret	`// Revision 1.7 2001/10/14 13:12:09 lampret`
51			`// MP3 version.`
52	218	lampret	`//`
53			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
54			`// no message`
55			`//`
56			`// Revision 1.2 2001/08/09 13:39:33 lampret`
57			`// Major clean-up.`
58			`//`
59			`// Revision 1.1 2001/07/20 00:46:03 lampret`
60			`// Development version of RTL. Libraries are missing.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "defines.v"
68
69			`define DCFSM_IDLE 3'd0
70			`define DCFSM_DOLOAD 3'd1
71			`define DCFSM_LREFILL3 3'd2
72			`define DCFSM_DOSTORE 3'd3
73			`define DCFSM_SREFILL3 3'd4
74			`define DCFSM_SMEMWR 3'd5
75
76			`//`
77			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
78			`//`
79
80			`module dc_fsm(`
81			`// Clock and reset`
82			`clk, rst,`
83
84			`// Internal i/f to top level DC`
85			`lsu_op, miss, biudata_valid, start_addr, saved_addr,`
86			`refill, refill_first, refill_prepare, dcram_we,`
87			`biu_read, biu_write, refill_rest, cntrbusy`
88			`);`
89
90			`//`
91			`// I/O`
92			`//`
93			`input clk;`
94			`input rst;`
95			`input miss;`
96			`input biudata_valid;`
97			`input [31:0] start_addr;`
98			input [`LSUOP_WIDTH-1:0] lsu_op;
99			`output [31:0] saved_addr;`
100			`output refill;`
101			`output refill_first;`
102			`output refill_prepare;`
103			`output [3:0] dcram_we;`
104			`output biu_read;`
105			`output biu_write;`
106			`output refill_rest;`
107			`output cntrbusy;`
108
109			`//`
110			`// Internal wires and regs`
111			`//`
112			`wire dcache_off = 1'b0;`
113			`reg [31:0] saved_addr;`
114			`reg refill;`
115			`reg [3:0] dcram_we;`
116			`reg [2:0] state;`
117			`reg [2:0] cnt;`
118			`reg refill_first;`
119			`reg refill_prepare;`
120			`reg biu_read;`
121			`reg biu_write;`
122			`reg refill_rest;`
123			`reg cntrbusy;`
124
125			`//`
126			`// Generation of DCRAM write enable`
127			`//`
128			`always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin`
129			`if (refill_first \|\| !refill)`
130			`casex({lsu_op, start_addr[1:0]})`
131			{`LSUOP_SB, 2'b00} : dcram_we = 4'b1000 ^ {4{refill_first}};
132			{`LSUOP_SB, 2'b01} : dcram_we = 4'b0100 ^ {4{refill_first}};
133			{`LSUOP_SB, 2'b10} : dcram_we = 4'b0010 ^ {4{refill_first}};
134			{`LSUOP_SB, 2'b11} : dcram_we = 4'b0001 ^ {4{refill_first}};
135			{`LSUOP_SH, 2'b00} : dcram_we = 4'b1100 ^ {4{refill_first}};
136			{`LSUOP_SH, 2'b10} : dcram_we = 4'b0011 ^ {4{refill_first}};
137			{`LSUOP_SW, 2'b00} : dcram_we = 4'b1111 ^ {4{refill_first}};
138			{`LSUOP_LWZ, 2'bxx}, {`LSUOP_LHZ, 2'bxx}, {`LSUOP_LHS, 2'bxx},
139			{`LSUOP_LBS, 2'bxx}, {`LSUOP_LBZ, 2'bxx} : dcram_we = 4'b0000 ^ {4{refill_first}};
140			`default : dcram_we = 4'b0000;`
141			`endcase`
142			`else`
143			`dcram_we = {4{refill & biudata_valid & ~biu_write}};`
144			`end`
145
146			`//`
147			`// Main DC FSM`
148			`//`
149			`always @(posedge clk or posedge rst) begin`
150			`if (rst) begin`
151			`refill <= #1 1'b0;`
152			state <= #1 `DCFSM_IDLE;
153			`cnt <= #1 3'b000;`
154			`refill_first <= #1 1'b0;`
155			`biu_read <= #1 1'b0;`
156			`biu_write <= #1 1'b0;`
157			`saved_addr <= #1 32'b0;`
158			`refill_prepare <= #1 1'b0;`
159			`refill_rest <= #1 1'b0;`
160			`cntrbusy <= #1 1'b0;`
161			`end`
162			`else`
163			`case (state) // synopsys parallel_case`
164			`DCFSM_IDLE :
165			`casex(lsu_op)`
166			`LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
167			`ifdef OR1200_VERBOSE
168			`// synopsys translate_off`
169			`$display("%t: DC_FSM Load op %h start_addr %h", $time, lsu_op, start_addr);`
170			`// synopsys translate_on`
171			`endif
172			state <= #1 `DCFSM_DOLOAD;
173			`refill <= #1 1'b0;`
174			`saved_addr <= #1 start_addr;`
175			`refill_first <= #1 1'b0;`
176			`refill_prepare <= #1 1'b1;`
177			`biu_read <= #1 1'b0;`
178			`biu_write <= #1 1'b0;`
179			`refill_rest <= #1 1'b0;`
180			`cntrbusy <= #1 1'b0;`
181			`end`
182			`LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
183			`ifdef OR1200_VERBOSE
184			`// synopsys translate_off`
185			`$display("%t: DC_FSM Store op %h start_addr %h", $time, lsu_op, start_addr);`
186			`// synopsys translate_on`
187			`endif
188			state <= #1 `DCFSM_DOSTORE;
189			`refill <= #1 1'b0;`
190			`saved_addr <= #1 start_addr;`
191			`refill_first <= #1 1'b0;`
192			`refill_prepare <= #1 1'b1;`
193			`biu_read <= #1 1'b0;`
194			`biu_write <= #1 1'b0;`
195			`refill_rest <= #1 1'b0;`
196			`cntrbusy <= #1 1'b0;`
197			`end`
198			`default: begin`
199			state <= #1 `DCFSM_IDLE;
200			`refill <= #1 1'b0;`
201			`refill_first <= #1 1'b0;`
202			`refill_prepare <= #1 1'b0;`
203			`refill_rest <= #1 1'b0;`
204			`biu_read <= #1 1'b0;`
205			`biu_write <= #1 1'b0;`
206			`cntrbusy <= #1 1'b0;`
207			`end`
208			`endcase`
209			`DCFSM_DOLOAD:
210			`if (dcache_off) begin`
211			`ifdef OR1200_VERBOSE
212			`// synopsys translate_off`
213			`$display("%t: DC_FSM DCache off", $time);`
214			`// synopsys translate_on`
215			`endif
216			state <= #1 `DCFSM_DOLOAD;
217			`refill <= #1 1'b1;`
218			`refill_first <= #1 1'b1;`
219			`refill_prepare <= #1 1'b0;`
220			`refill_rest <= #1 1'b0;`
221			`biu_read <= #1 1'b1;`
222			`if (biudata_valid) begin`
223			state <= #1 `DCFSM_IDLE;
224			`refill <= #1 1'b0;`
225			`refill_first <= #1 1'b0;`
226			`biu_read <= #1 1'b0;`
227			`saved_addr <= #1 start_addr;`
228			`end`
229			`end else`
230			`if (miss) begin`
231			`ifdef OR1200_VERBOSE
232			`// synopsys translate_off`
233			`$display("%t: DC_FSM Load miss", $time);`
234			`// synopsys translate_on`
235			`endif
236			state <= #1 `DCFSM_LREFILL3;
237			`refill <= #1 1'b1;`
238			`refill_first <= #1 1'b1;`
239			`refill_prepare <= #1 1'b0;`
240			`cnt <= #1 3'd3;`
241			`biu_read <= #1 1'b1;`
242			`end`
243			`else begin`
244			`ifdef OR1200_VERBOSE
245			`// synopsys translate_off`
246			`$display("%t: DC_FSM Load hit", $time);`
247			`// synopsys translate_on`
248			`endif
249			state <= #1 `DCFSM_IDLE;
250			`refill <= #1 1'b0;`
251			`refill_first <= #1 1'b0;`
252			`refill_prepare <= #1 1'b0;`
253			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
254			`end`
255			`DCFSM_LREFILL3 : begin
256			`if (biudata_valid && (\|cnt)) begin`
257			`ifdef OR1200_VERBOSE
258			`// synopsys translate_off`
259			`$display("%t: DC_FSM Load refill %d", $time, cnt);`
260			`// synopsys translate_on`
261			`endif
262			`cnt <= #1 cnt - 'd1;`
263			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
264			`refill_first <= #1 1'b0;`
265			`end`
266			`else if (biudata_valid) begin`
267			`ifdef OR1200_VERBOSE
268			`// synopsys translate_off`
269			`$display("%t: DC_FSM Load refill end", $time, cnt);`
270			`// synopsys translate_on`
271			`endif
272			state <= #1 `DCFSM_IDLE;
273			`refill <= #1 1'b0;`
274			`refill_first <= #1 1'b0;`
275			`biu_read <= #1 1'b0;`
276			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
277			`end`
278			`refill_rest <= #1 ~refill_first & refill;`
279			`end`
280			`DCFSM_DOSTORE:
281			`if (miss) begin`
282			`ifdef OR1200_VERBOSE
283			`// synopsys translate_off`
284			`$display("%t: DC_FSM Store miss", $time);`
285			`// synopsys translate_on`
286			`endif
287			state <= #1 `DCFSM_SREFILL3;
288			`refill <= #1 1'b1;`
289			`refill_first <= #1 1'b1;`
290			`refill_prepare <= #1 1'b0;`
291			`cnt <= #1 3'd3;`
292			`biu_read <= #1 1'b1;`
293			`end`
294			`else begin`
295			`ifdef OR1200_VERBOSE
296			`// synopsys translate_off`
297			`$display("%t: DC_FSM Store hit", $time);`
298			`// synopsys translate_on`
299			`endif
300			state <= #1 `DCFSM_SMEMWR;
301			`refill <= #1 1'b1;`
302			`refill_first <= #1 1'b0;`
303			`refill_prepare <= #1 1'b0;`
304			`biu_write <= #1 1'b1;`
305			`biu_read <= #1 1'b0;`
306			`end`
307			`DCFSM_SREFILL3 : begin
308			`if (biudata_valid && (\|cnt)) begin`
309			`ifdef OR1200_VERBOSE
310			`// synopsys translate_off`
311			`$display("%t: DC_FSM Store refill %d", $time, cnt);`
312			`// synopsys translate_on`
313			`endif
314			`cnt <= #1 cnt - 'd1;`
315			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
316			`refill_first <= #1 1'b0;`
317			`end`
318			`else if (biudata_valid) begin`
319			`ifdef OR1200_VERBOSE
320			`// synopsys translate_off`
321			`$display("%t: DC_FSM Store refill almost done", $time);`
322			`// synopsys translate_on`
323			`endif
324			state <= #1 `DCFSM_SMEMWR;
325			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
326			`biu_write <= #1 1'b1;`
327			`biu_read <= #1 1'b0;`
328			`end`
329			`refill_rest <= #1 ~refill_first & refill;`
330			`end`
331			`DCFSM_SMEMWR :
332			`if (biudata_valid) begin`
333			`ifdef OR1200_VERBOSE
334			`// synopsys translate_off`
335			`$display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);`
336			`// synopsys translate_on`
337			`endif
338			state <= #1 `DCFSM_IDLE;
339			`refill <= #1 1'b0;`
340			`biu_write <= #1 1'b0;`
341			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
342			`end`
343			`endcase`
344			`end`
345
346			`endmodule`

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