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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module dc_ram(
        // Reset and clock
        clk, rst,
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = 11;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
 
assign dataout = {dw{1'b0}};
 
`else
 
//
// Instantiation of RAM block 0
//
generic_spram_2048x8 dc_ram0(
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[0]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[7:0]),
        .do(dataout[7:0])
);
 
//
// Instantiation of RAM block 1
//
generic_spram_2048x8 dc_ram1(
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[1]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[15:8]),
        .do(dataout[15:8])
);
 
//
// Instantiation of RAM block 2
//
generic_spram_2048x8 dc_ram2(
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[2]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[23:16]),
        .do(dataout[23:16])
);
 
//
// Instantiation of RAM block 3
//
generic_spram_2048x8 dc_ram3(
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[3]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[31:24]),
        .do(dataout[31:24])
);
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instatiation of DC RAM blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.7 2001/10/14 13:12:09 lampret`
48			`// MP3 version.`
49			`//`
50			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
51			`// no message`
52			`//`
53			`// Revision 1.2 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`// Revision 1.1 2001/07/20 00:46:03 lampret`
57			`// Development version of RTL. Libraries are missing.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "defines.v"
65
66			`module dc_ram(`
67			`// Reset and clock`
68			`clk, rst,`
69
70			`// Internal i/f`
71			`addr, en, we, datain, dataout`
72			`);`
73
74			parameter dw = `OPERAND_WIDTH;
75			`parameter aw = 11;`
76
77			`//`
78			`// I/O`
79			`//`
80			`input clk;`
81			`input rst;`
82			`input [aw-1:0] addr;`
83			`input en;`
84			`input [3:0] we;`
85			`input [dw-1:0] datain;`
86			`output [dw-1:0] dataout;`
87
88			`ifdef OR1200_NO_DC
89
90			`//`
91			`// Data cache not implemented`
92			`//`
93
94			`assign dataout = {dw{1'b0}};`
95
96			`else
97
98			`//`
99			`// Instantiation of RAM block 0`
100			`//`
101			`generic_spram_2048x8 dc_ram0(`
102			`.clk(clk),`
103			`.rst(rst),`
104			`.ce(en),`
105			`.we(we[0]),`
106			`.oe(1'b1),`
107			`.addr(addr),`
108			`.di(datain[7:0]),`
109			`.do(dataout[7:0])`
110			`);`
111
112			`//`
113			`// Instantiation of RAM block 1`
114			`//`
115			`generic_spram_2048x8 dc_ram1(`
116			`.clk(clk),`
117			`.rst(rst),`
118			`.ce(en),`
119			`.we(we[1]),`
120			`.oe(1'b1),`
121			`.addr(addr),`
122			`.di(datain[15:8]),`
123			`.do(dataout[15:8])`
124			`);`
125
126			`//`
127			`// Instantiation of RAM block 2`
128			`//`
129			`generic_spram_2048x8 dc_ram2(`
130			`.clk(clk),`
131			`.rst(rst),`
132			`.ce(en),`
133			`.we(we[2]),`
134			`.oe(1'b1),`
135			`.addr(addr),`
136			`.di(datain[23:16]),`
137			`.do(dataout[23:16])`
138			`);`
139
140			`//`
141			`// Instantiation of RAM block 3`
142			`//`
143			`generic_spram_2048x8 dc_ram3(`
144			`.clk(clk),`
145			`.rst(rst),`
146			`.ce(en),`
147			`.we(we[3]),`
148			`.oe(1'b1),`
149			`.addr(addr),`
150			`.di(datain[31:24]),`
151			`.do(dataout[31:24])`
152			`);`
153
154			`endif
155
156			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [dc_ram.v] - Blame information for rev 1778