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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's definitions                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Parameters of the OR1200 core                               ////
////                                                              ////
////  To Do:                                                      ////
////   - add parameters that are missing                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.10  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.8  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/17 08:01:19  lampret
// IC enable/disable.
//
// Revision 1.2  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`define XILINX_RAMB4
//`define XILINX_RAM32X1D
//`define ARTISAN_SSP
//`define ARTISAN_SDP
//`define ARTISAN_STP
//`define VIRTUALSILICON_SSP
//`define VIRTUALSILICON_STP
 
// Dump VCD
`define VCD_DUMP
 
// Verbose
//`define OR1200_VERBOSE
 
//
// Data cache not implemented
//
`define OR1200_NO_DC
 
//
// Insn cache not implemented
//
`define OR1200_NO_IC
 
//
// Data MMU not implemented
//
`define OR1200_NO_DMMU
 
//
// Insn MMU not implemented
//
`define OR1200_NO_IMMU
 
//
// Register OR1200 outputs
//
//`define OR1200_REGISTERED_OUTPUTS
 
//
// Implement rotate in the ALU
//
//`define IMPL_ALU_ROTATE
 
//
// Which type of compare to implement
//
//`define IMPL_ALU_COMP1
`define IMPL_ALU_COMP2
 
//
// Simulate l.div and l.divu
//
`define SIM_ALU_DIV
`define SIM_ALU_DIVU
 
`define ALUOP_NOP       4'd0
 
/* Order defined by arith insns that have two source operands both in regs
   (see binutils/include/opcode/or32.h) */
`define ALUOP_ADD       4'd0
`define ALUOP_ADDC      4'd1
`define ALUOP_SUB       4'd2
`define ALUOP_AND       4'd3
`define ALUOP_OR        4'd4
`define ALUOP_XOR       4'd5
`define ALUOP_MUL       4'd6
`define ALUOP_MAC       4'd7
`define ALUOP_SHROT     4'd8
`define ALUOP_DIV       4'd9
`define ALUOP_DIVU      4'd10
 
/* Order not specifically defined. */
`define ALUOP_IMM       4'd11
`define ALUOP_MOVHI     4'd12
`define ALUOP_COMP      4'd13
`define ALUOP_MTSR      4'd14
`define ALUOP_MFSR      4'd15
 
`define ALUOP_WIDTH     4
 
/* Shift/rotate macros. */
`define SHROTOP_NOP     2'd0
`define SHROTOP_SLL     2'd0
`define SHROTOP_SRL     2'd1
`define SHROTOP_SRA     2'd2
`define SHROTOP_ROR     2'd3
 
`define SHROTOP_WIDTH   2
 
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define IC_LINESIZE             4
 
// Insn cache specific
`define ICSIZE                  13              // 8192
`define ICINDX                  `ICSIZE-2       // 11
`define ICINDXH                 `ICSIZE-1       // 12
`define ICTAGL                  `ICINDXH+1      // 13
 
`define OPERAND_WIDTH           32
`define REGFILE_ADDR_WIDTH      5
`define off     1'b0
`define on      1'b1
 
// Use fast (and bigger) version of mem2reg aligner
`define MEM2REG_FAST
 
// SHROT_OP position in machine word
`define SHROTOP_POS             7:6
 
// ALU instructions multicycle field in machine word
`define ALUMCYC_POS             9:8
 
// Execution cycles per instruction
`define MULTICYCLE_WIDTH        2
`define ONE_CYCLE               2'd0
`define TWO_CYCLES              2'd1
 
// Operand MUX selects
`define SEL_WIDTH               2
`define SEL_RF                  2'd0
`define SEL_IMM                 2'd1
`define SEL_EX_FORW             2'd2
`define SEL_WB_FORW             2'd3
 
// Branch ops
`define BRANCHOP_WIDTH          3
`define BRANCHOP_NOP            3'd0
`define BRANCHOP_J              3'd1
`define BRANCHOP_JR             3'd2
`define BRANCHOP_BAL            3'd3
`define BRANCHOP_BF             3'd4
`define BRANCHOP_BNF            3'd5
`define BRANCHOP_RFE            3'd6
 
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define LSUOP_WIDTH             4
`define LSUOP_NOP               4'b0000
`define LSUOP_LBZ               4'b0010
`define LSUOP_LBS               4'b0011
`define LSUOP_LHZ               4'b0100
`define LSUOP_LHS               4'b0101
`define LSUOP_LWZ               4'b0110
`define LSUOP_LWS               4'b0111
`define LSUOP_LD                4'b0001
`define LSUOP_SD                4'b1000
`define LSUOP_SB                4'b1010
`define LSUOP_SH                4'b1100
`define LSUOP_SW                4'b1110
 
// Fetch ops
`define FETCHOP_WIDTH           1
`define FETCHOP_NOP             1'b0
`define FETCHOP_LW              1'b1
 
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define RFWBOP_WIDTH            3
`define RFWBOP_NOP              3'b000
`define RFWBOP_ALU              3'b001
`define RFWBOP_LSU              3'b011
`define RFWBOP_SPRS             3'b101
`define RFWBOP_LR               3'b111
 
// Compare instructions
`define COP_SFEQ       3'b000
`define COP_SFNE       3'b001
`define COP_SFGT       3'b010
`define COP_SFGE       3'b011
`define COP_SFLT       3'b100
`define COP_SFLE       3'b101
`define COP_X          3'b0111
`define SIGNED_COMPARE 'd3
`define COMPOP_WIDTH    4
 
`define PAGEINDX_WIDTH          13
`define ITLBADDR_WIDTH          7
 
// Exceptions
`define EXCEPT_WIDTH 4
 
`define EXCEPT_UNUSED           `EXCEPT_WIDTH'hf
`define EXCEPT_TRAP             `EXCEPT_WIDTH'he
`define EXCEPT_BREAK            `EXCEPT_WIDTH'hd
`define EXCEPT_SYSCALL          `EXCEPT_WIDTH'hc
`define EXCEPT_RANGE            `EXCEPT_WIDTH'hb
`define EXCEPT_ITLBMISS         `EXCEPT_WIDTH'ha
`define EXCEPT_DTLBMISS         `EXCEPT_WIDTH'h9
`define EXCEPT_HPINT            `EXCEPT_WIDTH'h8
`define EXCEPT_ILLEGAL          `EXCEPT_WIDTH'h7
`define EXCEPT_ALIGN            `EXCEPT_WIDTH'h6
`define EXCEPT_LPINT            `EXCEPT_WIDTH'h5
`define EXCEPT_IPF              `EXCEPT_WIDTH'h4
`define EXCEPT_DPF              `EXCEPT_WIDTH'h3
`define EXCEPT_BUSERR           `EXCEPT_WIDTH'h2
`define EXCEPT_RESET            `EXCEPT_WIDTH'h1
`define EXCEPT_NONE             `EXCEPT_WIDTH'h0
 
`define SR_WIDTH 9
// SR bits (no CID)
`define SR_SUPV 0
`define SR_EXR  1
`define SR_EIR  2
`define SR_DCE  3
`define SR_ICE  4
`define SR_DME  5
`define SR_IME  6
`define SR_LEE  7
`define SR_CF   8
 
// Access types
`define ACCESS_WIDTH            2
`define ACCESS_USER_READ        2'b00
`define ACCESS_USER_WRITE       2'b01
`define ACCESS_SUPV_READ        2'b10
`define ACCESS_SUPV_WRITE       2'b11
 
// SPRS
// SIMON
//`define SPR_GROUP_BITS        31:27
`define SPR_GROUP_BITS  15:11
`define SPR_GROUP_WIDTH 5
`define SPR_GROUP_SYS   5'd00
`define SPR_GROUP_IMMU  5'd01
`define SPR_GROUP_DMMU  5'd02
`define SPR_GROUP_DC    5'd03
`define SPR_GROUP_IC    5'd04
`define SPR_GROUP_DU    5'd06
`define SPR_GROUP_PM    5'd08
`define SPR_GROUP_PIC   5'd09
`define SPR_GROUP_TT    5'd10
`define SPR_GROUP_MODA  5'd29
`define SPR_GROUP_MODD  5'd30
 
`define SPR_CFGR        7'd0
`define SPR_RF          6'd32   // 1024 >> 5
`define SPR_PC          11'd16
`define SPR_SR          11'd17
`define SPR_EPCR        11'd32
`define SPR_EEAR        11'd48
`define SPR_ESR         11'd64
 
 
// Bits that define the group
`define SPRGRP_BITS 15:11
 
// Bits that define offset inside the group
`define SPROFS_BITS 10:0
 
//
// Power Management
//
 
// Define it if you want PM implemented
`define PM_IMPLEMENTED
 
// Bit positions inside PMR (don't change)
`define PM_PMR_SDF 3:0
`define PM_PMR_DME 4
`define PM_PMR_SME 5
`define PM_PMR_DCGE 6
`define PM_PMR_UNUSED 31:7
 
// PMR offset inside PM group of registers
`define PM_OFS_PMR 11'b0
 
// PM group
`define SPRGRP_PM 5'd8
 
// Define if PMR can be read/written at any address inside PM group
`define PM_PARTIAL_DECODING
 
// Define if reading PMR is allowed
`define PM_READREGS
 
// Define if unused PMR bits should be zero
`define PM_UNUSED_ZERO
 
//
// Debug Unit
//
 
// Define it if you want DU implemented
`define DU_IMPLEMENTED
 
// Address offsets of DU registers inside DU group
`define DU_OFS_DMR1 5'd16
`define DU_OFS_DMR2 5'd17
`define DU_OFS_DSR 5'd20
`define DU_OFS_DRR 5'd21
 
// Position of offset bits inside SPR address
`define DUOFS_BITS 4:0
 
// Define if you want these DU registers to be implemented
`define DU_DMR1
`define DU_DMR2
`define DU_DSR
`define DU_DRR
 
// SIMON
`define DU_DMR1_ST 22
 
// Define if reading DU regs is allowed
`define DU_READREGS
 
// Define if unused DU registers bits should be zero
`define DU_UNUSED_ZERO
 
// DU operation commands
`define DU_OP_READSPR 3'd4
`define DU_OP_WRITESPR 3'd5
 
//
// Programmable Interrupt Controller
//
 
// Define it if you want PIC implemented
`define PIC_IMPLEMENTED
 
// Define number of interrupt inputs (2-31)
`define PIC_INTS 20
 
// Address offsets of PIC registers inside PIC group
`define PIC_OFS_PICMR 2'd0
`define PIC_OFS_PICPR 2'd1
`define PIC_OFS_PICSR 2'd2
 
// Position of offset bits inside SPR address
`define PICOFS_BITS 1:0
 
// Define if you want these PIC registers to be implemented
`define PIC_PICMR
`define PIC_PICPR
`define PIC_PICSR
 
// Define if reading PIC registers is allowed
`define PIC_READREGS
 
// Define if unused PIC register bits should be zero
`define PIC_UNUSED_ZERO
 
//
// Tick Timer
//
 
// Define it if you want TT implemented
`define TT_IMPLEMENTED
 
// Address offsets of TT registers inside TT group
`define TT_OFS_TTMR 1'd0
`define TT_OFS_TTCR 1'd1
 
// Position of offset bits inside SPR group
`define TTOFS_BITS 0
 
// Define if you want these TT registers to be implemented
`define TT_TTMR
`define TT_TTCR
 
// TTMR bits
`define TT_TTMR_TP 27:0
`define TT_TTMR_IP 28
`define TT_TTMR_IE 29
`define TT_TTMR_M 31:30
 
// Define if reading TT registers is allowed
`define TT_READREGS
 
 
//
// VR, UPR and Configuration Registers
//
 
// Define if you want configuration registers implemented
`define CFGR_IMPLEMENTED
 
// Define if you want full address decode inside SYS group
`define SYS_FULL_DECODE
 
// Offsets of VR, UPR and CFGR registers
`define SPRGRP_SYS_VR           4'h0
`define SPRGRP_SYS_UPR          4'h1
`define SPRGRP_SYS_CPUCFGR      4'h2
`define SPRGRP_SYS_DMMUCFGR     4'h3
`define SPRGRP_SYS_IMMUCFGR     4'h4
`define SPRGRP_SYS_DCCFGR       4'h5
`define SPRGRP_SYS_ICCFGR       4'h6
`define SPRGRP_SYS_DCFGR        4'h7
 
// VR fields
`define VR_REV_BITS             5:0
`define VR_RES1_BITS            15:6
`define VR_CFG_BITS             23:16
`define VR_VER_BITS             31:24
 
// VR values
`define VR_REV                  6'h00
`define VR_RES1                 10'h000
`define VR_CFG                  8'h00
`define VR_VER                  8'h12
 
// UPR fields
`define UPR_UP_BITS             0
`define UPR_DCP_BITS            1
`define UPR_ICP_BITS            2
`define UPR_DMP_BITS            3
`define UPR_IMP_BITS            4
`define UPR_MP_BITS             5
`define UPR_DUP_BITS            6
`define UPR_PCUP_BITS           7
`define UPR_PMP_BITS            8
`define UPR_PICP_BITS           9
`define UPR_TTP_BITS            10
`define UPR_RES1_BITS           23:11
`define UPR_CUP_BITS            31:24
 
// UPR values
`define UPR_UP                  1'b1
`define UPR_DCP                 1'b1
`define UPR_ICP                 1'b1
`define UPR_DMP                 1'b1
`define UPR_IMP                 1'b1
`define UPR_MP                  1'b1
`define UPR_DUP                 1'b1
`define UPR_PCUP                1'b0
`define UPR_PMP                 1'b1
`define UPR_PICP                1'b1
`define UPR_TTP                 1'b1
`define UPR_RES1                13'h0000
`define UPR_CUP                 8'h00
 
// CPUCFGR fields
`define CPUCFGR_NSGF_BITS       3:0
`define CPUCFGR_HGF_BITS        4
`define CPUCFGR_OB32S_BITS      5
`define CPUCFGR_OB64S_BITS      6
`define CPUCFGR_OF32S_BITS      7
`define CPUCFGR_OF64S_BITS      8
`define CPUCFGR_OV64S_BITS      9
`define CPUCFGR_RES1_BITS       31:10
 
// CPUCFGR values
`define CPUCFGR_NSGF            4'h0
`define CPUCFGR_HGF             1'b0
`define CPUCFGR_OB32S           1'b1
`define CPUCFGR_OB64S           1'b0
`define CPUCFGR_OF32S           1'b0
`define CPUCFGR_OF64S           1'b0
`define CPUCFGR_OV64S           1'b0
`define CPUCFGR_RES1            22'h000000
 
// DMMUCFGR fields
`define DMMUCFGR_NTW_BITS       1:0
`define DMMUCFGR_NTS_BITS       4:2
`define DMMUCFGR_NAE_BITS       7:5
`define DMMUCFGR_CRI_BITS       8
`define DMMUCFGR_PRI_BITS       9
`define DMMUCFGR_TEIRI_BITS     10
`define DMMUCFGR_HTR_BITS       11
`define DMMUCFGR_RES1_BITS      31:12
 
// DMMUCFGR values
`define DMMUCFGR_NTW            2'h0
`define DMMUCFGR_NTS            3'h5
`define DMMUCFGR_NAE            3'h0
`define DMMUCFGR_CRI            1'b0
`define DMMUCFGR_PRI            1'b0
`define DMMUCFGR_TEIRI          1'b1
`define DMMUCFGR_HTR            1'b0
`define DMMUCFGR_RES1           20'h00000
 
// IMMUCFGR fields
`define IMMUCFGR_NTW_BITS       1:0
`define IMMUCFGR_NTS_BITS       4:2
`define IMMUCFGR_NAE_BITS       7:5
`define IMMUCFGR_CRI_BITS       8
`define IMMUCFGR_PRI_BITS       9
`define IMMUCFGR_TEIRI_BITS     10
`define IMMUCFGR_HTR_BITS       11
`define IMMUCFGR_RES1_BITS      31:12
 
// IMMUCFGR values
`define IMMUCFGR_NTW            2'h0
`define IMMUCFGR_NTS            3'h5
`define IMMUCFGR_NAE            3'h0
`define IMMUCFGR_CRI            1'b0
`define IMMUCFGR_PRI            1'b0
`define IMMUCFGR_TEIRI          1'b1
`define IMMUCFGR_HTR            1'b0
`define IMMUCFGR_RES1           20'h00000
 
// DCCFGR fields
`define DCCFGR_NCW_BITS         2:0
`define DCCFGR_NCS_BITS         6:3
`define DCCFGR_CBS_BITS         7
`define DCCFGR_CWS_BITS         8
`define DCCFGR_CCRI_BITS        9
`define DCCFGR_CBIRI_BITS       10
`define DCCFGR_CBPRI_BITS       11
`define DCCFGR_CBLRI_BITS       12
`define DCCFGR_CBFRI_BITS       13
`define DCCFGR_CBWBRI_BITS      14
`define DCCFGR_RES1_BITS        31:15
 
// DCCFGR values
`define DCCFGR_NCW              3'h0
`define DCCFGR_NCS              4'h5
`define DCCFGR_CBS              1'b0
`define DCCFGR_CWS              1'b0
`define DCCFGR_CCRI             1'b1
`define DCCFGR_CBIRI            1'b1
`define DCCFGR_CBPRI            1'b0
`define DCCFGR_CBLRI            1'b0
`define DCCFGR_CBFRI            1'b0
`define DCCFGR_CBWBRI           1'b1
`define DCCFGR_RES1             17'h00000
 
// ICCFGR fields
`define ICCFGR_NCW_BITS         2:0
`define ICCFGR_NCS_BITS         6:3
`define ICCFGR_CBS_BITS         7
`define ICCFGR_CWS_BITS         8
`define ICCFGR_CCRI_BITS        9
`define ICCFGR_CBIRI_BITS       10
`define ICCFGR_CBPRI_BITS       11
`define ICCFGR_CBLRI_BITS       12
`define ICCFGR_CBFRI_BITS       13
`define ICCFGR_CBWBRI_BITS      14
`define ICCFGR_RES1_BITS        31:15
 
// ICCFGR values
`define ICCFGR_NCW              3'h0
`define ICCFGR_NCS              4'h5
`define ICCFGR_CBS              1'b0
`define ICCFGR_CWS              1'b0
`define ICCFGR_CCRI             1'b1
`define ICCFGR_CBIRI            1'b1
`define ICCFGR_CBPRI            1'b0
`define ICCFGR_CBLRI            1'b0
`define ICCFGR_CBFRI            1'b0
`define ICCFGR_CBWBRI           1'b1
`define ICCFGR_RES1             17'h00000
 
// DCFGR fields
`define DCFGR_NDP_BITS          2:0
`define DCFGR_WPCI_BITS         3
`define DCFGR_RES1_BITS         31:4
 
// DCFGR values
`define DCFGR_NDP               3'h0
`define DCFGR_WPCI              1'b0
`define DCFGR_RES1              28'h0000000
 
 
// Instruction opcode groups (basic)
`define OR32_J                 6'b000000
`define OR32_JAL               6'b000001
`define OR32_BNF               6'b000011
`define OR32_BF                6'b000100
`define OR32_NOP               6'b000101
`define OR32_MOVHI             6'b000110
`define OR32_MFSPR             6'b000111
`define OR32_XSYNC             6'b001000
`define OR32_RFE               6'b001001
 
`define OR32_MTSPR             6'b010000
`define OR32_JR                6'b010001
`define OR32_JALR              6'b010010
 
`define OR32_LWZ               6'b100001
`define OR32_LBZ               6'b100011
`define OR32_LBS               6'b100100
`define OR32_LHZ               6'b100101
`define OR32_LHS               6'b100110
`define OR32_ADDI              6'b100111
`define OR32_ADDIC             6'b101000
`define OR32_ANDI              6'b101001
`define OR32_ORI               6'b101010
`define OR32_XORI              6'b101011
`define OR32_MULI              6'b101100
`define OR32_MACI              6'b101101
`define OR32_SH_ROTI           6'b101110
`define OR32_SFXXI             6'b101111
 
`define OR32_SW                6'b110101
`define OR32_SB                6'b110110
`define OR32_SH                6'b110111
`define OR32_ALU               6'b111000
`define OR32_SFXX              6'b111001
 

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Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's definitions ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Parameters of the OR1200 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - add parameters that are missing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	217	lampret	`// $Log: not supported by cvs2svn $`
47	316	lampret	`// Revision 1.11 2001/11/02 18:57:14 lampret`
48			`// Modified virtual silicon instantiations.`
49			`//`
50	265	lampret	`// Revision 1.10 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53	218	lampret	`// Revision 1.9 2001/10/19 23:28:46 lampret`
54			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
55			`//`
56	217	lampret	`// Revision 1.8 2001/10/14 13:12:09 lampret`
57			`// MP3 version.`
58	218	lampret	`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.3 2001/08/17 08:01:19 lampret`
63			`// IC enable/disable.`
64			`//`
65			`// Revision 1.2 2001/08/13 03:36:20 lampret`
66			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
67			`//`
68			`// Revision 1.1 2001/08/09 13:39:33 lampret`
69			`// Major clean-up.`
70			`//`
71			`// Revision 1.2 2001/07/22 03:31:54 lampret`
72			`// Fixed RAM's oen bug. Cache bypass under development.`
73			`//`
74			`// Revision 1.1 2001/07/20 00:46:03 lampret`
75			`// Development version of RTL. Libraries are missing.`
76			`//`
77			`//`
78
79	316	lampret	`define XILINX_RAMB4
80	218	lampret	//`define XILINX_RAM32X1D
81	265	lampret	//`define ARTISAN_SSP
82			//`define ARTISAN_SDP
83	218	lampret	//`define ARTISAN_STP
84	316	lampret	//`define VIRTUALSILICON_SSP
85			//`define VIRTUALSILICON_STP
86	218	lampret
87			`// Dump VCD`
88			`define VCD_DUMP
89
90			`// Verbose`
91			//`define OR1200_VERBOSE
92
93			`//`
94			`// Data cache not implemented`
95			`//`
96	316	lampret	`define OR1200_NO_DC
97	218	lampret
98			`//`
99			`// Insn cache not implemented`
100			`//`
101	316	lampret	`define OR1200_NO_IC
102	218	lampret
103			`//`
104			`// Data MMU not implemented`
105			`//`
106	316	lampret	`define OR1200_NO_DMMU
107	218	lampret
108			`//`
109			`// Insn MMU not implemented`
110			`//`
111	316	lampret	`define OR1200_NO_IMMU
112	218	lampret
113			`//`
114			`// Register OR1200 outputs`
115			`//`
116			//`define OR1200_REGISTERED_OUTPUTS
117
118			`//`
119			`// Implement rotate in the ALU`
120			`//`
121			//`define IMPL_ALU_ROTATE
122
123			`//`
124			`// Which type of compare to implement`
125			`//`
126			//`define IMPL_ALU_COMP1
127			`define IMPL_ALU_COMP2
128
129			`//`
130			`// Simulate l.div and l.divu`
131			`//`
132			`define SIM_ALU_DIV
133			`define SIM_ALU_DIVU
134
135			`define ALUOP_NOP 4'd0
136
137			`/* Order defined by arith insns that have two source operands both in regs`
138			`(see binutils/include/opcode/or32.h) */`
139			`define ALUOP_ADD 4'd0
140			`define ALUOP_ADDC 4'd1
141			`define ALUOP_SUB 4'd2
142			`define ALUOP_AND 4'd3
143			`define ALUOP_OR 4'd4
144			`define ALUOP_XOR 4'd5
145			`define ALUOP_MUL 4'd6
146			`define ALUOP_MAC 4'd7
147			`define ALUOP_SHROT 4'd8
148			`define ALUOP_DIV 4'd9
149			`define ALUOP_DIVU 4'd10
150
151			`/* Order not specifically defined. */`
152			`define ALUOP_IMM 4'd11
153			`define ALUOP_MOVHI 4'd12
154			`define ALUOP_COMP 4'd13
155			`define ALUOP_MTSR 4'd14
156			`define ALUOP_MFSR 4'd15
157
158			`define ALUOP_WIDTH 4
159
160			`/* Shift/rotate macros. */`
161			`define SHROTOP_NOP 2'd0
162			`define SHROTOP_SLL 2'd0
163			`define SHROTOP_SRL 2'd1
164			`define SHROTOP_SRA 2'd2
165			`define SHROTOP_ROR 2'd3
166
167			`define SHROTOP_WIDTH 2
168
169
170			`// 3 for 8 bytes, 4 for 16 bytes etc`
171			`define IC_LINESIZE 4
172
173			`// Insn cache specific`
174			`define ICSIZE 13 // 8192
175			`define ICINDX `ICSIZE-2 // 11
176			`define ICINDXH `ICSIZE-1 // 12
177			`define ICTAGL `ICINDXH+1 // 13
178
179			`define OPERAND_WIDTH 32
180			`define REGFILE_ADDR_WIDTH 5
181			`define off 1'b0
182			`define on 1'b1
183
184			`// Use fast (and bigger) version of mem2reg aligner`
185			`define MEM2REG_FAST
186
187			`// SHROT_OP position in machine word`
188			`define SHROTOP_POS 7:6
189
190			`// ALU instructions multicycle field in machine word`
191			`define ALUMCYC_POS 9:8
192
193			`// Execution cycles per instruction`
194			`define MULTICYCLE_WIDTH 2
195			`define ONE_CYCLE 2'd0
196			`define TWO_CYCLES 2'd1
197
198			`// Operand MUX selects`
199			`define SEL_WIDTH 2
200			`define SEL_RF 2'd0
201			`define SEL_IMM 2'd1
202			`define SEL_EX_FORW 2'd2
203			`define SEL_WB_FORW 2'd3
204
205			`// Branch ops`
206			`define BRANCHOP_WIDTH 3
207			`define BRANCHOP_NOP 3'd0
208			`define BRANCHOP_J 3'd1
209			`define BRANCHOP_JR 3'd2
210			`define BRANCHOP_BAL 3'd3
211			`define BRANCHOP_BF 3'd4
212			`define BRANCHOP_BNF 3'd5
213			`define BRANCHOP_RFE 3'd6
214
215			`// Bit 0: sign extend`
216			`// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword`
217			`// Bit 3: 0 load, 1 store`
218			`define LSUOP_WIDTH 4
219			`define LSUOP_NOP 4'b0000
220			`define LSUOP_LBZ 4'b0010
221			`define LSUOP_LBS 4'b0011
222			`define LSUOP_LHZ 4'b0100
223			`define LSUOP_LHS 4'b0101
224			`define LSUOP_LWZ 4'b0110
225			`define LSUOP_LWS 4'b0111
226			`define LSUOP_LD 4'b0001
227			`define LSUOP_SD 4'b1000
228			`define LSUOP_SB 4'b1010
229			`define LSUOP_SH 4'b1100
230			`define LSUOP_SW 4'b1110
231
232			`// Fetch ops`
233			`define FETCHOP_WIDTH 1
234			`define FETCHOP_NOP 1'b0
235			`define FETCHOP_LW 1'b1
236
237			`// Bit 0: register file write enable`
238			`// Bits 2-1: write-back mux selects`
239			`define RFWBOP_WIDTH 3
240			`define RFWBOP_NOP 3'b000
241			`define RFWBOP_ALU 3'b001
242			`define RFWBOP_LSU 3'b011
243			`define RFWBOP_SPRS 3'b101
244			`define RFWBOP_LR 3'b111
245
246			`// Compare instructions`
247			`define COP_SFEQ 3'b000
248			`define COP_SFNE 3'b001
249			`define COP_SFGT 3'b010
250			`define COP_SFGE 3'b011
251			`define COP_SFLT 3'b100
252			`define COP_SFLE 3'b101
253			`define COP_X 3'b0111
254			`define SIGNED_COMPARE 'd3
255			`define COMPOP_WIDTH 4
256
257			`define PAGEINDX_WIDTH 13
258			`define ITLBADDR_WIDTH 7
259
260			`// Exceptions`
261			`define EXCEPT_WIDTH 4
262
263			`define EXCEPT_UNUSED `EXCEPT_WIDTH'hf
264			`define EXCEPT_TRAP `EXCEPT_WIDTH'he
265			`define EXCEPT_BREAK `EXCEPT_WIDTH'hd
266			`define EXCEPT_SYSCALL `EXCEPT_WIDTH'hc
267			`define EXCEPT_RANGE `EXCEPT_WIDTH'hb
268			`define EXCEPT_ITLBMISS `EXCEPT_WIDTH'ha
269			`define EXCEPT_DTLBMISS `EXCEPT_WIDTH'h9
270			`define EXCEPT_HPINT `EXCEPT_WIDTH'h8
271			`define EXCEPT_ILLEGAL `EXCEPT_WIDTH'h7
272			`define EXCEPT_ALIGN `EXCEPT_WIDTH'h6
273			`define EXCEPT_LPINT `EXCEPT_WIDTH'h5
274			`define EXCEPT_IPF `EXCEPT_WIDTH'h4
275			`define EXCEPT_DPF `EXCEPT_WIDTH'h3
276			`define EXCEPT_BUSERR `EXCEPT_WIDTH'h2
277			`define EXCEPT_RESET `EXCEPT_WIDTH'h1
278			`define EXCEPT_NONE `EXCEPT_WIDTH'h0
279
280			`define SR_WIDTH 9
281			`// SR bits (no CID)`
282			`define SR_SUPV 0
283			`define SR_EXR 1
284			`define SR_EIR 2
285			`define SR_DCE 3
286			`define SR_ICE 4
287			`define SR_DME 5
288			`define SR_IME 6
289			`define SR_LEE 7
290			`define SR_CF 8
291
292			`// Access types`
293			`define ACCESS_WIDTH 2
294			`define ACCESS_USER_READ 2'b00
295			`define ACCESS_USER_WRITE 2'b01
296			`define ACCESS_SUPV_READ 2'b10
297			`define ACCESS_SUPV_WRITE 2'b11
298
299			`// SPRS`
300	215	lampret	`// SIMON`
301	218	lampret	//`define SPR_GROUP_BITS 31:27
302			`define SPR_GROUP_BITS 15:11
303			`define SPR_GROUP_WIDTH 5
304			`define SPR_GROUP_SYS 5'd00
305			`define SPR_GROUP_IMMU 5'd01
306			`define SPR_GROUP_DMMU 5'd02
307			`define SPR_GROUP_DC 5'd03
308			`define SPR_GROUP_IC 5'd04
309			`define SPR_GROUP_DU 5'd06
310			`define SPR_GROUP_PM 5'd08
311			`define SPR_GROUP_PIC 5'd09
312			`define SPR_GROUP_TT 5'd10
313			`define SPR_GROUP_MODA 5'd29
314			`define SPR_GROUP_MODD 5'd30
315
316			`define SPR_CFGR 7'd0
317	209	lampret	`define SPR_RF 6'd32 // 1024 >> 5
318	218	lampret	`define SPR_PC 11'd16
319			`define SPR_SR 11'd17
320			`define SPR_EPCR 11'd32
321			`define SPR_EEAR 11'd48
322			`define SPR_ESR 11'd64
323
324
325			`// Bits that define the group`
326			`define SPRGRP_BITS 15:11
327
328			`// Bits that define offset inside the group`
329			`define SPROFS_BITS 10:0
330
331			`//`
332			`// Power Management`
333			`//`
334
335			`// Define it if you want PM implemented`
336			`define PM_IMPLEMENTED
337
338			`// Bit positions inside PMR (don't change)`
339			`define PM_PMR_SDF 3:0
340			`define PM_PMR_DME 4
341			`define PM_PMR_SME 5
342			`define PM_PMR_DCGE 6
343			`define PM_PMR_UNUSED 31:7
344
345			`// PMR offset inside PM group of registers`
346			`define PM_OFS_PMR 11'b0
347
348			`// PM group`
349			`define SPRGRP_PM 5'd8
350
351			`// Define if PMR can be read/written at any address inside PM group`
352			`define PM_PARTIAL_DECODING
353
354			`// Define if reading PMR is allowed`
355			`define PM_READREGS
356
357			`// Define if unused PMR bits should be zero`
358			`define PM_UNUSED_ZERO
359
360			`//`
361			`// Debug Unit`
362			`//`
363
364			`// Define it if you want DU implemented`
365			`define DU_IMPLEMENTED
366
367			`// Address offsets of DU registers inside DU group`
368			`define DU_OFS_DMR1 5'd16
369			`define DU_OFS_DMR2 5'd17
370			`define DU_OFS_DSR 5'd20
371			`define DU_OFS_DRR 5'd21
372
373			`// Position of offset bits inside SPR address`
374			`define DUOFS_BITS 4:0
375
376			`// Define if you want these DU registers to be implemented`
377			`define DU_DMR1
378			`define DU_DMR2
379			`define DU_DSR
380			`define DU_DRR
381
382	215	lampret	`// SIMON`
383			`define DU_DMR1_ST 22
384	168	lampret
385	218	lampret	`// Define if reading DU regs is allowed`
386			`define DU_READREGS
387
388			`// Define if unused DU registers bits should be zero`
389			`define DU_UNUSED_ZERO
390
391			`// DU operation commands`
392			`define DU_OP_READSPR 3'd4
393			`define DU_OP_WRITESPR 3'd5
394
395			`//`
396			`// Programmable Interrupt Controller`
397			`//`
398
399			`// Define it if you want PIC implemented`
400			`define PIC_IMPLEMENTED
401
402			`// Define number of interrupt inputs (2-31)`
403			`define PIC_INTS 20
404
405			`// Address offsets of PIC registers inside PIC group`
406			`define PIC_OFS_PICMR 2'd0
407			`define PIC_OFS_PICPR 2'd1
408			`define PIC_OFS_PICSR 2'd2
409
410			`// Position of offset bits inside SPR address`
411			`define PICOFS_BITS 1:0
412
413			`// Define if you want these PIC registers to be implemented`
414			`define PIC_PICMR
415			`define PIC_PICPR
416			`define PIC_PICSR
417
418			`// Define if reading PIC registers is allowed`
419			`define PIC_READREGS
420
421			`// Define if unused PIC register bits should be zero`
422			`define PIC_UNUSED_ZERO
423
424			`//`
425			`// Tick Timer`
426			`//`
427
428			`// Define it if you want TT implemented`
429			`define TT_IMPLEMENTED
430
431			`// Address offsets of TT registers inside TT group`
432			`define TT_OFS_TTMR 1'd0
433			`define TT_OFS_TTCR 1'd1
434
435			`// Position of offset bits inside SPR group`
436			`define TTOFS_BITS 0
437
438			`// Define if you want these TT registers to be implemented`
439			`define TT_TTMR
440			`define TT_TTCR
441
442			`// TTMR bits`
443			`define TT_TTMR_TP 27:0
444			`define TT_TTMR_IP 28
445			`define TT_TTMR_IE 29
446			`define TT_TTMR_M 31:30
447
448			`// Define if reading TT registers is allowed`
449			`define TT_READREGS
450
451
452			`//`
453			`// VR, UPR and Configuration Registers`
454			`//`
455
456			`// Define if you want configuration registers implemented`
457			`define CFGR_IMPLEMENTED
458
459			`// Define if you want full address decode inside SYS group`
460			`define SYS_FULL_DECODE
461
462			`// Offsets of VR, UPR and CFGR registers`
463			`define SPRGRP_SYS_VR 4'h0
464			`define SPRGRP_SYS_UPR 4'h1
465			`define SPRGRP_SYS_CPUCFGR 4'h2
466			`define SPRGRP_SYS_DMMUCFGR 4'h3
467			`define SPRGRP_SYS_IMMUCFGR 4'h4
468			`define SPRGRP_SYS_DCCFGR 4'h5
469			`define SPRGRP_SYS_ICCFGR 4'h6
470			`define SPRGRP_SYS_DCFGR 4'h7
471
472			`// VR fields`
473			`define VR_REV_BITS 5:0
474			`define VR_RES1_BITS 15:6
475			`define VR_CFG_BITS 23:16
476			`define VR_VER_BITS 31:24
477
478			`// VR values`
479			`define VR_REV 6'h00
480			`define VR_RES1 10'h000
481			`define VR_CFG 8'h00
482			`define VR_VER 8'h12
483
484			`// UPR fields`
485			`define UPR_UP_BITS 0
486			`define UPR_DCP_BITS 1
487			`define UPR_ICP_BITS 2
488			`define UPR_DMP_BITS 3
489			`define UPR_IMP_BITS 4
490			`define UPR_MP_BITS 5
491			`define UPR_DUP_BITS 6
492			`define UPR_PCUP_BITS 7
493			`define UPR_PMP_BITS 8
494			`define UPR_PICP_BITS 9
495			`define UPR_TTP_BITS 10
496			`define UPR_RES1_BITS 23:11
497			`define UPR_CUP_BITS 31:24
498
499			`// UPR values`
500			`define UPR_UP 1'b1
501			`define UPR_DCP 1'b1
502			`define UPR_ICP 1'b1
503			`define UPR_DMP 1'b1
504			`define UPR_IMP 1'b1
505			`define UPR_MP 1'b1
506			`define UPR_DUP 1'b1
507			`define UPR_PCUP 1'b0
508			`define UPR_PMP 1'b1
509			`define UPR_PICP 1'b1
510			`define UPR_TTP 1'b1
511			`define UPR_RES1 13'h0000
512			`define UPR_CUP 8'h00
513
514			`// CPUCFGR fields`
515			`define CPUCFGR_NSGF_BITS 3:0
516			`define CPUCFGR_HGF_BITS 4
517			`define CPUCFGR_OB32S_BITS 5
518			`define CPUCFGR_OB64S_BITS 6
519			`define CPUCFGR_OF32S_BITS 7
520			`define CPUCFGR_OF64S_BITS 8
521			`define CPUCFGR_OV64S_BITS 9
522			`define CPUCFGR_RES1_BITS 31:10
523
524			`// CPUCFGR values`
525			`define CPUCFGR_NSGF 4'h0
526			`define CPUCFGR_HGF 1'b0
527			`define CPUCFGR_OB32S 1'b1
528			`define CPUCFGR_OB64S 1'b0
529			`define CPUCFGR_OF32S 1'b0
530			`define CPUCFGR_OF64S 1'b0
531			`define CPUCFGR_OV64S 1'b0
532			`define CPUCFGR_RES1 22'h000000
533
534			`// DMMUCFGR fields`
535			`define DMMUCFGR_NTW_BITS 1:0
536			`define DMMUCFGR_NTS_BITS 4:2
537			`define DMMUCFGR_NAE_BITS 7:5
538			`define DMMUCFGR_CRI_BITS 8
539			`define DMMUCFGR_PRI_BITS 9
540			`define DMMUCFGR_TEIRI_BITS 10
541			`define DMMUCFGR_HTR_BITS 11
542			`define DMMUCFGR_RES1_BITS 31:12
543
544			`// DMMUCFGR values`
545			`define DMMUCFGR_NTW 2'h0
546			`define DMMUCFGR_NTS 3'h5
547			`define DMMUCFGR_NAE 3'h0
548			`define DMMUCFGR_CRI 1'b0
549			`define DMMUCFGR_PRI 1'b0
550			`define DMMUCFGR_TEIRI 1'b1
551			`define DMMUCFGR_HTR 1'b0
552			`define DMMUCFGR_RES1 20'h00000
553
554			`// IMMUCFGR fields`
555			`define IMMUCFGR_NTW_BITS 1:0
556			`define IMMUCFGR_NTS_BITS 4:2
557			`define IMMUCFGR_NAE_BITS 7:5
558			`define IMMUCFGR_CRI_BITS 8
559			`define IMMUCFGR_PRI_BITS 9
560			`define IMMUCFGR_TEIRI_BITS 10
561			`define IMMUCFGR_HTR_BITS 11
562			`define IMMUCFGR_RES1_BITS 31:12
563
564			`// IMMUCFGR values`
565			`define IMMUCFGR_NTW 2'h0
566			`define IMMUCFGR_NTS 3'h5
567			`define IMMUCFGR_NAE 3'h0
568			`define IMMUCFGR_CRI 1'b0
569			`define IMMUCFGR_PRI 1'b0
570			`define IMMUCFGR_TEIRI 1'b1
571			`define IMMUCFGR_HTR 1'b0
572			`define IMMUCFGR_RES1 20'h00000
573
574			`// DCCFGR fields`
575			`define DCCFGR_NCW_BITS 2:0
576			`define DCCFGR_NCS_BITS 6:3
577			`define DCCFGR_CBS_BITS 7
578			`define DCCFGR_CWS_BITS 8
579			`define DCCFGR_CCRI_BITS 9
580			`define DCCFGR_CBIRI_BITS 10
581			`define DCCFGR_CBPRI_BITS 11
582			`define DCCFGR_CBLRI_BITS 12
583			`define DCCFGR_CBFRI_BITS 13
584			`define DCCFGR_CBWBRI_BITS 14
585			`define DCCFGR_RES1_BITS 31:15
586
587			`// DCCFGR values`
588			`define DCCFGR_NCW 3'h0
589			`define DCCFGR_NCS 4'h5
590			`define DCCFGR_CBS 1'b0
591			`define DCCFGR_CWS 1'b0
592			`define DCCFGR_CCRI 1'b1
593			`define DCCFGR_CBIRI 1'b1
594			`define DCCFGR_CBPRI 1'b0
595			`define DCCFGR_CBLRI 1'b0
596			`define DCCFGR_CBFRI 1'b0
597			`define DCCFGR_CBWBRI 1'b1
598			`define DCCFGR_RES1 17'h00000
599
600			`// ICCFGR fields`
601			`define ICCFGR_NCW_BITS 2:0
602			`define ICCFGR_NCS_BITS 6:3
603			`define ICCFGR_CBS_BITS 7
604			`define ICCFGR_CWS_BITS 8
605			`define ICCFGR_CCRI_BITS 9
606			`define ICCFGR_CBIRI_BITS 10
607			`define ICCFGR_CBPRI_BITS 11
608			`define ICCFGR_CBLRI_BITS 12
609			`define ICCFGR_CBFRI_BITS 13
610			`define ICCFGR_CBWBRI_BITS 14
611			`define ICCFGR_RES1_BITS 31:15
612
613			`// ICCFGR values`
614			`define ICCFGR_NCW 3'h0
615			`define ICCFGR_NCS 4'h5
616			`define ICCFGR_CBS 1'b0
617			`define ICCFGR_CWS 1'b0
618			`define ICCFGR_CCRI 1'b1
619			`define ICCFGR_CBIRI 1'b1
620			`define ICCFGR_CBPRI 1'b0
621			`define ICCFGR_CBLRI 1'b0
622			`define ICCFGR_CBFRI 1'b0
623			`define ICCFGR_CBWBRI 1'b1
624			`define ICCFGR_RES1 17'h00000
625
626			`// DCFGR fields`
627			`define DCFGR_NDP_BITS 2:0
628			`define DCFGR_WPCI_BITS 3
629			`define DCFGR_RES1_BITS 31:4
630
631			`// DCFGR values`
632			`define DCFGR_NDP 3'h0
633			`define DCFGR_WPCI 1'b0
634			`define DCFGR_RES1 28'h0000000
635
636
637			`// Instruction opcode groups (basic)`
638			`define OR32_J 6'b000000
639			`define OR32_JAL 6'b000001
640			`define OR32_BNF 6'b000011
641			`define OR32_BF 6'b000100
642			`define OR32_NOP 6'b000101
643			`define OR32_MOVHI 6'b000110
644			`define OR32_MFSPR 6'b000111
645			`define OR32_XSYNC 6'b001000
646			`define OR32_RFE 6'b001001
647
648			`define OR32_MTSPR 6'b010000
649			`define OR32_JR 6'b010001
650			`define OR32_JALR 6'b010010
651
652			`define OR32_LWZ 6'b100001
653			`define OR32_LBZ 6'b100011
654			`define OR32_LBS 6'b100100
655			`define OR32_LHZ 6'b100101
656			`define OR32_LHS 6'b100110
657			`define OR32_ADDI 6'b100111
658			`define OR32_ADDIC 6'b101000
659			`define OR32_ANDI 6'b101001
660			`define OR32_ORI 6'b101010
661			`define OR32_XORI 6'b101011
662			`define OR32_MULI 6'b101100
663			`define OR32_MACI 6'b101101
664			`define OR32_SH_ROTI 6'b101110
665			`define OR32_SFXXI 6'b101111
666
667			`define OR32_SW 6'b110101
668			`define OR32_SB 6'b110110
669			`define OR32_SH 6'b110111
670			`define OR32_ALU 6'b111000
671			`define OR32_SFXX 6'b111001
672