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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's definitions                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Parameters of the OR1200 core                               ////
////                                                              ////
////  To Do:                                                      ////
////   - add parameters that are missing                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`define ARTISAN_SSP
//`define ARTISAN_STP
 
// Dump VCD
`define VCD_DUMP
 
//
// Implement rotate in the ALU
//
`define IMPL_ALU_ROTATE
 
//
// Which type of compare to implement
//
//`define IMPL_ALU_COMP1
`define IMPL_ALU_COMP2
 
//
// Simulate l.div and l.divu
//
`define SIM_ALU_DIV
`define SIM_ALU_DIVU
 
`define ALUOP_NOP       4'd0
 
/* Order defined by arith insns that have two source operands both in regs
   (see binutils/include/opcode/or32.h) */
`define ALUOP_ADD       4'd0
`define ALUOP_ADDC      4'd1
`define ALUOP_SUB       4'd2
`define ALUOP_AND       4'd3
`define ALUOP_OR        4'd4
`define ALUOP_XOR       4'd5
`define ALUOP_MUL       4'd6
`define ALUOP_MAC       4'd7
`define ALUOP_SHROT     4'd8
`define ALUOP_DIV       4'd9
`define ALUOP_DIVU      4'd10
 
/* Order not specifically defined. */
`define ALUOP_IMM       4'd11
`define ALUOP_MOVHI     4'd12
`define ALUOP_COMP      4'd13
`define ALUOP_MTSR      4'd14
`define ALUOP_MFSR      4'd15
 
`define ALUOP_WIDTH     4
 
/* Shift/rotate macros. */
`define SHROTOP_NOP     2'd0
`define SHROTOP_SLL     2'd0
`define SHROTOP_SRL     2'd1
`define SHROTOP_SRA     2'd2
`define SHROTOP_ROR     2'd3
 
`define SHROTOP_WIDTH   2
 
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define IC_LINESIZE             4
 
// Insn cache specific
`define ICSIZE                  13              // 8192
`define ICINDX                  `ICSIZE-2       // 11
`define ICINDXH                 `ICSIZE-1       // 12
`define ICTAGL                  `ICINDXH+1      // 13
 
`define OPERAND_WIDTH           32
`define REGFILE_ADDR_WIDTH      5
`define off     0
`define on      1
 
// Use fast (and bigger) version of mem2reg aligner
`define MEM2REG_FAST
 
// SHROT_OP position in machine word
`define SHROTOP_POS             7:6
 
// ALU instructions multicycle field in machine word
`define ALUMCYC_POS             9:8
 
// Execution cycles per instruction
`define MULTICYCLE_WIDTH        2
`define ONE_CYCLE               2'd0
`define TWO_CYCLES              2'd1
 
// Operand MUX selects
`define SEL_WIDTH               2
`define SEL_RF                  2'd0
`define SEL_IMM                 2'd1
`define SEL_EX_FORW             2'd2
`define SEL_WB_FORW             2'd3
 
// Branch ops
`define BRANCHOP_WIDTH          3
`define BRANCHOP_NOP            3'd0
`define BRANCHOP_J              3'd1
`define BRANCHOP_JR             3'd2
`define BRANCHOP_BAL            3'd3
`define BRANCHOP_BF             3'd4
`define BRANCHOP_BNF            3'd5
`define BRANCHOP_RFE            3'd6
 
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define LSUOP_WIDTH             4
`define LSUOP_NOP               4'b0000
`define LSUOP_LBZ               4'b0010
`define LSUOP_LBS               4'b0011
`define LSUOP_LHZ               4'b0100
`define LSUOP_LHS               4'b0101
`define LSUOP_LWZ               4'b0110
`define LSUOP_LWS               4'b0111
`define LSUOP_LD                4'b0001
`define LSUOP_SD                4'b1000
`define LSUOP_SB                4'b1010
`define LSUOP_SH                4'b1100
`define LSUOP_SW                4'b1110
 
// Fetch ops
`define FETCHOP_WIDTH           1
`define FETCHOP_NOP             1'b0
`define FETCHOP_LW              1'b1
 
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define RFWBOP_WIDTH            3
`define RFWBOP_NOP              3'b000
`define RFWBOP_ALU              3'b001
`define RFWBOP_LSU              3'b011
`define RFWBOP_SPRS             3'b101
`define RFWBOP_LR               3'b111
 
// Compare instructions
`define COP_SFEQ       'b000
`define COP_SFNE       'b001
`define COP_SFGT       'b010
`define COP_SFGE       'b011
`define COP_SFLT       'b100
`define COP_SFLE       'b101
`define COP_X          'b0111
`define SIGNED_COMPARE 'd3
`define COMPOP_WIDTH    4
 
`define LSUOP_WIDTH     4
 
`define PAGEINDX_WIDTH          13
`define ITLBADDR_WIDTH          7
 
// Exceptions
`define EXCEPT_WIDTH 4
 
`define EXCEPT_DTLBMISS         `EXCEPT_WIDTH'd7
`define EXCEPT_DMMUFAULT        `EXCEPT_WIDTH'd6
`define EXCEPT_INTHIGH          `EXCEPT_WIDTH'd5
`define EXCEPT_SYSCALL          `EXCEPT_WIDTH'd4
`define EXCEPT_ITLBMISS         `EXCEPT_WIDTH'd3
`define EXCEPT_IMMUFAULT        `EXCEPT_WIDTH'd2
`define EXCEPT_RESET            `EXCEPT_WIDTH'd1
`define EXCEPT_NONE             `EXCEPT_WIDTH'd0
 
// BIU Control 1 register
`define BCTRL1_WIDTH     30
`define BCTRL1_T0_CS0   3:0
`define BCTRL1_T0_CS0B  4
`define BCTRL1_T0_CS1   8:5
`define BCTRL1_T0_CS1B  9
`define BCTRL1_T0_CS2   13:10
`define BCTRL1_T0_CS2B  14
`define BCTRL1_T0_CS3   18:15
`define BCTRL1_T0_CS3B  19
`define BCTRL1_T0_CS4   23:20
`define BCTRL1_T0_CS4B  24
`define BCTRL1_T0_CS5   28:25
`define BCTRL1_T0_CS5B  29
 
// BIU Control 2 register
`define BCTRL2_WIDTH    28
`define BCTRL2_T0_CS6   3:0
`define BCTRL2_T0_CS6B  4
`define BCTRL2_T0_CS7   8:5
`define BCTRL2_T0_CS7B  9
`define BCTRL2_T1_CS0   13:10
`define BCTRL2_T1_CS0B  14
`define BCTRL2_T0_PARK2 15
`define BCTRL2_T0_PARK1 16
`define BCTRL2_T0_PARK0 17
`define BCTRL2_T1_PARK2 18
`define BCTRL2_T1_PARK1 19
`define BCTRL2_T1_PARK0 20
`define BCTRL2_I0_B     21
`define BCTRL2_I1_B     22
`define BCTRL2_I2_B     23
`define BCTRL2_I3_B     24
`define BCTRL2_I4_B     25
`define BCTRL2_I5_B     26
`define BCTRL2_CLKDIVBY2 27
 
`define PCTRL_WIDTH     29
// Peripheral Control register bits
`define PCTRL_RTC_RST   0
`define PCTRL_UART1_RST 1
`define PCTRL_UART2_RST 2
`define PCTRL_TC1_RST   3
`define PCTRL_TC2_RST   4
`define PCTRL_ETH1_RST  5
`define PCTRL_ETH2_RST  6
`define PCTRL_RTC_TM    7
`define PCTRL_VID_RST   8
`define PCTRL_GPIO_RST  9
`define PCTRL_TDM_RST   10
`define PCTRL_PLL_F     19:11
`define PCTRL_PLL_R     24:20
`define PCTRL_PLL_OD    26:25
`define PCTRL_PLL_PD    27
`define PCTRL_PLL_BP    28
 
`define SR_WIDTH 9
// SR bits (no CID)
`define SR_SUPV 0
`define SR_EXR  1
`define SR_EIR  2
`define SR_DCE  3
`define SR_ICE  4
`define SR_DME  5
`define SR_IME  6
`define SR_LEE  7
`define SR_CF   8
 
// Trace port
`define TP1W_WIDTH      23
`define TP1W_RF_TAA     4:0
`define TP1W_RF_TCENA   5
`define TP1W_RF_TOENA   6
`define TP1W_RF_TQOENA  7
`define TP1W_RF_TISA    8
`define TP1W_RF_TMSA    9
`define TP1W_RF_TAB     14:10
`define TP1W_RF_TCENB   15
`define TP1W_RF_TISB    16
`define TP1W_RF_TMSB    17
`define TP1W_RF_DSIB    18
`define TP1W_RF_SMSB    19
`define TP1W_MUXSEL     22:20
 
`define TP1R_WIDTH      14
`define TP1R_RF_DSOB    0
`define TP1R_RF_CENSQB  1
`define TP1R_RF_QSQA    2
`define TP1R_RF_OENSQA  3
`define TP1R_RF_ASQB    8:4
`define TP1R_RF_ASQA    13:9
 
 
`define TP2W_WIDTH      32
`define TP2W_DCR_TIS    0
`define TP2W_DCR_TMS    1
`define TP2W_DCR_TCEN   2
`define TP2W_DCR_TOEN   3
`define TP2W_DCR_TQOEN  4
`define TP2W_DCR_TWEN   5
`define TP2W_DCR_TA     16:6
`define TP2W_DCT_TIS    17
`define TP2W_DCT_TMS    18
`define TP2W_DCT_TCEN   19
`define TP2W_DCT_TOEN   20
`define TP2W_DCT_TQOEN  21
`define TP2W_DCT_TWEN   22
`define TP2W_DCT_TA     31:23
 
`define TP2R_WIDTH      26
`define TP2R_DCR_CENSQ  0
`define TP2R_DCR_OENSQ  1
`define TP2R_DCR_WENSQ  2
`define TP2R_DCR_ASQ    13:3
`define TP2R_DCT_CENSQ  14
`define TP2R_DCT_OENSQ  15
`define TP2R_DCT_WENSQ  16
`define TP2R_DCT_ASQ    25:17
 
 
`define TP3W_WIDTH      13
`define TP3W_DMT_TIS    0
`define TP3W_DMT_TMS    1
`define TP3W_DMT_TCEN   2
`define TP3W_DMT_TOEN   3
`define TP3W_DMT_TQOEN  4
`define TP3W_DMT_TWEN   5
`define TP3W_DMT_TA     12:6
 
`define TP3R_WIDTH      10
`define TP3R_DMT_CENSQ  0
`define TP3R_DMT_OENSQ  1
`define TP3R_DMT_WENSQ  2
`define TP3R_DMT_ASQ    9:3
 
 
`define TP4W_WIDTH      28
`define TP4W_IMT_TIS    0
`define TP4W_IMT_TMS    1
`define TP4W_IMT_TCEN   2
`define TP4W_IMT_TOEN   3
`define TP4W_IMT_TQOEN  4
`define TP4W_IMT_TWEN   5
`define TP4W_IMT_TA     12:6
`define TP4W_ICT_TIS    13
`define TP4W_ICT_TMS    14
`define TP4W_ICT_TCEN   15
`define TP4W_ICT_TOEN   16
`define TP4W_ICT_TQOEN  17
`define TP4W_ICT_TWEN   18
`define TP4W_ICT_TA     27:19
 
`define TP4R_WIDTH      22
`define TP4R_IMT_CENSQ  0
`define TP4R_IMT_OENSQ  1
`define TP4R_IMT_WENSQ  2
`define TP4R_IMT_ASQ    9:3
`define TP4R_ICT_CENSQ  10
`define TP4R_ICT_OENSQ  11
`define TP4R_ICT_WENSQ  12
`define TP4R_ICT_ASQ    21:13
 
// Access types
`define ACCESS_WIDTH            2
`define ACCESS_USER_READ        2'b00
`define ACCESS_USER_WRITE       2'b01
`define ACCESS_SUPV_READ        2'b10
`define ACCESS_SUPV_WRITE       2'b11
 
// SPRS
`define SPR_GROUP_BITS  31:27
`define SPR_GROUP_WIDTH 5
`define SPR_GROUP_SYS   5'd0
`define SPR_GROUP_PM    5'd8
`define SPR_GROUP_PIC   5'd9
`define SPR_GROUP_TT    5'd10
`define SPR_GROUP_ITLB  5'd28
`define SPR_GROUP_MODA  5'd29
`define SPR_GROUP_MODD  5'd30
`define SPR_GROUP_DTLB  5'd31
 
`define SPR_CFGR        3'd0
`define SPR_SR          7'd16
`define SPR_EPCR        7'd32
`define SPR_EEAR        7'd48
`define SPR_ESR         7'd64
 
 
// Bits that define the group
`define SPRGRP_BITS 15:11
 
// Bits that define offset inside the group
`define SPROFS_BITS 10:0
 
//
// Power Management
//
 
// Define it if you want PM implemented
`define PM_IMPLEMENTED
 
// Bit positions inside PMR (don't change)
`define PM_PMR_SDF 3:0
`define PM_PMR_DME 4
`define PM_PMR_SME 5
`define PM_PMR_DCGE 6
`define PM_PMR_UNUSED 31:7
 
// PMR offset inside PM group of registers
`define PM_OFS_PMR 11'b0
 
// PM group
`define SPRGRP_PM 5'd8
 
// Define if PMR can be read/written at any address inside PM group
`define PM_PARTIAL_DECODING
 
// Define if reading PMR is allowed
`define PM_READREGS
 
// Define if unused PMR bits should be zero
// `define PM_UNUSED_ZERO
 
//
// Programmable Interrupt Controller
//
 
// Define it if you want PIC implemented
`define PIC_IMPLEMENTED
 
// Define number of interrupt inputs (2-31)
`define PIC_INTS 20
 
// Address offsets of PIC registers inside PIC group
`define PIC_OFS_PICMR 2'd0
`define PIC_OFS_PICPR 2'd1
`define PIC_OFS_PICSR 2'd2
 
// Position of offset bits inside SPR address
`define PICOFS_BITS 1:0
 
// Define if you want these PIC registers to be implemented
`define PIC_PICMR
`define PIC_PICPR
`define PIC_PICSR
 
// Define if reading PIC registers is allowed
`define PIC_READREGS
 
// Define if unused PIC register bits should be zero
`define PIC_UNUSED_ZERO
 
//
// Tick Timer
//
 
// Define it if you want TT implemented
`define TT_IMPLEMENTED
 
// Address offsets of TT registers inside TT group
`define TT_OFS_TTMR 1'd0
`define TT_OFS_TTCR 1'd1
 
// Position of offset bits inside SPR group
`define TTOFS_BITS 0
 
// Define if you want these TT registers to be implemented
`define TT_TTMR
`define TT_TTCR
 
// TTMR bits
`define TT_TTMR_TP 27:0
`define TT_TTMR_IP 28
`define TT_TTMR_IE 29
`define TT_TTMR_M 31:30
 
// Define if reading TT registers is allowed
`define TT_READREGS
 
 
//
// VR, UPR and Configuration Registers
//
 
// Define if you want configuration registers implemented
`define CFGR_IMPLEMENTED
 
// Define if you want full address decode inside SYS group
`define SYS_FULL_DECODE
 
// Offsets of VR, UPR and CFGR registers
`define SPRGRP_SYS_VR           4'h0
`define SPRGRP_SYS_UPR          4'h1
`define SPRGRP_SYS_CPUCFGR      4'h2
`define SPRGRP_SYS_DMMUCFGR     4'h3
`define SPRGRP_SYS_IMMUCFGR     4'h4
`define SPRGRP_SYS_DCCFGR       4'h5
`define SPRGRP_SYS_ICCFGR       4'h6
`define SPRGRP_SYS_DCFGR        4'h7
 
// VR fields
`define VR_REV_BITS             5:0
`define VR_RES1_BITS            15:6
`define VR_CFG_BITS             23:16
`define VR_VER_BITS             31:24
 
// VR values
`define VR_REV                  6'h00
`define VR_RES1                 10'h000
`define VR_CFG                  8'h00
`define VR_VER                  8'h12
 
// UPR fields
`define UPR_UP_BITS             0
`define UPR_DCP_BITS            1
`define UPR_ICP_BITS            2
`define UPR_DMP_BITS            3
`define UPR_IMP_BITS            4
`define UPR_MP_BITS             5
`define UPR_DUP_BITS            6
`define UPR_PCUP_BITS           7
`define UPR_PMP_BITS            8
`define UPR_PICP_BITS           9
`define UPR_TTP_BITS            10
`define UPR_RES1_BITS           23:11
`define UPR_CUP_BITS            31:24
 
// UPR values
`define UPR_UP                  1'b1
`define UPR_DCP                 1'b1
`define UPR_ICP                 1'b1
`define UPR_DMP                 1'b1
`define UPR_IMP                 1'b1
`define UPR_MP                  1'b1
`define UPR_DUP                 1'b1
`define UPR_PCUP                1'b0
`define UPR_PMP                 1'b1
`define UPR_PICP                1'b1
`define UPR_TTP                 1'b1
`define UPR_RES1                13'h0000
`define UPR_CUP                 8'h00
 
// CPUCFGR fields
`define CPUCFGR_NSGF_BITS       3:0
`define CPUCFGR_HGF_BITS        4
`define CPUCFGR_OB32S_BITS      5
`define CPUCFGR_OB64S_BITS      6
`define CPUCFGR_OF32S_BITS      7
`define CPUCFGR_OF64S_BITS      8
`define CPUCFGR_OV64S_BITS      9
`define CPUCFGR_RES1_BITS       31:10
 
// CPUCFGR values
`define CPUCFGR_NSGF            4'h0
`define CPUCFGR_HGF             1'b0
`define CPUCFGR_OB32S           1'b1
`define CPUCFGR_OB64S           1'b0
`define CPUCFGR_OF32S           1'b0
`define CPUCFGR_OF64S           1'b0
`define CPUCFGR_OV64S           1'b0
`define CPUCFGR_RES1            22'h000000
 
// DMMUCFGR fields
`define DMMUCFGR_NTW_BITS       1:0
`define DMMUCFGR_NTS_BITS       4:2
`define DMMUCFGR_NAE_BITS       7:5
`define DMMUCFGR_CRI_BITS       8
`define DMMUCFGR_PRI_BITS       9
`define DMMUCFGR_TEIRI_BITS     10
`define DMMUCFGR_HTR_BITS       11
`define DMMUCFGR_RES1_BITS      31:12
 
// DMMUCFGR values
`define DMMUCFGR_NTW            2'h0
`define DMMUCFGR_NTS            3'h5
`define DMMUCFGR_NAE            3'h0
`define DMMUCFGR_CRI            1'b0
`define DMMUCFGR_PRI            1'b0
`define DMMUCFGR_TEIRI          1'b1
`define DMMUCFGR_HTR            1'b0
`define DMMUCFGR_RES1           20'h00000
 
// IMMUCFGR fields
`define IMMUCFGR_NTW_BITS       1:0
`define IMMUCFGR_NTS_BITS       4:2
`define IMMUCFGR_NAE_BITS       7:5
`define IMMUCFGR_CRI_BITS       8
`define IMMUCFGR_PRI_BITS       9
`define IMMUCFGR_TEIRI_BITS     10
`define IMMUCFGR_HTR_BITS       11
`define IMMUCFGR_RES1_BITS      31:12
 
// IMMUCFGR values
`define IMMUCFGR_NTW            2'h0
`define IMMUCFGR_NTS            3'h5
`define IMMUCFGR_NAE            3'h0
`define IMMUCFGR_CRI            1'b0
`define IMMUCFGR_PRI            1'b0
`define IMMUCFGR_TEIRI          1'b1
`define IMMUCFGR_HTR            1'b0
`define IMMUCFGR_RES1           20'h00000
 
// DCCFGR fields
`define DCCFGR_NCW_BITS         2:0
`define DCCFGR_NCS_BITS         6:3
`define DCCFGR_CBS_BITS         7
`define DCCFGR_CWS_BITS         8
`define DCCFGR_CCRI_BITS        9
`define DCCFGR_CBIRI_BITS       10
`define DCCFGR_CBPRI_BITS       11
`define DCCFGR_CBLRI_BITS       12
`define DCCFGR_CBFRI_BITS       13
`define DCCFGR_CBWBRI_BITS      14
`define DCCFGR_RES1_BITS        31:15
 
// DCCFGR values
`define DCCFGR_NCW              3'h0
`define DCCFGR_NCS              4'h5
`define DCCFGR_CBS              1'b0
`define DCCFGR_CWS              1'b0
`define DCCFGR_CCRI             1'b1
`define DCCFGR_CBIRI            1'b1
`define DCCFGR_CBPRI            1'b0
`define DCCFGR_CBLRI            1'b0
`define DCCFGR_CBFRI            1'b0
`define DCCFGR_CBWBRI           1'b1
`define DCCFGR_RES1             17'h00000
 
// ICCFGR fields
`define ICCFGR_NCW_BITS         2:0
`define ICCFGR_NCS_BITS         6:3
`define ICCFGR_CBS_BITS         7
`define ICCFGR_CWS_BITS         8
`define ICCFGR_CCRI_BITS        9
`define ICCFGR_CBIRI_BITS       10
`define ICCFGR_CBPRI_BITS       11
`define ICCFGR_CBLRI_BITS       12
`define ICCFGR_CBFRI_BITS       13
`define ICCFGR_CBWBRI_BITS      14
`define ICCFGR_RES1_BITS        31:15
 
// ICCFGR values
`define ICCFGR_NCW              3'h0
`define ICCFGR_NCS              4'h5
`define ICCFGR_CBS              1'b0
`define ICCFGR_CWS              1'b0
`define ICCFGR_CCRI             1'b1
`define ICCFGR_CBIRI            1'b1
`define ICCFGR_CBPRI            1'b0
`define ICCFGR_CBLRI            1'b0
`define ICCFGR_CBFRI            1'b0
`define ICCFGR_CBWBRI           1'b1
`define ICCFGR_RES1             17'h00000
 
// DCFGR fields
`define DCFGR_NDP_BITS          2:0
`define DCFGR_WPCI_BITS         3
`define DCFGR_RES1_BITS         31:4
 
// DCFGR values
`define DCFGR_NDP               3'h0
`define DCFGR_WPCI              1'b0
`define DCFGR_RES1              28'h0000000
 
 
// Instruction opcode groups (basic)
`define OR32_J                 6'b000000
`define OR32_JAL               6'b000001
`define OR32_BNF               6'b000011
`define OR32_BF                6'b000100
`define OR32_NOP               6'b000101
`define OR32_MOVHI             6'b000110
`define OR32_MFSPR             6'b000111
`define OR32_XSYNC             6'b001000
`define OR32_RFE               6'b001001
 
`define OR32_MTSPR             6'b010000
`define OR32_JR                6'b010001
`define OR32_JALR              6'b010010
 
`define OR32_LWZ               6'b100001
`define OR32_LBZ               6'b100011
`define OR32_LBS               6'b100100
`define OR32_LHZ               6'b100101
`define OR32_LHS               6'b100110
`define OR32_ADDI              6'b100111
`define OR32_ADDIC             6'b101000
`define OR32_ANDI              6'b101001
`define OR32_ORI               6'b101010
`define OR32_XORI              6'b101011
`define OR32_MULI              6'b101100
`define OR32_MACI              6'b101101
`define OR32_SH_ROTI           6'b101110
`define OR32_SFXXI             6'b101111
 
`define OR32_SW                6'b110101
`define OR32_SB                6'b110110
`define OR32_SH                6'b110111
`define OR32_ALU               6'b111000
`define OR32_SFXX              6'b111001
 

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Line No.	Rev	Author	Line
1	168	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's definitions ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Parameters of the OR1200 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - add parameters that are missing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	170	lampret	`// Revision 1.1 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.2 2001/07/22 03:31:54 lampret`
51			`// Fixed RAM's oen bug. Cache bypass under development.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:03 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`define ARTISAN_SSP
59			//`define ARTISAN_STP
60
61			`// Dump VCD`
62			`define VCD_DUMP
63
64			`//`
65			`// Implement rotate in the ALU`
66			`//`
67			`define IMPL_ALU_ROTATE
68
69			`//`
70			`// Which type of compare to implement`
71			`//`
72			//`define IMPL_ALU_COMP1
73			`define IMPL_ALU_COMP2
74
75			`//`
76			`// Simulate l.div and l.divu`
77			`//`
78			`define SIM_ALU_DIV
79			`define SIM_ALU_DIVU
80
81			`define ALUOP_NOP 4'd0
82
83			`/* Order defined by arith insns that have two source operands both in regs`
84			`(see binutils/include/opcode/or32.h) */`
85			`define ALUOP_ADD 4'd0
86			`define ALUOP_ADDC 4'd1
87			`define ALUOP_SUB 4'd2
88			`define ALUOP_AND 4'd3
89			`define ALUOP_OR 4'd4
90			`define ALUOP_XOR 4'd5
91			`define ALUOP_MUL 4'd6
92			`define ALUOP_MAC 4'd7
93			`define ALUOP_SHROT 4'd8
94			`define ALUOP_DIV 4'd9
95			`define ALUOP_DIVU 4'd10
96
97			`/* Order not specifically defined. */`
98			`define ALUOP_IMM 4'd11
99			`define ALUOP_MOVHI 4'd12
100			`define ALUOP_COMP 4'd13
101			`define ALUOP_MTSR 4'd14
102			`define ALUOP_MFSR 4'd15
103
104			`define ALUOP_WIDTH 4
105
106			`/* Shift/rotate macros. */`
107			`define SHROTOP_NOP 2'd0
108			`define SHROTOP_SLL 2'd0
109			`define SHROTOP_SRL 2'd1
110			`define SHROTOP_SRA 2'd2
111			`define SHROTOP_ROR 2'd3
112
113			`define SHROTOP_WIDTH 2
114
115
116			`// 3 for 8 bytes, 4 for 16 bytes etc`
117			`define IC_LINESIZE 4
118
119			`// Insn cache specific`
120			`define ICSIZE 13 // 8192
121			`define ICINDX `ICSIZE-2 // 11
122			`define ICINDXH `ICSIZE-1 // 12
123			`define ICTAGL `ICINDXH+1 // 13
124
125			`define OPERAND_WIDTH 32
126			`define REGFILE_ADDR_WIDTH 5
127			`define off 0
128			`define on 1
129
130			`// Use fast (and bigger) version of mem2reg aligner`
131			`define MEM2REG_FAST
132
133			`// SHROT_OP position in machine word`
134			`define SHROTOP_POS 7:6
135
136			`// ALU instructions multicycle field in machine word`
137			`define ALUMCYC_POS 9:8
138
139			`// Execution cycles per instruction`
140			`define MULTICYCLE_WIDTH 2
141			`define ONE_CYCLE 2'd0
142			`define TWO_CYCLES 2'd1
143
144			`// Operand MUX selects`
145			`define SEL_WIDTH 2
146			`define SEL_RF 2'd0
147			`define SEL_IMM 2'd1
148			`define SEL_EX_FORW 2'd2
149			`define SEL_WB_FORW 2'd3
150
151			`// Branch ops`
152			`define BRANCHOP_WIDTH 3
153			`define BRANCHOP_NOP 3'd0
154			`define BRANCHOP_J 3'd1
155			`define BRANCHOP_JR 3'd2
156			`define BRANCHOP_BAL 3'd3
157			`define BRANCHOP_BF 3'd4
158			`define BRANCHOP_BNF 3'd5
159			`define BRANCHOP_RFE 3'd6
160
161			`// Bit 0: sign extend`
162			`// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword`
163			`// Bit 3: 0 load, 1 store`
164			`define LSUOP_WIDTH 4
165			`define LSUOP_NOP 4'b0000
166			`define LSUOP_LBZ 4'b0010
167			`define LSUOP_LBS 4'b0011
168			`define LSUOP_LHZ 4'b0100
169			`define LSUOP_LHS 4'b0101
170			`define LSUOP_LWZ 4'b0110
171			`define LSUOP_LWS 4'b0111
172			`define LSUOP_LD 4'b0001
173			`define LSUOP_SD 4'b1000
174			`define LSUOP_SB 4'b1010
175			`define LSUOP_SH 4'b1100
176			`define LSUOP_SW 4'b1110
177
178			`// Fetch ops`
179			`define FETCHOP_WIDTH 1
180			`define FETCHOP_NOP 1'b0
181			`define FETCHOP_LW 1'b1
182
183			`// Bit 0: register file write enable`
184			`// Bits 2-1: write-back mux selects`
185			`define RFWBOP_WIDTH 3
186			`define RFWBOP_NOP 3'b000
187			`define RFWBOP_ALU 3'b001
188			`define RFWBOP_LSU 3'b011
189			`define RFWBOP_SPRS 3'b101
190			`define RFWBOP_LR 3'b111
191
192			`// Compare instructions`
193			`define COP_SFEQ 'b000
194			`define COP_SFNE 'b001
195			`define COP_SFGT 'b010
196			`define COP_SFGE 'b011
197			`define COP_SFLT 'b100
198			`define COP_SFLE 'b101
199			`define COP_X 'b0111
200			`define SIGNED_COMPARE 'd3
201			`define COMPOP_WIDTH 4
202
203			`define LSUOP_WIDTH 4
204
205			`define PAGEINDX_WIDTH 13
206			`define ITLBADDR_WIDTH 7
207
208			`// Exceptions`
209			`define EXCEPT_WIDTH 4
210
211			`define EXCEPT_DTLBMISS `EXCEPT_WIDTH'd7
212			`define EXCEPT_DMMUFAULT `EXCEPT_WIDTH'd6
213			`define EXCEPT_INTHIGH `EXCEPT_WIDTH'd5
214			`define EXCEPT_SYSCALL `EXCEPT_WIDTH'd4
215			`define EXCEPT_ITLBMISS `EXCEPT_WIDTH'd3
216			`define EXCEPT_IMMUFAULT `EXCEPT_WIDTH'd2
217			`define EXCEPT_RESET `EXCEPT_WIDTH'd1
218			`define EXCEPT_NONE `EXCEPT_WIDTH'd0
219
220			`// BIU Control 1 register`
221			`define BCTRL1_WIDTH 30
222			`define BCTRL1_T0_CS0 3:0
223			`define BCTRL1_T0_CS0B 4
224			`define BCTRL1_T0_CS1 8:5
225			`define BCTRL1_T0_CS1B 9
226			`define BCTRL1_T0_CS2 13:10
227			`define BCTRL1_T0_CS2B 14
228			`define BCTRL1_T0_CS3 18:15
229			`define BCTRL1_T0_CS3B 19
230			`define BCTRL1_T0_CS4 23:20
231			`define BCTRL1_T0_CS4B 24
232			`define BCTRL1_T0_CS5 28:25
233			`define BCTRL1_T0_CS5B 29
234
235			`// BIU Control 2 register`
236			`define BCTRL2_WIDTH 28
237			`define BCTRL2_T0_CS6 3:0
238			`define BCTRL2_T0_CS6B 4
239			`define BCTRL2_T0_CS7 8:5
240			`define BCTRL2_T0_CS7B 9
241			`define BCTRL2_T1_CS0 13:10
242			`define BCTRL2_T1_CS0B 14
243			`define BCTRL2_T0_PARK2 15
244			`define BCTRL2_T0_PARK1 16
245			`define BCTRL2_T0_PARK0 17
246			`define BCTRL2_T1_PARK2 18
247			`define BCTRL2_T1_PARK1 19
248			`define BCTRL2_T1_PARK0 20
249			`define BCTRL2_I0_B 21
250			`define BCTRL2_I1_B 22
251			`define BCTRL2_I2_B 23
252			`define BCTRL2_I3_B 24
253			`define BCTRL2_I4_B 25
254			`define BCTRL2_I5_B 26
255			`define BCTRL2_CLKDIVBY2 27
256
257			`define PCTRL_WIDTH 29
258			`// Peripheral Control register bits`
259			`define PCTRL_RTC_RST 0
260			`define PCTRL_UART1_RST 1
261			`define PCTRL_UART2_RST 2
262			`define PCTRL_TC1_RST 3
263			`define PCTRL_TC2_RST 4
264			`define PCTRL_ETH1_RST 5
265			`define PCTRL_ETH2_RST 6
266			`define PCTRL_RTC_TM 7
267			`define PCTRL_VID_RST 8
268			`define PCTRL_GPIO_RST 9
269			`define PCTRL_TDM_RST 10
270			`define PCTRL_PLL_F 19:11
271			`define PCTRL_PLL_R 24:20
272			`define PCTRL_PLL_OD 26:25
273			`define PCTRL_PLL_PD 27
274			`define PCTRL_PLL_BP 28
275
276			`define SR_WIDTH 9
277			`// SR bits (no CID)`
278			`define SR_SUPV 0
279			`define SR_EXR 1
280			`define SR_EIR 2
281			`define SR_DCE 3
282			`define SR_ICE 4
283			`define SR_DME 5
284			`define SR_IME 6
285			`define SR_LEE 7
286			`define SR_CF 8
287
288			`// Trace port`
289			`define TP1W_WIDTH 23
290			`define TP1W_RF_TAA 4:0
291			`define TP1W_RF_TCENA 5
292			`define TP1W_RF_TOENA 6
293			`define TP1W_RF_TQOENA 7
294			`define TP1W_RF_TISA 8
295			`define TP1W_RF_TMSA 9
296			`define TP1W_RF_TAB 14:10
297			`define TP1W_RF_TCENB 15
298			`define TP1W_RF_TISB 16
299			`define TP1W_RF_TMSB 17
300			`define TP1W_RF_DSIB 18
301			`define TP1W_RF_SMSB 19
302			`define TP1W_MUXSEL 22:20
303
304			`define TP1R_WIDTH 14
305			`define TP1R_RF_DSOB 0
306			`define TP1R_RF_CENSQB 1
307			`define TP1R_RF_QSQA 2
308			`define TP1R_RF_OENSQA 3
309			`define TP1R_RF_ASQB 8:4
310			`define TP1R_RF_ASQA 13:9
311
312
313			`define TP2W_WIDTH 32
314			`define TP2W_DCR_TIS 0
315			`define TP2W_DCR_TMS 1
316			`define TP2W_DCR_TCEN 2
317			`define TP2W_DCR_TOEN 3
318			`define TP2W_DCR_TQOEN 4
319			`define TP2W_DCR_TWEN 5
320			`define TP2W_DCR_TA 16:6
321			`define TP2W_DCT_TIS 17
322			`define TP2W_DCT_TMS 18
323			`define TP2W_DCT_TCEN 19
324			`define TP2W_DCT_TOEN 20
325			`define TP2W_DCT_TQOEN 21
326			`define TP2W_DCT_TWEN 22
327			`define TP2W_DCT_TA 31:23
328
329			`define TP2R_WIDTH 26
330			`define TP2R_DCR_CENSQ 0
331			`define TP2R_DCR_OENSQ 1
332			`define TP2R_DCR_WENSQ 2
333			`define TP2R_DCR_ASQ 13:3
334			`define TP2R_DCT_CENSQ 14
335			`define TP2R_DCT_OENSQ 15
336			`define TP2R_DCT_WENSQ 16
337			`define TP2R_DCT_ASQ 25:17
338
339
340			`define TP3W_WIDTH 13
341			`define TP3W_DMT_TIS 0
342			`define TP3W_DMT_TMS 1
343			`define TP3W_DMT_TCEN 2
344			`define TP3W_DMT_TOEN 3
345			`define TP3W_DMT_TQOEN 4
346			`define TP3W_DMT_TWEN 5
347			`define TP3W_DMT_TA 12:6
348
349			`define TP3R_WIDTH 10
350			`define TP3R_DMT_CENSQ 0
351			`define TP3R_DMT_OENSQ 1
352			`define TP3R_DMT_WENSQ 2
353			`define TP3R_DMT_ASQ 9:3
354
355
356			`define TP4W_WIDTH 28
357			`define TP4W_IMT_TIS 0
358			`define TP4W_IMT_TMS 1
359			`define TP4W_IMT_TCEN 2
360			`define TP4W_IMT_TOEN 3
361			`define TP4W_IMT_TQOEN 4
362			`define TP4W_IMT_TWEN 5
363			`define TP4W_IMT_TA 12:6
364			`define TP4W_ICT_TIS 13
365			`define TP4W_ICT_TMS 14
366			`define TP4W_ICT_TCEN 15
367			`define TP4W_ICT_TOEN 16
368			`define TP4W_ICT_TQOEN 17
369			`define TP4W_ICT_TWEN 18
370			`define TP4W_ICT_TA 27:19
371
372			`define TP4R_WIDTH 22
373			`define TP4R_IMT_CENSQ 0
374			`define TP4R_IMT_OENSQ 1
375			`define TP4R_IMT_WENSQ 2
376			`define TP4R_IMT_ASQ 9:3
377			`define TP4R_ICT_CENSQ 10
378			`define TP4R_ICT_OENSQ 11
379			`define TP4R_ICT_WENSQ 12
380			`define TP4R_ICT_ASQ 21:13
381
382			`// Access types`
383			`define ACCESS_WIDTH 2
384			`define ACCESS_USER_READ 2'b00
385			`define ACCESS_USER_WRITE 2'b01
386			`define ACCESS_SUPV_READ 2'b10
387			`define ACCESS_SUPV_WRITE 2'b11
388
389			`// SPRS`
390			`define SPR_GROUP_BITS 31:27
391			`define SPR_GROUP_WIDTH 5
392			`define SPR_GROUP_SYS 5'd0
393			`define SPR_GROUP_PM 5'd8
394			`define SPR_GROUP_PIC 5'd9
395			`define SPR_GROUP_TT 5'd10
396			`define SPR_GROUP_ITLB 5'd28
397			`define SPR_GROUP_MODA 5'd29
398			`define SPR_GROUP_MODD 5'd30
399			`define SPR_GROUP_DTLB 5'd31
400
401	170	lampret	`define SPR_CFGR 3'd0
402			`define SPR_SR 7'd16
403			`define SPR_EPCR 7'd32
404	168	lampret	`define SPR_EEAR 7'd48
405			`define SPR_ESR 7'd64
406
407
408			`// Bits that define the group`
409			`define SPRGRP_BITS 15:11
410
411			`// Bits that define offset inside the group`
412			`define SPROFS_BITS 10:0
413
414			`//`
415			`// Power Management`
416			`//`
417
418			`// Define it if you want PM implemented`
419			`define PM_IMPLEMENTED
420
421			`// Bit positions inside PMR (don't change)`
422			`define PM_PMR_SDF 3:0
423			`define PM_PMR_DME 4
424			`define PM_PMR_SME 5
425			`define PM_PMR_DCGE 6
426			`define PM_PMR_UNUSED 31:7
427
428			`// PMR offset inside PM group of registers`
429			`define PM_OFS_PMR 11'b0
430
431			`// PM group`
432			`define SPRGRP_PM 5'd8
433
434			`// Define if PMR can be read/written at any address inside PM group`
435			`define PM_PARTIAL_DECODING
436
437			`// Define if reading PMR is allowed`
438			`define PM_READREGS
439
440			`// Define if unused PMR bits should be zero`
441			// `define PM_UNUSED_ZERO
442
443			`//`
444			`// Programmable Interrupt Controller`
445			`//`
446
447			`// Define it if you want PIC implemented`
448			`define PIC_IMPLEMENTED
449
450			`// Define number of interrupt inputs (2-31)`
451			`define PIC_INTS 20
452
453			`// Address offsets of PIC registers inside PIC group`
454			`define PIC_OFS_PICMR 2'd0
455			`define PIC_OFS_PICPR 2'd1
456			`define PIC_OFS_PICSR 2'd2
457
458			`// Position of offset bits inside SPR address`
459			`define PICOFS_BITS 1:0
460
461			`// Define if you want these PIC registers to be implemented`
462			`define PIC_PICMR
463			`define PIC_PICPR
464			`define PIC_PICSR
465
466			`// Define if reading PIC registers is allowed`
467			`define PIC_READREGS
468
469			`// Define if unused PIC register bits should be zero`
470			`define PIC_UNUSED_ZERO
471
472			`//`
473			`// Tick Timer`
474			`//`
475
476			`// Define it if you want TT implemented`
477			`define TT_IMPLEMENTED
478
479			`// Address offsets of TT registers inside TT group`
480			`define TT_OFS_TTMR 1'd0
481			`define TT_OFS_TTCR 1'd1
482
483			`// Position of offset bits inside SPR group`
484			`define TTOFS_BITS 0
485
486			`// Define if you want these TT registers to be implemented`
487			`define TT_TTMR
488			`define TT_TTCR
489
490			`// TTMR bits`
491			`define TT_TTMR_TP 27:0
492			`define TT_TTMR_IP 28
493			`define TT_TTMR_IE 29
494			`define TT_TTMR_M 31:30
495
496			`// Define if reading TT registers is allowed`
497			`define TT_READREGS
498
499
500			`//`
501			`// VR, UPR and Configuration Registers`
502			`//`
503
504			`// Define if you want configuration registers implemented`
505			`define CFGR_IMPLEMENTED
506
507			`// Define if you want full address decode inside SYS group`
508			`define SYS_FULL_DECODE
509
510			`// Offsets of VR, UPR and CFGR registers`
511			`define SPRGRP_SYS_VR 4'h0
512			`define SPRGRP_SYS_UPR 4'h1
513			`define SPRGRP_SYS_CPUCFGR 4'h2
514			`define SPRGRP_SYS_DMMUCFGR 4'h3
515			`define SPRGRP_SYS_IMMUCFGR 4'h4
516			`define SPRGRP_SYS_DCCFGR 4'h5
517			`define SPRGRP_SYS_ICCFGR 4'h6
518			`define SPRGRP_SYS_DCFGR 4'h7
519
520			`// VR fields`
521			`define VR_REV_BITS 5:0
522			`define VR_RES1_BITS 15:6
523			`define VR_CFG_BITS 23:16
524			`define VR_VER_BITS 31:24
525
526			`// VR values`
527			`define VR_REV 6'h00
528			`define VR_RES1 10'h000
529			`define VR_CFG 8'h00
530			`define VR_VER 8'h12
531
532			`// UPR fields`
533			`define UPR_UP_BITS 0
534			`define UPR_DCP_BITS 1
535			`define UPR_ICP_BITS 2
536			`define UPR_DMP_BITS 3
537			`define UPR_IMP_BITS 4
538			`define UPR_MP_BITS 5
539			`define UPR_DUP_BITS 6
540			`define UPR_PCUP_BITS 7
541			`define UPR_PMP_BITS 8
542			`define UPR_PICP_BITS 9
543			`define UPR_TTP_BITS 10
544			`define UPR_RES1_BITS 23:11
545			`define UPR_CUP_BITS 31:24
546
547			`// UPR values`
548			`define UPR_UP 1'b1
549			`define UPR_DCP 1'b1
550			`define UPR_ICP 1'b1
551			`define UPR_DMP 1'b1
552			`define UPR_IMP 1'b1
553			`define UPR_MP 1'b1
554			`define UPR_DUP 1'b1
555			`define UPR_PCUP 1'b0
556			`define UPR_PMP 1'b1
557			`define UPR_PICP 1'b1
558			`define UPR_TTP 1'b1
559			`define UPR_RES1 13'h0000
560			`define UPR_CUP 8'h00
561
562			`// CPUCFGR fields`
563			`define CPUCFGR_NSGF_BITS 3:0
564			`define CPUCFGR_HGF_BITS 4
565			`define CPUCFGR_OB32S_BITS 5
566			`define CPUCFGR_OB64S_BITS 6
567			`define CPUCFGR_OF32S_BITS 7
568			`define CPUCFGR_OF64S_BITS 8
569			`define CPUCFGR_OV64S_BITS 9
570			`define CPUCFGR_RES1_BITS 31:10
571
572			`// CPUCFGR values`
573			`define CPUCFGR_NSGF 4'h0
574			`define CPUCFGR_HGF 1'b0
575			`define CPUCFGR_OB32S 1'b1
576			`define CPUCFGR_OB64S 1'b0
577			`define CPUCFGR_OF32S 1'b0
578			`define CPUCFGR_OF64S 1'b0
579			`define CPUCFGR_OV64S 1'b0
580			`define CPUCFGR_RES1 22'h000000
581
582			`// DMMUCFGR fields`
583			`define DMMUCFGR_NTW_BITS 1:0
584			`define DMMUCFGR_NTS_BITS 4:2
585			`define DMMUCFGR_NAE_BITS 7:5
586			`define DMMUCFGR_CRI_BITS 8
587			`define DMMUCFGR_PRI_BITS 9
588			`define DMMUCFGR_TEIRI_BITS 10
589			`define DMMUCFGR_HTR_BITS 11
590			`define DMMUCFGR_RES1_BITS 31:12
591
592			`// DMMUCFGR values`
593			`define DMMUCFGR_NTW 2'h0
594			`define DMMUCFGR_NTS 3'h5
595			`define DMMUCFGR_NAE 3'h0
596			`define DMMUCFGR_CRI 1'b0
597			`define DMMUCFGR_PRI 1'b0
598			`define DMMUCFGR_TEIRI 1'b1
599			`define DMMUCFGR_HTR 1'b0
600			`define DMMUCFGR_RES1 20'h00000
601
602			`// IMMUCFGR fields`
603			`define IMMUCFGR_NTW_BITS 1:0
604			`define IMMUCFGR_NTS_BITS 4:2
605			`define IMMUCFGR_NAE_BITS 7:5
606			`define IMMUCFGR_CRI_BITS 8
607			`define IMMUCFGR_PRI_BITS 9
608			`define IMMUCFGR_TEIRI_BITS 10
609			`define IMMUCFGR_HTR_BITS 11
610			`define IMMUCFGR_RES1_BITS 31:12
611
612			`// IMMUCFGR values`
613			`define IMMUCFGR_NTW 2'h0
614			`define IMMUCFGR_NTS 3'h5
615			`define IMMUCFGR_NAE 3'h0
616			`define IMMUCFGR_CRI 1'b0
617			`define IMMUCFGR_PRI 1'b0
618			`define IMMUCFGR_TEIRI 1'b1
619			`define IMMUCFGR_HTR 1'b0
620			`define IMMUCFGR_RES1 20'h00000
621
622			`// DCCFGR fields`
623			`define DCCFGR_NCW_BITS 2:0
624			`define DCCFGR_NCS_BITS 6:3
625			`define DCCFGR_CBS_BITS 7
626			`define DCCFGR_CWS_BITS 8
627			`define DCCFGR_CCRI_BITS 9
628			`define DCCFGR_CBIRI_BITS 10
629			`define DCCFGR_CBPRI_BITS 11
630			`define DCCFGR_CBLRI_BITS 12
631			`define DCCFGR_CBFRI_BITS 13
632			`define DCCFGR_CBWBRI_BITS 14
633			`define DCCFGR_RES1_BITS 31:15
634
635			`// DCCFGR values`
636			`define DCCFGR_NCW 3'h0
637			`define DCCFGR_NCS 4'h5
638			`define DCCFGR_CBS 1'b0
639			`define DCCFGR_CWS 1'b0
640			`define DCCFGR_CCRI 1'b1
641			`define DCCFGR_CBIRI 1'b1
642			`define DCCFGR_CBPRI 1'b0
643			`define DCCFGR_CBLRI 1'b0
644			`define DCCFGR_CBFRI 1'b0
645			`define DCCFGR_CBWBRI 1'b1
646			`define DCCFGR_RES1 17'h00000
647
648			`// ICCFGR fields`
649			`define ICCFGR_NCW_BITS 2:0
650			`define ICCFGR_NCS_BITS 6:3
651			`define ICCFGR_CBS_BITS 7
652			`define ICCFGR_CWS_BITS 8
653			`define ICCFGR_CCRI_BITS 9
654			`define ICCFGR_CBIRI_BITS 10
655			`define ICCFGR_CBPRI_BITS 11
656			`define ICCFGR_CBLRI_BITS 12
657			`define ICCFGR_CBFRI_BITS 13
658			`define ICCFGR_CBWBRI_BITS 14
659			`define ICCFGR_RES1_BITS 31:15
660
661			`// ICCFGR values`
662			`define ICCFGR_NCW 3'h0
663			`define ICCFGR_NCS 4'h5
664			`define ICCFGR_CBS 1'b0
665			`define ICCFGR_CWS 1'b0
666			`define ICCFGR_CCRI 1'b1
667			`define ICCFGR_CBIRI 1'b1
668			`define ICCFGR_CBPRI 1'b0
669			`define ICCFGR_CBLRI 1'b0
670			`define ICCFGR_CBFRI 1'b0
671			`define ICCFGR_CBWBRI 1'b1
672			`define ICCFGR_RES1 17'h00000
673
674			`// DCFGR fields`
675			`define DCFGR_NDP_BITS 2:0
676			`define DCFGR_WPCI_BITS 3
677			`define DCFGR_RES1_BITS 31:4
678
679			`// DCFGR values`
680			`define DCFGR_NDP 3'h0
681			`define DCFGR_WPCI 1'b0
682			`define DCFGR_RES1 28'h0000000
683
684
685			`// Instruction opcode groups (basic)`
686			`define OR32_J 6'b000000
687			`define OR32_JAL 6'b000001
688			`define OR32_BNF 6'b000011
689			`define OR32_BF 6'b000100
690			`define OR32_NOP 6'b000101
691			`define OR32_MOVHI 6'b000110
692			`define OR32_MFSPR 6'b000111
693			`define OR32_XSYNC 6'b001000
694			`define OR32_RFE 6'b001001
695
696			`define OR32_MTSPR 6'b010000
697			`define OR32_JR 6'b010001
698			`define OR32_JALR 6'b010010
699
700			`define OR32_LWZ 6'b100001
701			`define OR32_LBZ 6'b100011
702			`define OR32_LBS 6'b100100
703			`define OR32_LHZ 6'b100101
704			`define OR32_LHS 6'b100110
705			`define OR32_ADDI 6'b100111
706			`define OR32_ADDIC 6'b101000
707			`define OR32_ANDI 6'b101001
708			`define OR32_ORI 6'b101010
709			`define OR32_XORI 6'b101011
710			`define OR32_MULI 6'b101100
711			`define OR32_MACI 6'b101101
712			`define OR32_SH_ROTI 6'b101110
713			`define OR32_SFXXI 6'b101111
714
715			`define OR32_SW 6'b110101
716			`define OR32_SB 6'b110110
717			`define OR32_SH 6'b110111
718			`define OR32_ALU 6'b111000
719			`define OR32_SFXX 6'b111001
720