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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data MMU top level                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of all DMMU blocks.                           ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/17 08:03:35  lampret
// *** empty log message ***
//
// Revision 1.2  2001/07/22 03:31:53  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Data MMU
//
 
module dmmu(
        // Rst and clk
        clk, rst,
 
        // LSU i/f
        dmmu_en, supv, dmmulsu_vaddr, dmmulsu_lsuop, dmmulsu_stall,
 
        // Except I/F
        dmmuexcept_miss, dmmuexcept_fault,
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
        // DC i/f
        dcdmmu_paddr
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// LSU I/F
//
input                           dmmu_en;
input                           supv;
input   [aw-1:0]         dmmulsu_vaddr;
input   [`LSUOP_WIDTH-1:0]       dmmulsu_lsuop;
output                          dmmulsu_stall;
 
//
// Exception I/F
//
output                          dmmuexcept_miss;
output                          dmmuexcept_fault;
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [aw-1:0]         spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// DC I/F
//
output  [aw-1:0]         dcdmmu_paddr;
 
//
// Internal wires and regs
//
wire                            dtlb_spr_access;
wire    [31:13]                 dtlb_ppn;
wire                            dtlb_hit;
wire                            dtlb_uwe;
wire                            dtlb_ure;
wire                            dtlb_swe;
wire                            dtlb_sre;
wire    [31:0]                   dtlb_dat_o;
 
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-10  v 0
// dtlbwYtrX: ppn 31-10  uwe 9  ure 8  swe 7  sre 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
 
`ifdef OR1200_NO_DMMU
 
//
// Put all outputs in inactive state
//
assign dmmulsu_stall = 1'b0;
assign dmmuexcept_miss = 1'b0;
assign dmmuexcept_fault = 1'b0;
assign spr_dat_o = 32'h00000000;
assign dcdmmu_paddr = dmmulsu_vaddr;
 
`else
 
//
// DTLB SPR access
//
// 0C00 - 0E00  dtlbmr w0-3
// 0C00 - 0C80  dtlbmr w0
// 0C00 - 0C40  dtlbmr w0 [63:0]
//
// 0E00 - 1000  dtlbtr w0-3
// 0E00 - 0E80  dtlbtr w0
// 0E00 - 0E40  dtlbtr w0 [63:0]
//
assign dtlb_spr_access = spr_cs & spr_addr[10];
 
//
// Physical address is either translated virtual address or
// simply equal when DMMU is disabled
//
assign dcdmmu_paddr = dmmu_en ? {dtlb_ppn, dmmulsu_vaddr[12:0]} : dmmulsu_vaddr;
 
//
// Output to SPRS unit
//
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
 
//
// DMMU stall
//
assign dmmulsu_stall = 1'b0;
 
//
// Page fault exception logic
//
assign dmmuexcept_fault = (|dmmulsu_lsuop) && dmmu_en &&
                        (  (!dmmulsu_lsuop[3] & !supv & !dtlb_ure) // Load in user mode not enabled
                        || (!dmmulsu_lsuop[3] & supv & !dtlb_sre) // Load in supv mode not enabled
                        || (dmmulsu_lsuop[3] & !supv & !dtlb_uwe) // Store in user mode not enabled
                        || (dmmulsu_lsuop[3] & supv & !dtlb_swe) ); // Store in supv mode not enabled
 
//
// TLB Miss exception logic
//
assign dmmuexcept_miss = (|dmmulsu_lsuop) && dmmu_en && !dtlb_hit;
 
//
// Instantiation of DTLB
//
dtlb dtlb(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // I/F for translation
        .tlb_en(dmmu_en),
        .vaddr(dmmulsu_vaddr),
        .hit(dtlb_hit),
        .ppn(dtlb_ppn),
        .uwe(dtlb_uwe),
        .ure(dtlb_ure),
        .swe(dtlb_swe),
        .sre(dtlb_sre),
 
        // SPR access
        .spr_cs(dtlb_spr_access),
        .spr_write(spr_write),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_i),
        .spr_dat_o(dtlb_dat_o)
);
 
`endif
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [dmmu.v] - Blame information for rev 1778

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Data MMU top level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of all DMMU blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.5 2001/10/14 13:12:09 lampret`
48			`// MP3 version.`
49			`//`
50			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
51			`// no message`
52			`//`
53			`// Revision 1.1 2001/08/17 08:03:35 lampret`
54			`// * empty log message *`
55			`//`
56			`// Revision 1.2 2001/07/22 03:31:53 lampret`
57			`// Fixed RAM's oen bug. Cache bypass under development.`
58			`//`
59			`// Revision 1.1 2001/07/20 00:46:03 lampret`
60			`// Development version of RTL. Libraries are missing.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "defines.v"
68
69			`//`
70			`// Data MMU`
71			`//`
72
73			`module dmmu(`
74			`// Rst and clk`
75			`clk, rst,`
76
77			`// LSU i/f`
78			`dmmu_en, supv, dmmulsu_vaddr, dmmulsu_lsuop, dmmulsu_stall,`
79
80			`// Except I/F`
81			`dmmuexcept_miss, dmmuexcept_fault,`
82
83			`// SPR access`
84			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
85
86			`// DC i/f`
87			`dcdmmu_paddr`
88			`);`
89
90			parameter dw = `OPERAND_WIDTH;
91			parameter aw = `OPERAND_WIDTH;
92
93			`//`
94			`// I/O`
95			`//`
96
97			`//`
98			`// Clock and reset`
99			`//`
100			`input clk;`
101			`input rst;`
102
103			`//`
104			`// LSU I/F`
105			`//`
106			`input dmmu_en;`
107			`input supv;`
108			`input [aw-1:0] dmmulsu_vaddr;`
109			input [`LSUOP_WIDTH-1:0] dmmulsu_lsuop;
110			`output dmmulsu_stall;`
111
112			`//`
113			`// Exception I/F`
114			`//`
115			`output dmmuexcept_miss;`
116			`output dmmuexcept_fault;`
117
118			`//`
119			`// SPR access`
120			`//`
121			`input spr_cs;`
122			`input spr_write;`
123			`input [aw-1:0] spr_addr;`
124			`input [31:0] spr_dat_i;`
125			`output [31:0] spr_dat_o;`
126
127			`//`
128			`// DC I/F`
129			`//`
130			`output [aw-1:0] dcdmmu_paddr;`
131
132			`//`
133			`// Internal wires and regs`
134			`//`
135			`wire dtlb_spr_access;`
136			`wire [31:13] dtlb_ppn;`
137			`wire dtlb_hit;`
138			`wire dtlb_uwe;`
139			`wire dtlb_ure;`
140			`wire dtlb_swe;`
141			`wire dtlb_sre;`
142			`wire [31:0] dtlb_dat_o;`
143
144			`//`
145			`// Implemented bits inside match and translate registers`
146			`//`
147			`// dtlbwYmrX: vpn 31-10 v 0`
148			`// dtlbwYtrX: ppn 31-10 uwe 9 ure 8 swe 7 sre 6`
149			`//`
150			`// dtlb memory width:`
151			`// 19 bits for ppn`
152			`// 13 bits for vpn`
153			`// 1 bit for valid`
154			`// 4 bits for protection`
155
156			`ifdef OR1200_NO_DMMU
157
158			`//`
159			`// Put all outputs in inactive state`
160			`//`
161			`assign dmmulsu_stall = 1'b0;`
162			`assign dmmuexcept_miss = 1'b0;`
163			`assign dmmuexcept_fault = 1'b0;`
164			`assign spr_dat_o = 32'h00000000;`
165			`assign dcdmmu_paddr = dmmulsu_vaddr;`
166
167			`else
168
169			`//`
170			`// DTLB SPR access`
171			`//`
172			`// 0C00 - 0E00 dtlbmr w0-3`
173			`// 0C00 - 0C80 dtlbmr w0`
174			`// 0C00 - 0C40 dtlbmr w0 [63:0]`
175			`//`
176			`// 0E00 - 1000 dtlbtr w0-3`
177			`// 0E00 - 0E80 dtlbtr w0`
178			`// 0E00 - 0E40 dtlbtr w0 [63:0]`
179			`//`
180			`assign dtlb_spr_access = spr_cs & spr_addr[10];`
181
182			`//`
183			`// Physical address is either translated virtual address or`
184			`// simply equal when DMMU is disabled`
185			`//`
186			`assign dcdmmu_paddr = dmmu_en ? {dtlb_ppn, dmmulsu_vaddr[12:0]} : dmmulsu_vaddr;`
187
188			`//`
189			`// Output to SPRS unit`
190			`//`
191			`assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;`
192
193			`//`
194			`// DMMU stall`
195			`//`
196			`assign dmmulsu_stall = 1'b0;`
197
198			`//`
199			`// Page fault exception logic`
200			`//`
201			`assign dmmuexcept_fault = (\|dmmulsu_lsuop) && dmmu_en &&`
202			`( (!dmmulsu_lsuop[3] & !supv & !dtlb_ure) // Load in user mode not enabled`
203			`\|\| (!dmmulsu_lsuop[3] & supv & !dtlb_sre) // Load in supv mode not enabled`
204			`\|\| (dmmulsu_lsuop[3] & !supv & !dtlb_uwe) // Store in user mode not enabled`
205			`\|\| (dmmulsu_lsuop[3] & supv & !dtlb_swe) ); // Store in supv mode not enabled`
206
207			`//`
208			`// TLB Miss exception logic`
209			`//`
210			`assign dmmuexcept_miss = (\|dmmulsu_lsuop) && dmmu_en && !dtlb_hit;`
211
212			`//`
213			`// Instantiation of DTLB`
214			`//`
215			`dtlb dtlb(`
216			`// Rst and clk`
217			`.clk(clk),`
218			`.rst(rst),`
219
220			`// I/F for translation`
221			`.tlb_en(dmmu_en),`
222			`.vaddr(dmmulsu_vaddr),`
223			`.hit(dtlb_hit),`
224			`.ppn(dtlb_ppn),`
225			`.uwe(dtlb_uwe),`
226			`.ure(dtlb_ure),`
227			`.swe(dtlb_swe),`
228			`.sre(dtlb_sre),`
229
230			`// SPR access`
231			`.spr_cs(dtlb_spr_access),`
232			`.spr_write(spr_write),`
233			`.spr_addr(spr_addr),`
234			`.spr_dat_i(spr_dat_i),`
235			`.spr_dat_o(dtlb_dat_o)`
236			`);`
237
238			`endif
239
240			`endmodule`