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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Debug Unit                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Basic OR1200 debug unit.                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Debug unit
//
 
module du(
        // RISC Internal Interface
        clk, rst,
        dclsu_lsuop, icfetch_op, ex_freeze, branch_op,
        du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
        // External Debug Interface
        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// RISC Internal Interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input   [`LSUOP_WIDTH-1:0]       dclsu_lsuop;    // LSU status
input   [`FETCHOP_WIDTH-1:0]     icfetch_op;     // IFETCH unit status
input                           ex_freeze;      // EX stage freeze
input   [`BRANCHOP_WIDTH-1:0]    branch_op;      // Branch op
output                          du_stall;       // Debug Unit Stall
output  [aw-1:0]         du_addr;        // Debug Unit Address
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
output                          du_read;        // Debug Unit Read Enable
output                          du_write;       // Debug Unit Write Enable
input   [`EXCEPT_WIDTH-1:0]      du_except;      // Exception started
input                           spr_cs;         // SPR Chip Select
input                           spr_write;      // SPR Read/Write
input   [aw-1:0]         spr_addr;       // SPR Address
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
 
//
// External Debug Interface
//
input                           dbg_stall_i;    // External Stall Input
input   [dw-1:0]         dbg_dat_i;      // External Data Input
input   [aw-1:0]         dbg_adr_i;      // External Address Input
input   [2:0]                    dbg_op_i;       // External Operation Select Input
input                           dbg_ewt_i;      // External Watchpoint Trigger Input
output  [3:0]                    dbg_lss_o;      // External Load/Store Unit Status
output  [1:0]                    dbg_is_o;       // External Insn Fetch Status
output  [10:0]                   dbg_wp_o;       // Watchpoints Outputs
output                          dbg_bp_o;       // Breakpoint Output
output  [dw-1:0]         dbg_dat_o;      // External Data Output
 
 
//
// Some connections go directly from the CPU through DU to Debug I/F
//
assign dbg_lss_o = dclsu_lsuop;
assign dbg_is_o = icfetch_op;
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
 
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = (dbg_op_i == `DU_OP_READSPR);
assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
 
`ifdef DU_IMPLEMENTED
 
//
// Debug Mode Register 1 (only ST and BT implemented)
//
`ifdef DU_DMR1
reg     [23:22]                 dmr1;           // DMR1 implemented (ST & BT)
`else
wire    [23:22]                 dmr1;           // DMR1 not implemented
`endif
 
//
// Debug Mode Register 2 (not implemented)
//
`ifdef DU_DMR2
wire    [31:0]                   dmr2;           // DMR not implemented
`endif
 
//
// Debug Stop Register
//
`ifdef DU_DSR
reg     [13:0]                   dsr;            // DSR implemented
`else
wire    [13:0]                   dsr;            // DSR not implemented
`endif
 
//
// Debug Reason Register
//
`ifdef DU_DRR
reg     [13:0]                   drr;            // DRR implemented
reg     [13:0]                   except_unmasked;
`else
wire    [13:0]                   drr;            // DRR not implemented
`endif
 
//
// Internal wires
//
wire    [13:0]                   except_masked;
wire                            dmr1_sel;       // DMR1 select
wire                            dsr_sel;        // DSR select
wire                            drr_sel;        // DRR select
reg                             dbg_bp_r;
`ifdef DU_READREGS
reg     [31:0]                   spr_dat_o;
`endif
 
//
// DU registers address decoder
//
`ifdef DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DMR1));
`endif
`ifdef DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DSR));
`endif
`ifdef DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DRR));
`endif
 
//
// Decode started exception
//
always @(du_except)
        case (du_except)
                4'he: except_unmasked = 14'b10_0000_0000_0000;
                4'hd: except_unmasked = 14'b01_0000_0000_0000;
                4'hc: except_unmasked = 14'b00_1000_0000_0000;
                4'hb: except_unmasked = 14'b00_0100_0000_0000;
                4'ha: except_unmasked = 14'b00_0010_0000_0000;
                4'h9: except_unmasked = 14'b00_0001_0000_0000;
                4'h8: except_unmasked = 14'b00_0000_1000_0000;
                4'h7: except_unmasked = 14'b00_0000_0100_0000;
                4'h6: except_unmasked = 14'b00_0000_0010_0000;
                4'h5: except_unmasked = 14'b00_0000_0001_0000;
                4'h4: except_unmasked = 14'b00_0000_0000_1000;
                4'h3: except_unmasked = 14'b00_0000_0000_0100;
                4'h2: except_unmasked = 14'b00_0000_0000_0010;
                4'h1: except_unmasked = 14'b00_0000_0000_0001;
                default: except_unmasked = 14'b00_0000_0000_0000;
        endcase
 
//
// Get only 'stop' exceptions
//
assign except_masked = dsr & except_unmasked;
 
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
 
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
        if (rst)
// SIMON
//              dbg_bp_r <= #1 1'b1;
                dbg_bp_r <= #1 1'b0;
        else
                dbg_bp_r <= |except_masked
`ifdef DU_DMR1_ST
                        | ~ex_freeze & dmr1[`DU_DMR1_ST]
`endif
`ifdef DU_DMR1_BT
                        | ~ex_freeze & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT]
`endif
                        ;
 
//
// Write to DMR1
//
`ifdef DU_DMR1
always @(posedge clk or posedge rst)
        if (rst)
                dmr1 <= 2'b00;
        else if (dmr1_sel && spr_write)
                dmr1 <= #1 spr_dat_i[23:22];
`else
assign dmr1 = 2'b00;
`endif
 
//
// DMR2 bits tied to zero
//
`ifdef DU_DMR2
assign dmr2 = 32'h0000_0000;
`endif
 
//
// Write to DSR
//
`ifdef DU_DSR
always @(posedge clk or posedge rst)
        if (rst)
                dsr <= 14'b0;
        else if (dsr_sel && spr_write)
                dsr <= #1 spr_dat_i[13:0];
`else
assign dsr = 14'b0;
`endif
 
//
// Write to DRR
//
`ifdef DU_DRR
always @(posedge clk or posedge rst)
        if (rst)
                drr <= 14'b0;
        else if (drr_sel && spr_write)
                drr <= #1 spr_dat_i[13:0];
        else
                drr <= #1 drr | except_masked;
`else
assign drr = 14'b0;
`endif
 
//
// Read DU registers
//
`ifdef DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2)
        case (spr_addr[`SPROFS_BITS])
`ifdef DU_DMR1
                `DU_OFS_DMR1:
                        spr_dat_o = {8'b0, dmr1, 22'b0};
`endif
`ifdef DU_DMR2
                `DU_OFS_DMR2:
                        spr_dat_o = dmr2;
`endif
`ifdef DU_DSR
                `DU_OFS_DSR:
                        spr_dat_o = {18'b0, dsr};
`endif
`ifdef DU_DRR
                `DU_OFS_DRR:
                        spr_dat_o = {18'b0, drr};
`endif
                default:
                        spr_dat_o = 32'h0000_0000;
        endcase
`endif
 
`else
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
 
//
// Read DU registers
//
`ifdef DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef DU_UNUSED_ZERO
`endif
`endif
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	205	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Debug Unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Basic OR1200 debug unit. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	219	lampret	`// Revision 1.6 2001/10/14 13:12:09 lampret`
48			`// MP3 version.`
49	205	lampret	`//`
50	219	lampret	`//`
51	205	lampret
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55			`include "defines.v"
56
57			`//`
58			`// Debug unit`
59			`//`
60
61			`module du(`
62			`// RISC Internal Interface`
63			`clk, rst,`
64	215	lampret	`dclsu_lsuop, icfetch_op, ex_freeze, branch_op,`
65	210	lampret	`du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,`
66	205	lampret	`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
67
68			`// External Debug Interface`
69			`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
70			`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o`
71			`);`
72
73			parameter dw = `OPERAND_WIDTH;
74			parameter aw = `OPERAND_WIDTH;
75
76			`//`
77			`// I/O`
78			`//`
79
80			`//`
81			`// RISC Internal Interface`
82			`//`
83			`input clk; // Clock`
84			`input rst; // Reset`
85	215	lampret	input [`LSUOP_WIDTH-1:0] dclsu_lsuop; // LSU status
86			input [`FETCHOP_WIDTH-1:0] icfetch_op; // IFETCH unit status
87			`input ex_freeze; // EX stage freeze`
88			input [`BRANCHOP_WIDTH-1:0] branch_op; // Branch op
89	205	lampret	`output du_stall; // Debug Unit Stall`
90			`output [aw-1:0] du_addr; // Debug Unit Address`
91			`input [dw-1:0] du_dat_i; // Debug Unit Data In`
92			`output [dw-1:0] du_dat_o; // Debug Unit Data Out`
93			`output du_read; // Debug Unit Read Enable`
94			`output du_write; // Debug Unit Write Enable`
95	210	lampret	input [`EXCEPT_WIDTH-1:0] du_except; // Exception started
96	205	lampret	`input spr_cs; // SPR Chip Select`
97			`input spr_write; // SPR Read/Write`
98			`input [aw-1:0] spr_addr; // SPR Address`
99			`input [dw-1:0] spr_dat_i; // SPR Data Input`
100			`output [dw-1:0] spr_dat_o; // SPR Data Output`
101
102			`//`
103			`// External Debug Interface`
104			`//`
105			`input dbg_stall_i; // External Stall Input`
106			`input [dw-1:0] dbg_dat_i; // External Data Input`
107			`input [aw-1:0] dbg_adr_i; // External Address Input`
108			`input [2:0] dbg_op_i; // External Operation Select Input`
109			`input dbg_ewt_i; // External Watchpoint Trigger Input`
110			`output [3:0] dbg_lss_o; // External Load/Store Unit Status`
111			`output [1:0] dbg_is_o; // External Insn Fetch Status`
112			`output [10:0] dbg_wp_o; // Watchpoints Outputs`
113			`output dbg_bp_o; // Breakpoint Output`
114			`output [dw-1:0] dbg_dat_o; // External Data Output`
115
116	210	lampret
117	205	lampret	`//`
118			`// Some connections go directly from the CPU through DU to Debug I/F`
119			`//`
120			`assign dbg_lss_o = dclsu_lsuop;`
121			`assign dbg_is_o = icfetch_op;`
122	210	lampret	`assign dbg_wp_o = 11'b000_0000_0000;`
123			`assign dbg_dat_o = du_dat_i;`
124	205	lampret
125			`//`
126			`// Some connections go directly from Debug I/F through DU to the CPU`
127			`//`
128			`assign du_stall = dbg_stall_i;`
129	210	lampret	`assign du_addr = dbg_adr_i;`
130			`assign du_dat_o = dbg_dat_i;`
131			assign du_read = (dbg_op_i == `DU_OP_READSPR);
132			assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
133	205	lampret
134			`ifdef DU_IMPLEMENTED
135
136			`//`
137	215	lampret	`// Debug Mode Register 1 (only ST and BT implemented)`
138			`//`
139			`ifdef DU_DMR1
140			`reg [23:22] dmr1; // DMR1 implemented (ST & BT)`
141			`else
142			`wire [23:22] dmr1; // DMR1 not implemented`
143			`endif
144
145			`//`
146			`// Debug Mode Register 2 (not implemented)`
147			`//`
148			`ifdef DU_DMR2
149			`wire [31:0] dmr2; // DMR not implemented`
150			`endif
151
152			`//`
153	210	lampret	`// Debug Stop Register`
154	205	lampret	`//`
155	210	lampret	`ifdef DU_DSR
156			`reg [13:0] dsr; // DSR implemented`
157			`else
158			`wire [13:0] dsr; // DSR not implemented`
159			`endif
160	205	lampret
161			`//`
162	210	lampret	`// Debug Reason Register`
163			`//`
164			`ifdef DU_DRR
165			`reg [13:0] drr; // DRR implemented`
166	215	lampret	`reg [13:0] except_unmasked;`
167	210	lampret	`else
168			`wire [13:0] drr; // DRR not implemented`
169			`endif
170
171			`//`
172	205	lampret	`// Internal wires`
173			`//`
174	210	lampret	`wire [13:0] except_masked;`
175	215	lampret	`wire dmr1_sel; // DMR1 select`
176	210	lampret	`wire dsr_sel; // DSR select`
177	215	lampret	`wire drr_sel; // DRR select`
178			`reg dbg_bp_r;`
179	210	lampret	`ifdef DU_READREGS
180			`reg [31:0] spr_dat_o;`
181			`endif
182	205	lampret
183			`//`
184	210	lampret	`// DU registers address decoder`
185	205	lampret	`//`
186	215	lampret	`ifdef DU_DMR1
187			assign dmr1_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DMR1));
188			`endif
189	210	lampret	`ifdef DU_DSR
190	215	lampret	assign dsr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DSR));
191	205	lampret	`endif
192	210	lampret	`ifdef DU_DRR
193	215	lampret	assign drr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DRR));
194	210	lampret	`endif
195	205	lampret
196			`//`
197	210	lampret	`// Decode started exception`
198	205	lampret	`//`
199	210	lampret	`always @(du_except)`
200			`case (du_except)`
201			`4'he: except_unmasked = 14'b10_0000_0000_0000;`
202			`4'hd: except_unmasked = 14'b01_0000_0000_0000;`
203			`4'hc: except_unmasked = 14'b00_1000_0000_0000;`
204			`4'hb: except_unmasked = 14'b00_0100_0000_0000;`
205			`4'ha: except_unmasked = 14'b00_0010_0000_0000;`
206			`4'h9: except_unmasked = 14'b00_0001_0000_0000;`
207			`4'h8: except_unmasked = 14'b00_0000_1000_0000;`
208			`4'h7: except_unmasked = 14'b00_0000_0100_0000;`
209			`4'h6: except_unmasked = 14'b00_0000_0010_0000;`
210			`4'h5: except_unmasked = 14'b00_0000_0001_0000;`
211			`4'h4: except_unmasked = 14'b00_0000_0000_1000;`
212			`4'h3: except_unmasked = 14'b00_0000_0000_0100;`
213			`4'h2: except_unmasked = 14'b00_0000_0000_0010;`
214			`4'h1: except_unmasked = 14'b00_0000_0000_0001;`
215			`default: except_unmasked = 14'b00_0000_0000_0000;`
216			`endcase`
217	205	lampret
218			`//`
219	210	lampret	`// Get only 'stop' exceptions`
220	205	lampret	`//`
221	210	lampret	`assign except_masked = dsr & except_unmasked;`
222	205	lampret
223			`//`
224	215	lampret	`// dbg_bp_o is registered`
225	205	lampret	`//`
226	215	lampret	`assign dbg_bp_o = dbg_bp_r;`
227	205	lampret
228			`//`
229	215	lampret	`// Breakpoint activation register`
230			`//`
231			`always @(posedge clk or posedge rst)`
232			`if (rst)`
233			`// SIMON`
234			`// dbg_bp_r <= #1 1'b1;`
235			`dbg_bp_r <= #1 1'b0;`
236			`else`
237			`dbg_bp_r <= \|except_masked`
238			`ifdef DU_DMR1_ST
239			\| ~ex_freeze & dmr1[`DU_DMR1_ST]
240			`endif
241			`ifdef DU_DMR1_BT
242			\| ~ex_freeze & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT]
243			`endif
244			`;`
245
246			`//`
247			`// Write to DMR1`
248			`//`
249			`ifdef DU_DMR1
250			`always @(posedge clk or posedge rst)`
251			`if (rst)`
252			`dmr1 <= 2'b00;`
253			`else if (dmr1_sel && spr_write)`
254			`dmr1 <= #1 spr_dat_i[23:22];`
255			`else
256			`assign dmr1 = 2'b00;`
257			`endif
258
259			`//`
260			`// DMR2 bits tied to zero`
261			`//`
262			`ifdef DU_DMR2
263			`assign dmr2 = 32'h0000_0000;`
264			`endif
265
266			`//`
267	210	lampret	`// Write to DSR`
268	205	lampret	`//`
269	210	lampret	`ifdef DU_DSR
270			`always @(posedge clk or posedge rst)`
271			`if (rst)`
272			`dsr <= 14'b0;`
273			`else if (dsr_sel && spr_write)`
274			`dsr <= #1 spr_dat_i[13:0];`
275			`else
276			`assign dsr = 14'b0;`
277			`endif
278	205	lampret
279			`//`
280	210	lampret	`// Write to DRR`
281	205	lampret	`//`
282	210	lampret	`ifdef DU_DRR
283			`always @(posedge clk or posedge rst)`
284			`if (rst)`
285			`drr <= 14'b0;`
286			`else if (drr_sel && spr_write)`
287			`drr <= #1 spr_dat_i[13:0];`
288	215	lampret	`else`
289	210	lampret	`drr <= #1 drr \| except_masked;`
290			`else
291			`assign drr = 14'b0;`
292			`endif
293	205	lampret
294			`//`
295	210	lampret	`// Read DU registers`
296	205	lampret	`//`
297	210	lampret	`ifdef DU_READREGS
298	219	lampret	`always @(spr_addr or dsr or drr or dmr1 or dmr2)`
299	210	lampret	case (spr_addr[`SPROFS_BITS])
300	215	lampret	`ifdef DU_DMR1
301			`DU_OFS_DMR1:
302			`spr_dat_o = {8'b0, dmr1, 22'b0};`
303			`endif
304			`ifdef DU_DMR2
305			`DU_OFS_DMR2:
306			`spr_dat_o = dmr2;`
307			`endif
308	210	lampret	`ifdef DU_DSR
309			`DU_OFS_DSR:
310			`spr_dat_o = {18'b0, dsr};`
311			`endif
312			`ifdef DU_DRR
313			`DU_OFS_DRR:
314			`spr_dat_o = {18'b0, drr};`
315			`endif
316			`default:`
317			`spr_dat_o = 32'h0000_0000;`
318			`endcase`
319			`endif
320	205	lampret
321			`else
322
323			`//`
324			`// When DU is not implemented, drive all outputs as would when DU is disabled`
325			`//`
326			`assign dbg_bp_o = 1'b0;`
327
328			`//`
329	210	lampret	`// Read DU registers`
330	205	lampret	`//`
331			`ifdef DU_READREGS
332	210	lampret	`assign spr_dat_o = 32'h0000_0000;`
333	205	lampret	`ifdef DU_UNUSED_ZERO
334			`endif
335			`endif
336
337			`endif
338
339			`endmodule`

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