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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Freeze logic                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Generates all freezes and stalls inside RISC                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define NO_FREEZE       3'd0
`define FREEZE_BYDC     3'd1
`define FREEZE_BYMULTICYCLE     3'd2
`define WAIT_LSU_TO_FINISH      3'd3
`define WAIT_IC                 3'd4
 
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module frz_logic(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        multicycle, except_flushpipe, lsu_stall, if_stall, dclsu_unstall, branch_stall, force_dslot_fetch, pipeline_freeze
);
 
//
// I/O
//
input                           clk;
input                           rst;
input   [`MULTICYCLE_WIDTH-1:0]  multicycle;
input                           except_flushpipe;
input                           lsu_stall;
input                           if_stall;
input                           dclsu_unstall;
input                           branch_stall;
input                           force_dslot_fetch;
output                          pipeline_freeze;
 
//
// Internal wires and regs
//
reg                             multicycle_freeze;
reg     [1:0]                    state;
reg     [2:0]                    state2;
reg     [2:0]                    multicycle_cnt;
reg                             done_once;
 
//
// Pipeline freeze
//
assign pipeline_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe;
 
//
// Freeze FSM1
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `NO_FREEZE;
        end
        else
                case (state)    // synopsys full_case parallel_case
                `NO_FREEZE :
                        if (lsu_stall) begin
                                state <= #1 `FREEZE_BYDC;
                        end
                `FREEZE_BYDC :
                        if (!lsu_stall) begin
                                state <= #1 `NO_FREEZE;
                        end
        endcase
end
 
//
// Freeze FSM2
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state2 <= #1 `NO_FREEZE;
                multicycle_freeze <= #1 1'b1;
                multicycle_cnt <= #1 3'b0;
                done_once <= #1 1'b0;
        end
        else
                case (state2)   // synopsys full_case parallel_case
                `NO_FREEZE :
                        if (done_once && pipeline_freeze)
                                done_once <= #1 1'b1;
                        else if (multicycle) begin
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
                                done_once <= #1 1'b0;
                        end
                        else
                                multicycle_freeze <= #1 1'b0;
                `FREEZE_BYMULTICYCLE :
                        if (multicycle_cnt) begin
                                multicycle_cnt <= #1 multicycle_cnt - 'd1;
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                        end
                        else if (lsu_stall) begin
                                state2 <= #1 `WAIT_LSU_TO_FINISH;
                                multicycle_freeze <= #1 1'b0;
                        end
                        else if (if_stall) begin
                                state2 <= #1 `NO_FREEZE;
                                done_once <= #1 1'b1;
                                multicycle_freeze <= #1 1'b0;
                        end
                        else begin
                                state2 <= #1 `NO_FREEZE;
                                multicycle_freeze <= #1 1'b0;
                        end
                `WAIT_LSU_TO_FINISH:
                        if (!lsu_stall && !multicycle) begin
                                state2 <= #1 `NO_FREEZE;
                        end
                        else if (!lsu_stall && multicycle) begin
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
                        end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Freeze logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Generates all freezes and stalls inside RISC ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.2 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	168	lampret	`//`
54	161	lampret
55	203	lampret	`// synopsys translate_off`
56	168	lampret	`include "timescale.v"
57	203	lampret	`// synopsys translate_on`
58	168	lampret	`include "defines.v"
59	161	lampret
60			`define NO_FREEZE 3'd0
61			`define FREEZE_BYDC 3'd1
62			`define FREEZE_BYMULTICYCLE 3'd2
63			`define WAIT_LSU_TO_FINISH 3'd3
64			`define WAIT_IC 3'd4
65
66	168	lampret	`//`
67	161	lampret	`// Freeze logic (stalls CPU pipeline, ifetcher etc.)`
68	168	lampret	`//`
69			`module frz_logic(`
70			`// Clock and reset`
71			`clk, rst,`
72	161	lampret
73	168	lampret	`// Internal i/f`
74	203	lampret	`multicycle, except_flushpipe, lsu_stall, if_stall, dclsu_unstall, branch_stall, force_dslot_fetch, pipeline_freeze`
75	168	lampret	`);`
76	161	lampret
77	168	lampret	`//`
78			`// I/O`
79			`//`
80			`input clk;`
81			`input rst;`
82			input [`MULTICYCLE_WIDTH-1:0] multicycle;
83			`input except_flushpipe;`
84			`input lsu_stall;`
85	203	lampret	`input if_stall;`
86			`input dclsu_unstall;`
87	168	lampret	`input branch_stall;`
88	203	lampret	`input force_dslot_fetch;`
89	168	lampret	`output pipeline_freeze;`
90	161	lampret
91	168	lampret	`//`
92			`// Internal wires and regs`
93			`//`
94			`reg multicycle_freeze;`
95			`reg [1:0] state;`
96			`reg [2:0] state2;`
97			`reg [2:0] multicycle_cnt;`
98			`reg done_once;`
99	161	lampret
100	168	lampret	`//`
101			`// Pipeline freeze`
102			`//`
103	203	lampret	`assign pipeline_freeze = (lsu_stall \| (~dclsu_unstall & if_stall) \| multicycle_freeze) & ~except_flushpipe;`
104	161	lampret
105	168	lampret	`//`
106			`// Freeze FSM1`
107			`//`
108	161	lampret	`always @(posedge clk or posedge rst) begin`
109			`if (rst) begin`
110			state <= #1 `NO_FREEZE;
111			`end`
112			`else`
113			`case (state) // synopsys full_case parallel_case`
114			`NO_FREEZE :
115			`if (lsu_stall) begin`
116			state <= #1 `FREEZE_BYDC;
117			`end`
118			`FREEZE_BYDC :
119			`if (!lsu_stall) begin`
120			state <= #1 `NO_FREEZE;
121			`end`
122			`endcase`
123			`end`
124
125	168	lampret	`//`
126			`// Freeze FSM2`
127			`//`
128	161	lampret	`always @(posedge clk or posedge rst) begin`
129			`if (rst) begin`
130			state2 <= #1 `NO_FREEZE;
131			`multicycle_freeze <= #1 1'b1;`
132			`multicycle_cnt <= #1 3'b0;`
133			`done_once <= #1 1'b0;`
134			`end`
135			`else`
136			`case (state2) // synopsys full_case parallel_case`
137			`NO_FREEZE :
138			`if (done_once && pipeline_freeze)`
139			`done_once <= #1 1'b1;`
140			`else if (multicycle) begin`
141			state2 <= #1 `FREEZE_BYMULTICYCLE;
142			`multicycle_freeze <= #1 1'b1;`
143			`multicycle_cnt <= #1 multicycle - 'd1;`
144			`done_once <= #1 1'b0;`
145			`end`
146			`else`
147			`multicycle_freeze <= #1 1'b0;`
148			`FREEZE_BYMULTICYCLE :
149			`if (multicycle_cnt) begin`
150			`multicycle_cnt <= #1 multicycle_cnt - 'd1;`
151			state2 <= #1 `FREEZE_BYMULTICYCLE;
152			`end`
153			`else if (lsu_stall) begin`
154			state2 <= #1 `WAIT_LSU_TO_FINISH;
155			`multicycle_freeze <= #1 1'b0;`
156			`end`
157	203	lampret	`else if (if_stall) begin`
158	161	lampret	state2 <= #1 `NO_FREEZE;
159			`done_once <= #1 1'b1;`
160			`multicycle_freeze <= #1 1'b0;`
161			`end`
162			`else begin`
163			state2 <= #1 `NO_FREEZE;
164			`multicycle_freeze <= #1 1'b0;`
165			`end`
166			`WAIT_LSU_TO_FINISH:
167			`if (!lsu_stall && !multicycle) begin`
168			state2 <= #1 `NO_FREEZE;
169			`end`
170			`else if (!lsu_stall && multicycle) begin`
171			state2 <= #1 `FREEZE_BYMULTICYCLE;
172			`multicycle_freeze <= #1 1'b1;`
173			`multicycle_cnt <= #1 multicycle - 'd1;`
174			`end`
175			`endcase`
176			`end`
177
178			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [frz_logic.v] - Blame information for rev 203