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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Freeze logic                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Generates all freezes and stalls inside RISC                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define NO_FREEZE       3'd0
`define FREEZE_BYDC     3'd1
`define FREEZE_BYMULTICYCLE     3'd2
`define WAIT_LSU_TO_FINISH      3'd3
`define WAIT_IC                 3'd4
 
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module frz_logic(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        multicycle, except_flushpipe, lsu_stall, if_stall, dclsu_unstall, branch_stall, force_dslot_fetch,
        if_freeze, id_freeze, ex_freeze, wb_freeze
);
 
//
// I/O
//
input                           clk;
input                           rst;
input   [`MULTICYCLE_WIDTH-1:0]  multicycle;
input                           except_flushpipe;
input                           lsu_stall;
input                           if_stall;
input                           dclsu_unstall;
input                           branch_stall;
input                           force_dslot_fetch;
output                          if_freeze;
output                          id_freeze;
output                          ex_freeze;
output                          wb_freeze;
 
//
// Internal wires and regs
//
reg                             multicycle_freeze;
reg     [1:0]                    state;
reg     [2:0]                    state2;
reg     [2:0]                    multicycle_cnt;
reg                             done_once;
 
//
// Pipeline freeze
//
assign if_freeze = id_freeze;
assign id_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~except_flushpipe;
assign ex_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe;
assign wb_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe;
 
//
// Freeze FSM1
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `NO_FREEZE;
        end
        else
                case (state)    // synopsys full_case parallel_case
                `NO_FREEZE :
                        if (lsu_stall) begin
                                state <= #1 `FREEZE_BYDC;
                        end
                `FREEZE_BYDC :
                        if (!lsu_stall) begin
                                state <= #1 `NO_FREEZE;
                        end
        endcase
end
 
//
// Freeze FSM2
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state2 <= #1 `NO_FREEZE;
                multicycle_freeze <= #1 1'b1;
                multicycle_cnt <= #1 3'b0;
                done_once <= #1 1'b0;
        end
        else
                case (state2)   // synopsys full_case parallel_case
                `NO_FREEZE :
                        if (done_once && ex_freeze)
                                done_once <= #1 1'b1;
                        else if (multicycle) begin
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
                                done_once <= #1 1'b0;
                        end
                        else
                                multicycle_freeze <= #1 1'b0;
                `FREEZE_BYMULTICYCLE :
                        if (multicycle_cnt) begin
                                multicycle_cnt <= #1 multicycle_cnt - 'd1;
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                        end
                        else if (lsu_stall) begin
                                state2 <= #1 `WAIT_LSU_TO_FINISH;
                                multicycle_freeze <= #1 1'b0;
                        end
                        else if (if_stall) begin
                                state2 <= #1 `NO_FREEZE;
                                done_once <= #1 1'b1;
                                multicycle_freeze <= #1 1'b0;
                        end
                        else begin
                                state2 <= #1 `NO_FREEZE;
                                multicycle_freeze <= #1 1'b0;
                        end
                `WAIT_LSU_TO_FINISH:
                        if (!lsu_stall && !multicycle) begin
                                state2 <= #1 `NO_FREEZE;
                        end
                        else if (!lsu_stall && multicycle) begin
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
                        end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Freeze logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Generates all freezes and stalls inside RISC ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.2 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	168	lampret	`//`
54	161	lampret
55	203	lampret	`// synopsys translate_off`
56	168	lampret	`include "timescale.v"
57	203	lampret	`// synopsys translate_on`
58	168	lampret	`include "defines.v"
59	161	lampret
60			`define NO_FREEZE 3'd0
61			`define FREEZE_BYDC 3'd1
62			`define FREEZE_BYMULTICYCLE 3'd2
63			`define WAIT_LSU_TO_FINISH 3'd3
64			`define WAIT_IC 3'd4
65
66	168	lampret	`//`
67	161	lampret	`// Freeze logic (stalls CPU pipeline, ifetcher etc.)`
68	168	lampret	`//`
69			`module frz_logic(`
70			`// Clock and reset`
71			`clk, rst,`
72	161	lampret
73	168	lampret	`// Internal i/f`
74	205	lampret	`multicycle, except_flushpipe, lsu_stall, if_stall, dclsu_unstall, branch_stall, force_dslot_fetch,`
75			`if_freeze, id_freeze, ex_freeze, wb_freeze`
76	168	lampret	`);`
77	161	lampret
78	168	lampret	`//`
79			`// I/O`
80			`//`
81			`input clk;`
82			`input rst;`
83			input [`MULTICYCLE_WIDTH-1:0] multicycle;
84			`input except_flushpipe;`
85			`input lsu_stall;`
86	203	lampret	`input if_stall;`
87			`input dclsu_unstall;`
88	168	lampret	`input branch_stall;`
89	203	lampret	`input force_dslot_fetch;`
90	205	lampret	`output if_freeze;`
91			`output id_freeze;`
92			`output ex_freeze;`
93			`output wb_freeze;`
94	161	lampret
95	168	lampret	`//`
96			`// Internal wires and regs`
97			`//`
98			`reg multicycle_freeze;`
99			`reg [1:0] state;`
100			`reg [2:0] state2;`
101			`reg [2:0] multicycle_cnt;`
102			`reg done_once;`
103	161	lampret
104	168	lampret	`//`
105			`// Pipeline freeze`
106			`//`
107	205	lampret	`assign if_freeze = id_freeze;`
108			`assign id_freeze = (lsu_stall \| (~dclsu_unstall & if_stall) \| multicycle_freeze \| force_dslot_fetch) & ~except_flushpipe;`
109			`assign ex_freeze = (lsu_stall \| (~dclsu_unstall & if_stall) \| multicycle_freeze) & ~except_flushpipe;`
110			`assign wb_freeze = (lsu_stall \| (~dclsu_unstall & if_stall) \| multicycle_freeze) & ~except_flushpipe;`
111	161	lampret
112	168	lampret	`//`
113			`// Freeze FSM1`
114			`//`
115	161	lampret	`always @(posedge clk or posedge rst) begin`
116			`if (rst) begin`
117			state <= #1 `NO_FREEZE;
118			`end`
119			`else`
120			`case (state) // synopsys full_case parallel_case`
121			`NO_FREEZE :
122			`if (lsu_stall) begin`
123			state <= #1 `FREEZE_BYDC;
124			`end`
125			`FREEZE_BYDC :
126			`if (!lsu_stall) begin`
127			state <= #1 `NO_FREEZE;
128			`end`
129			`endcase`
130			`end`
131
132	168	lampret	`//`
133			`// Freeze FSM2`
134			`//`
135	161	lampret	`always @(posedge clk or posedge rst) begin`
136			`if (rst) begin`
137			state2 <= #1 `NO_FREEZE;
138			`multicycle_freeze <= #1 1'b1;`
139			`multicycle_cnt <= #1 3'b0;`
140			`done_once <= #1 1'b0;`
141			`end`
142			`else`
143			`case (state2) // synopsys full_case parallel_case`
144			`NO_FREEZE :
145	205	lampret	`if (done_once && ex_freeze)`
146	161	lampret	`done_once <= #1 1'b1;`
147			`else if (multicycle) begin`
148			state2 <= #1 `FREEZE_BYMULTICYCLE;
149			`multicycle_freeze <= #1 1'b1;`
150			`multicycle_cnt <= #1 multicycle - 'd1;`
151			`done_once <= #1 1'b0;`
152			`end`
153			`else`
154			`multicycle_freeze <= #1 1'b0;`
155			`FREEZE_BYMULTICYCLE :
156			`if (multicycle_cnt) begin`
157			`multicycle_cnt <= #1 multicycle_cnt - 'd1;`
158			state2 <= #1 `FREEZE_BYMULTICYCLE;
159			`end`
160			`else if (lsu_stall) begin`
161			state2 <= #1 `WAIT_LSU_TO_FINISH;
162			`multicycle_freeze <= #1 1'b0;`
163			`end`
164	203	lampret	`else if (if_stall) begin`
165	161	lampret	state2 <= #1 `NO_FREEZE;
166			`done_once <= #1 1'b1;`
167			`multicycle_freeze <= #1 1'b0;`
168			`end`
169			`else begin`
170			state2 <= #1 `NO_FREEZE;
171			`multicycle_freeze <= #1 1'b0;`
172			`end`
173			`WAIT_LSU_TO_FINISH:
174			`if (!lsu_stall && !multicycle) begin`
175			state2 <= #1 `NO_FREEZE;
176			`end`
177			`else if (!lsu_stall && multicycle) begin`
178			state2 <= #1 `FREEZE_BYMULTICYCLE;
179			`multicycle_freeze <= #1 1'b1;`
180			`multicycle_cnt <= #1 multicycle - 'd1;`
181			`end`
182			`endcase`
183			`end`
184
185			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [frz_logic.v] - Blame information for rev 205