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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Freeze logic                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Generates all freezes and stalls inside RISC                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define NO_FREEZE       3'd0
`define FREEZE_BYDC     3'd1
`define FREEZE_BYMULTICYCLE     3'd2
`define WAIT_LSU_TO_FINISH      3'd3
`define WAIT_IC                 3'd4
 
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module frz_logic(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        multicycle, except_flushpipe, lsu_stall, if_stall,
        dclsu_unstall, branch_stall, du_stall, mac_stall,
        force_dslot_fetch,
        if_freeze, id_freeze, ex_freeze, wb_freeze
);
 
//
// I/O
//
input                           clk;
input                           rst;
input   [`MULTICYCLE_WIDTH-1:0]  multicycle;
input                           except_flushpipe;
input                           lsu_stall;
input                           if_stall;
input                           dclsu_unstall;
input                           branch_stall;
input                           force_dslot_fetch;
input                           du_stall;
input                           mac_stall;
output                          if_freeze;
output                          id_freeze;
output                          ex_freeze;
output                          wb_freeze;
 
//
// Internal wires and regs
//
reg                             multicycle_freeze;
reg     [2:0]                    state2;
reg     [2:0]                    multicycle_cnt;
reg                             done_once;
 
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Frreze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
assign if_freeze = id_freeze;
assign id_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~except_flushpipe | du_stall;
assign ex_freeze = wb_freeze;
assign wb_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe | du_stall | mac_stall;
 
//
// Freeze FSM2
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state2 <= #1 `NO_FREEZE;
                multicycle_freeze <= #1 1'b1;
                multicycle_cnt <= #1 3'b0;
                done_once <= #1 1'b0;
        end
        else
                case (state2)   // synopsys parallel_case
                `NO_FREEZE :
                        if (done_once && ex_freeze)
                                done_once <= #1 1'b1;
                        else if (multicycle) begin
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
                                done_once <= #1 1'b0;
                        end
                        else
                                multicycle_freeze <= #1 1'b0;
                `FREEZE_BYMULTICYCLE :
                        if (multicycle_cnt) begin
                                multicycle_cnt <= #1 multicycle_cnt - 'd1;
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                        end
                        else if (lsu_stall) begin
                                state2 <= #1 `WAIT_LSU_TO_FINISH;
                                multicycle_freeze <= #1 1'b0;
                        end
                        else if (if_stall) begin
                                state2 <= #1 `NO_FREEZE;
                                done_once <= #1 1'b1;
                                multicycle_freeze <= #1 1'b0;
                        end
                        else begin
                                state2 <= #1 `NO_FREEZE;
                                multicycle_freeze <= #1 1'b0;
                        end
                `WAIT_LSU_TO_FINISH:
                        if (!lsu_stall && !(|multicycle)) begin
                                state2 <= #1 `NO_FREEZE;
                        end
                        else if (!lsu_stall & (|multicycle)) begin
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
                        end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	215	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Freeze logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Generates all freezes and stalls inside RISC ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	217	lampret	`// $Log: not supported by cvs2svn $`
47			`// Revision 1.7 2001/10/14 13:12:09 lampret`
48			`// MP3 version.`
49			`//`
50	215	lampret	`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
51			`// no message`
52			`//`
53			`// Revision 1.2 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`// Revision 1.1 2001/07/20 00:46:03 lampret`
57			`// Development version of RTL. Libraries are missing.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "defines.v"
65
66			`define NO_FREEZE 3'd0
67			`define FREEZE_BYDC 3'd1
68			`define FREEZE_BYMULTICYCLE 3'd2
69			`define WAIT_LSU_TO_FINISH 3'd3
70			`define WAIT_IC 3'd4
71
72			`//`
73			`// Freeze logic (stalls CPU pipeline, ifetcher etc.)`
74			`//`
75			`module frz_logic(`
76			`// Clock and reset`
77			`clk, rst,`
78
79			`// Internal i/f`
80			`multicycle, except_flushpipe, lsu_stall, if_stall,`
81			`dclsu_unstall, branch_stall, du_stall, mac_stall,`
82			`force_dslot_fetch,`
83			`if_freeze, id_freeze, ex_freeze, wb_freeze`
84			`);`
85
86			`//`
87			`// I/O`
88			`//`
89			`input clk;`
90			`input rst;`
91			input [`MULTICYCLE_WIDTH-1:0] multicycle;
92			`input except_flushpipe;`
93			`input lsu_stall;`
94			`input if_stall;`
95			`input dclsu_unstall;`
96			`input branch_stall;`
97			`input force_dslot_fetch;`
98			`input du_stall;`
99			`input mac_stall;`
100			`output if_freeze;`
101			`output id_freeze;`
102			`output ex_freeze;`
103			`output wb_freeze;`
104
105			`//`
106			`// Internal wires and regs`
107			`//`
108			`reg multicycle_freeze;`
109			`reg [2:0] state2;`
110			`reg [2:0] multicycle_cnt;`
111			`reg done_once;`
112
113			`//`
114			`// Pipeline freeze`
115			`//`
116			`// Rules how to create freeze signals:`
117			`// 1. Not overwriting pipeline stages:`
118			`// Frreze signals at the beginning of pipeline (such as if_freeze) can be asserted more`
119			`// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never`
120			`// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.`
121			`//`
122			`// 2. Inserting NOPs in the middle of pipeline only if supported:`
123			`// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.`
124			`// This way NOP is asserted from stage ID into EX stage.`
125			`//`
126			`assign if_freeze = id_freeze;`
127			`assign id_freeze = (lsu_stall \| (~dclsu_unstall & if_stall) \| multicycle_freeze \| force_dslot_fetch) & ~except_flushpipe \| du_stall;`
128			`assign ex_freeze = wb_freeze;`
129			`assign wb_freeze = (lsu_stall \| (~dclsu_unstall & if_stall) \| multicycle_freeze) & ~except_flushpipe \| du_stall \| mac_stall;`
130
131			`//`
132			`// Freeze FSM2`
133			`//`
134			`always @(posedge clk or posedge rst) begin`
135			`if (rst) begin`
136			state2 <= #1 `NO_FREEZE;
137			`multicycle_freeze <= #1 1'b1;`
138			`multicycle_cnt <= #1 3'b0;`
139			`done_once <= #1 1'b0;`
140			`end`
141			`else`
142	217	lampret	`case (state2) // synopsys parallel_case`
143	215	lampret	`NO_FREEZE :
144			`if (done_once && ex_freeze)`
145			`done_once <= #1 1'b1;`
146			`else if (multicycle) begin`
147			state2 <= #1 `FREEZE_BYMULTICYCLE;
148			`multicycle_freeze <= #1 1'b1;`
149			`multicycle_cnt <= #1 multicycle - 'd1;`
150			`done_once <= #1 1'b0;`
151			`end`
152			`else`
153			`multicycle_freeze <= #1 1'b0;`
154			`FREEZE_BYMULTICYCLE :
155			`if (multicycle_cnt) begin`
156			`multicycle_cnt <= #1 multicycle_cnt - 'd1;`
157			state2 <= #1 `FREEZE_BYMULTICYCLE;
158			`end`
159			`else if (lsu_stall) begin`
160			state2 <= #1 `WAIT_LSU_TO_FINISH;
161			`multicycle_freeze <= #1 1'b0;`
162			`end`
163			`else if (if_stall) begin`
164			state2 <= #1 `NO_FREEZE;
165			`done_once <= #1 1'b1;`
166			`multicycle_freeze <= #1 1'b0;`
167			`end`
168			`else begin`
169			state2 <= #1 `NO_FREEZE;
170			`multicycle_freeze <= #1 1'b0;`
171			`end`
172			`WAIT_LSU_TO_FINISH:
173			`if (!lsu_stall && !(\|multicycle)) begin`
174			state2 <= #1 `NO_FREEZE;
175			`end`
176			`else if (!lsu_stall & (\|multicycle)) begin`
177			state2 <= #1 `FREEZE_BYMULTICYCLE;
178			`multicycle_freeze <= #1 1'b1;`
179			`multicycle_cnt <= #1 multicycle - 'd1;`
180			`end`
181			`endcase`
182			`end`
183
184			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [frz_logic.v] - Blame information for rev 217