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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Double-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common double-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  double-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module generic_dpram_32x32(
        // Generic synchronous double-port RAM interface
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous double-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
 
//
// Internal wires and registers
//
 
`ifdef ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(1'b1),
        .aa(addr_a),
        .da(32'h00000000),
        .oena(~oe_a),
        .qb(),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(1'b1)
);
 
`else
 
`ifdef AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(),
 
        .ADRA(addr_a),
        .DA(32'h00000000),
        .WEA(1'b0),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(addr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(1'b1),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef XILINX_RAM32X1D
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
xcv_ram32x8d xcv_ram32x8d_0 (
        .DPO(do_a[7:0]),
        .SPO(),
        .A(addr_b),
        .D(di_b[7:0]),
        .DPRA(addr_a),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 1
//
xcv_ram32x8d xcv_ram32x8d_1 (
        .DPO(do_a[15:8]),
        .SPO(),
        .A(addr_b),
        .D(di_b[15:8]),
        .DPRA(addr_a),
        .WCLK(clk_b),
        .WE(we_b)
);
 
 
//
// Block 2
//
xcv_ram32x8d xcv_ram32x8d_2 (
        .DPO(do_a[23:16]),
        .SPO(),
        .A(addr_b),
        .D(di_b[23:16]),
        .DPRA(addr_a),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 3
//
xcv_ram32x8d xcv_ram32x8d_3 (
        .DPO(do_a[31:24]),
        .SPO(),
        .A(addr_b),
        .D(di_b[31:24]),
        .DPRA(addr_a),
        .WCLK(clk_b),
        .WE(we_b)
);
 
`else
 
`ifdef XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
`else
 
//
// Generic double-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg : {dw{1'bz}};
 
//
// RAM read
//
always @(posedge clk_a)
        if (ce_a)
                do_reg <= #1 mem[addr_a];
 
//
// RAM write
//
always @(posedge clk_b)
        if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
`endif  // !XILINX_RAMB4_S16_S16
`endif  // !XILINX_RAM32X1D
`endif  // !VIRAGE_STP
`endif  // !AVANT_ATP
`endif  // !ARTISAN_SDP
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_dpram_32x32.v] - Blame information for rev 220

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Double-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common double-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// double-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35			`//// ////`
36			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
37			`//// ////`
38			`//// This source file may be used and distributed without ////`
39			`//// restriction provided that this copyright statement is not ////`
40			`//// removed from the file and that any derivative work contains ////`
41			`//// the original copyright notice and the associated disclaimer. ////`
42			`//// ////`
43			`//// This source file is free software; you can redistribute it ////`
44			`//// and/or modify it under the terms of the GNU Lesser General ////`
45			`//// Public License as published by the Free Software Foundation; ////`
46			`//// either version 2.1 of the License, or (at your option) any ////`
47			`//// later version. ////`
48			`//// ////`
49			`//// This source is distributed in the hope that it will be ////`
50			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
51			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
52			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
53			`//// details. ////`
54			`//// ////`
55			`//// You should have received a copy of the GNU Lesser General ////`
56			`//// Public License along with this source; if not, download it ////`
57			`//// from http://www.opencores.org/lgpl.shtml ////`
58			`//// ////`
59			`//////////////////////////////////////////////////////////////////////`
60			`//`
61			`// CVS Revision History`
62			`//`
63			`// $Log: not supported by cvs2svn $`
64	220	lampret	`// Revision 1.7 2001/10/21 17:57:16 lampret`
65			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
66			`//`
67	218	lampret	`// Revision 1.6 2001/10/14 13:12:09 lampret`
68			`// MP3 version.`
69			`//`
70			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
71			`// no message`
72			`//`
73			`// Revision 1.1 2001/08/09 13:39:33 lampret`
74			`// Major clean-up.`
75			`//`
76			`// Revision 1.2 2001/07/30 05:38:02 lampret`
77			`// Adding empty directories required by HDL coding guidelines`
78			`//`
79			`//`
80
81			`// synopsys translate_off`
82			`include "timescale.v"
83			`// synopsys translate_on`
84			`include "defines.v"
85
86			`module generic_dpram_32x32(`
87			`// Generic synchronous double-port RAM interface`
88			`clk_a, rst_a, ce_a, oe_a, addr_a, do_a,`
89			`clk_b, rst_b, ce_b, we_b, addr_b, di_b`
90			`);`
91
92			`//`
93			`// Default address and data buses width`
94			`//`
95			`parameter aw = 5;`
96			`parameter dw = 32;`
97
98			`//`
99			`// Generic synchronous double-port RAM interface`
100			`//`
101			`input clk_a; // Clock`
102			`input rst_a; // Reset`
103			`input ce_a; // Chip enable input`
104			`input oe_a; // Output enable input`
105			`input [aw-1:0] addr_a; // address bus inputs`
106			`output [dw-1:0] do_a; // output data bus`
107			`input clk_b; // Clock`
108			`input rst_b; // Reset`
109			`input ce_b; // Chip enable input`
110			`input we_b; // Write enable input`
111			`input [aw-1:0] addr_b; // address bus inputs`
112			`input [dw-1:0] di_b; // input data bus`
113
114			`//`
115			`// Internal wires and registers`
116			`//`
117
118			`ifdef ARTISAN_SDP
119
120			`//`
121			`// Instantiation of ASIC memory:`
122			`//`
123			`// Artisan Synchronous Double-Port RAM (ra2sh)`
124			`//`
125			`ifdef UNUSED
126			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
127			`else
128	220	lampret	`art_hsdp_32x32 artisan_sdp(`
129	218	lampret	`endif
130			`.qa(do_a),`
131			`.clka(clk_a),`
132			`.cena(~ce_a),`
133			`.wena(1'b1),`
134			`.aa(addr_a),`
135			`.da(32'h00000000),`
136			`.oena(~oe_a),`
137			`.qb(),`
138			`.clkb(clk_b),`
139			`.cenb(~ce_b),`
140			`.wenb(~we_b),`
141			`.ab(addr_b),`
142			`.db(di_b),`
143			`.oenb(1'b1)`
144			`);`
145
146			`else
147
148			`ifdef AVANT_ATP
149
150			`//`
151			`// Instantiation of ASIC memory:`
152			`//`
153			`// Avant! Asynchronous Two-Port RAM`
154			`//`
155			`avant_atp avant_atp(`
156			`.web(~we),`
157			`.reb(),`
158			`.oeb(~oe),`
159			`.rcsb(),`
160			`.wcsb(),`
161			`.ra(addr),`
162			`.wa(addr),`
163			`.di(di),`
164			`.do(do)`
165			`);`
166
167			`else
168
169			`ifdef VIRAGE_STP
170
171			`//`
172			`// Instantiation of ASIC memory:`
173			`//`
174			`// Virage Synchronous 2-port R/W RAM`
175			`//`
176			`virage_stp virage_stp(`
177			`.QA(do_a),`
178			`.QB(),`
179
180			`.ADRA(addr_a),`
181			`.DA(32'h00000000),`
182			`.WEA(1'b0),`
183			`.OEA(oe_a),`
184			`.MEA(ce_a),`
185			`.CLKA(clk_a),`
186
187			`.ADRB(addr_b),`
188			`.DB(di_b),`
189			`.WEB(we_b),`
190			`.OEB(1'b1),`
191			`.MEB(ce_b),`
192			`.CLKB(clk_b)`
193			`);`
194
195			`else
196
197			`ifdef XILINX_RAM32X1D
198
199			`//`
200			`// Instantiation of FPGA memory:`
201			`//`
202			`// Virtex/Spartan2`
203			`//`
204
205			`//`
206			`// Block 0`
207			`//`
208			`xcv_ram32x8d xcv_ram32x8d_0 (`
209			`.DPO(do_a[7:0]),`
210			`.SPO(),`
211			`.A(addr_b),`
212			`.D(di_b[7:0]),`
213			`.DPRA(addr_a),`
214			`.WCLK(clk_b),`
215			`.WE(we_b)`
216			`);`
217
218			`//`
219			`// Block 1`
220			`//`
221			`xcv_ram32x8d xcv_ram32x8d_1 (`
222			`.DPO(do_a[15:8]),`
223			`.SPO(),`
224			`.A(addr_b),`
225			`.D(di_b[15:8]),`
226			`.DPRA(addr_a),`
227			`.WCLK(clk_b),`
228			`.WE(we_b)`
229			`);`
230
231
232			`//`
233			`// Block 2`
234			`//`
235			`xcv_ram32x8d xcv_ram32x8d_2 (`
236			`.DPO(do_a[23:16]),`
237			`.SPO(),`
238			`.A(addr_b),`
239			`.D(di_b[23:16]),`
240			`.DPRA(addr_a),`
241			`.WCLK(clk_b),`
242			`.WE(we_b)`
243			`);`
244
245			`//`
246			`// Block 3`
247			`//`
248			`xcv_ram32x8d xcv_ram32x8d_3 (`
249			`.DPO(do_a[31:24]),`
250			`.SPO(),`
251			`.A(addr_b),`
252			`.D(di_b[31:24]),`
253			`.DPRA(addr_a),`
254			`.WCLK(clk_b),`
255			`.WE(we_b)`
256			`);`
257
258			`else
259
260			`ifdef XILINX_RAMB4
261
262			`//`
263			`// Instantiation of FPGA memory:`
264			`//`
265			`// Virtex/Spartan2`
266			`//`
267
268			`//`
269			`// Block 0`
270			`//`
271			`RAMB4_S16_S16 ramb4_s16_0(`
272			`.CLKA(clk_a),`
273			`.RSTA(rst_a),`
274			`.ADDRA({3'b000, addr_a}),`
275			`.DIA(16'h0000),`
276			`.ENA(ce_a),`
277			`.WEA(1'b0),`
278			`.DOA(do_a[15:0]),`
279
280			`.CLKB(clk_b),`
281			`.RSTB(rst_b),`
282			`.ADDRB({3'b000, addr_b}),`
283			`.DIB(di_b[15:0]),`
284			`.ENB(ce_b),`
285			`.WEB(we_b),`
286			`.DOB()`
287			`);`
288
289			`//`
290			`// Block 1`
291			`//`
292			`RAMB4_S16_S16 ramb4_s16_1(`
293			`.CLKA(clk_a),`
294			`.RSTA(rst_a),`
295			`.ADDRA({3'b000, addr_a}),`
296			`.DIA(16'h0000),`
297			`.ENA(ce_a),`
298			`.WEA(1'b0),`
299			`.DOA(do_a[31:16]),`
300
301			`.CLKB(clk_b),`
302			`.RSTB(rst_b),`
303			`.ADDRB({3'b000, addr_b}),`
304			`.DIB(di_b[31:16]),`
305			`.ENB(ce_b),`
306			`.WEB(we_b),`
307			`.DOB()`
308			`);`
309
310			`else
311
312			`//`
313			`// Generic double-port synchronous RAM model`
314			`//`
315
316			`//`
317			`// Generic RAM's registers and wires`
318			`//`
319			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
320			`reg [dw-1:0] do_reg; // RAM data output register`
321
322			`//`
323			`// Data output drivers`
324			`//`
325			`assign do_a = (oe_a) ? do_reg : {dw{1'bz}};`
326
327			`//`
328			`// RAM read`
329			`//`
330			`always @(posedge clk_a)`
331			`if (ce_a)`
332			`do_reg <= #1 mem[addr_a];`
333
334			`//`
335			`// RAM write`
336			`//`
337			`always @(posedge clk_b)`
338			`if (ce_b && we_b)`
339			`mem[addr_b] <= #1 di_b;`
340
341			`endif // !XILINX_RAMB4_S16_S16
342			`endif // !XILINX_RAM32X1D
343			`endif // !VIRAGE_STP
344			`endif // !AVANT_ATP
345			`endif // !ARTISAN_SDP
346
347			`endmodule`