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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs (Altera etc)                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
`include "timescale.v"
 
module generic_spram_2048x32(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 32;
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
art_hdsp_2048x32 #(dw, 2<<aw, aw) artisan_ssp(
        .clk(clk),
        .cen(~ce),
        .wen(~we),
        .a(addr),
        .d(di),
        .oen(~oe),
        .q(do)
);
 
`else
 
`ifdef AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
virtualsilicon_ssp #(2<<aw, aw-1, dw-1) virtualsilicon_ssp(
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we),
        .DO(do[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we),
        .DO(do[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we),
        .DO(do[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we),
        .DO(do[7:6])
);
 
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[9:8]),
        .EN(ce),
        .WE(we),
        .DO(do[9:8])
);
 
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:10]),
        .EN(ce),
        .WE(we),
        .DO(do[11:10])
);
 
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[13:12]),
        .EN(ce),
        .WE(we),
        .DO(do[13:12])
);
 
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:14]),
        .EN(ce),
        .WE(we),
        .DO(do[15:14])
);
 
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[17:16]),
        .EN(ce),
        .WE(we),
        .DO(do[17:16])
);
 
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:18]),
        .EN(ce),
        .WE(we),
        .DO(do[19:18])
);
 
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[21:20]),
        .EN(ce),
        .WE(we),
        .DO(do[21:20])
);
 
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:22]),
        .EN(ce),
        .WE(we),
        .DO(do[23:22])
);
 
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[25:24]),
        .EN(ce),
        .WE(we),
        .DO(do[25:24])
);
 
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:26]),
        .EN(ce),
        .WE(we),
        .DO(do[27:26])
);
 
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[29:28]),
        .EN(ce),
        .WE(we),
        .DO(do[29:28])
);
 
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:30]),
        .EN(ce),
        .WE(we),
        .DO(do[31:30])
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(2<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !XILINX_RAMB4_S16
`endif  // !VIRTUALSILICON_SSP
`endif  // !VIRAGE_SSP
`endif  // !AVANT_ATP
`endif  // !ARTISAN_SSP
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_spram_2048x32.v] - Blame information for rev 168

Line No.	Rev	Author	Line
1	168	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// ////`
27			`//// To Do: ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - fix avant! two-port ram ////`
30			`//// - add additional RAMs (Altera etc) ////`
31			`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65			`// Revision 1.2 2001/07/30 05:38:02 lampret`
66			`// Adding empty directories required by HDL coding guidelines`
67			`//`
68			`//`
69
70			`include "timescale.v"
71
72			`module generic_spram_2048x32(`
73			`// Generic synchronous single-port RAM interface`
74			`clk, rst, ce, we, oe, addr, di, do`
75			`);`
76
77			`//`
78			`// Default address and data buses width`
79			`//`
80			`parameter aw = 11;`
81			`parameter dw = 32;`
82
83			`//`
84			`// Generic synchronous single-port RAM interface`
85			`//`
86			`input clk; // Clock`
87			`input rst; // Reset`
88			`input ce; // Chip enable input`
89			`input we; // Write enable input`
90			`input oe; // Output enable input`
91			`input [aw-1:0] addr; // address bus inputs`
92			`input [dw-1:0] di; // input data bus`
93			`output [dw-1:0] do; // output data bus`
94
95			`//`
96			`// Internal wires and registers`
97			`//`
98
99
100			`ifdef ARTISAN_SSP
101
102			`//`
103			`// Instantiation of ASIC memory:`
104			`//`
105			`// Artisan Synchronous Single-Port RAM (ra1sh)`
106			`//`
107			`art_hdsp_2048x32 #(dw, 2<<aw, aw) artisan_ssp(`
108			`.clk(clk),`
109			`.cen(~ce),`
110			`.wen(~we),`
111			`.a(addr),`
112			`.d(di),`
113			`.oen(~oe),`
114			`.q(do)`
115			`);`
116
117			`else
118
119			`ifdef AVANT_ATP
120
121			`//`
122			`// Instantiation of ASIC memory:`
123			`//`
124			`// Avant! Asynchronous Two-Port RAM`
125			`//`
126			`avant_atp avant_atp(`
127			`.web(~we),`
128			`.reb(),`
129			`.oeb(~oe),`
130			`.rcsb(),`
131			`.wcsb(),`
132			`.ra(addr),`
133			`.wa(addr),`
134			`.di(di),`
135			`.do(do)`
136			`);`
137
138			`else
139
140			`ifdef VIRAGE_SSP
141
142			`//`
143			`// Instantiation of ASIC memory:`
144			`//`
145			`// Virage Synchronous 1-port R/W RAM`
146			`//`
147			`virage_ssp virage_ssp(`
148			`.clk(clk),`
149			`.adr(addr),`
150			`.d(di),`
151			`.we(we),`
152			`.oe(oe),`
153			`.me(ce),`
154			`.q(do)`
155			`);`
156
157			`else
158
159			`ifdef VIRTUALSILICON_SSP
160
161			`//`
162			`// Instantiation of ASIC memory:`
163			`//`
164			`// Virtual Silicon Single-Port Synchronous SRAM`
165			`//`
166			`virtualsilicon_ssp #(2<<aw, aw-1, dw-1) virtualsilicon_ssp(`
167			`.CK(clk),`
168			`.ADR(addr),`
169			`.DI(di),`
170			`.WEN(~we),`
171			`.CEN(~ce),`
172			`.OEN(~oe),`
173			`.DOUT(do)`
174			`);`
175
176			`else
177
178			`ifdef XILINX_RAMB4
179
180			`//`
181			`// Instantiation of FPGA memory:`
182			`//`
183			`// Virtex/Spartan2`
184			`//`
185
186			`//`
187			`// Block 0`
188			`//`
189			`RAMB4_S2 ramb4_s2_0(`
190			`.CLK(clk),`
191			`.RST(rst),`
192			`.ADDR(addr),`
193			`.DI(di[1:0]),`
194			`.EN(ce),`
195			`.WE(we),`
196			`.DO(do[1:0])`
197			`);`
198
199			`//`
200			`// Block 1`
201			`//`
202			`RAMB4_S2 ramb4_s2_1(`
203			`.CLK(clk),`
204			`.RST(rst),`
205			`.ADDR(addr),`
206			`.DI(di[3:2]),`
207			`.EN(ce),`
208			`.WE(we),`
209			`.DO(do[3:2])`
210			`);`
211
212			`//`
213			`// Block 2`
214			`//`
215			`RAMB4_S2 ramb4_s2_2(`
216			`.CLK(clk),`
217			`.RST(rst),`
218			`.ADDR(addr),`
219			`.DI(di[5:4]),`
220			`.EN(ce),`
221			`.WE(we),`
222			`.DO(do[5:4])`
223			`);`
224
225			`//`
226			`// Block 3`
227			`//`
228			`RAMB4_S2 ramb4_s2_3(`
229			`.CLK(clk),`
230			`.RST(rst),`
231			`.ADDR(addr),`
232			`.DI(di[7:6]),`
233			`.EN(ce),`
234			`.WE(we),`
235			`.DO(do[7:6])`
236			`);`
237
238			`//`
239			`// Block 4`
240			`//`
241			`RAMB4_S2 ramb4_s2_4(`
242			`.CLK(clk),`
243			`.RST(rst),`
244			`.ADDR(addr),`
245			`.DI(di[9:8]),`
246			`.EN(ce),`
247			`.WE(we),`
248			`.DO(do[9:8])`
249			`);`
250
251			`//`
252			`// Block 5`
253			`//`
254			`RAMB4_S2 ramb4_s2_5(`
255			`.CLK(clk),`
256			`.RST(rst),`
257			`.ADDR(addr),`
258			`.DI(di[11:10]),`
259			`.EN(ce),`
260			`.WE(we),`
261			`.DO(do[11:10])`
262			`);`
263
264			`//`
265			`// Block 6`
266			`//`
267			`RAMB4_S2 ramb4_s2_6(`
268			`.CLK(clk),`
269			`.RST(rst),`
270			`.ADDR(addr),`
271			`.DI(di[13:12]),`
272			`.EN(ce),`
273			`.WE(we),`
274			`.DO(do[13:12])`
275			`);`
276
277			`//`
278			`// Block 7`
279			`//`
280			`RAMB4_S2 ramb4_s2_7(`
281			`.CLK(clk),`
282			`.RST(rst),`
283			`.ADDR(addr),`
284			`.DI(di[15:14]),`
285			`.EN(ce),`
286			`.WE(we),`
287			`.DO(do[15:14])`
288			`);`
289
290			`//`
291			`// Block 8`
292			`//`
293			`RAMB4_S2 ramb4_s2_8(`
294			`.CLK(clk),`
295			`.RST(rst),`
296			`.ADDR(addr),`
297			`.DI(di[17:16]),`
298			`.EN(ce),`
299			`.WE(we),`
300			`.DO(do[17:16])`
301			`);`
302
303			`//`
304			`// Block 9`
305			`//`
306			`RAMB4_S2 ramb4_s2_9(`
307			`.CLK(clk),`
308			`.RST(rst),`
309			`.ADDR(addr),`
310			`.DI(di[19:18]),`
311			`.EN(ce),`
312			`.WE(we),`
313			`.DO(do[19:18])`
314			`);`
315
316			`//`
317			`// Block 10`
318			`//`
319			`RAMB4_S2 ramb4_s2_10(`
320			`.CLK(clk),`
321			`.RST(rst),`
322			`.ADDR(addr),`
323			`.DI(di[21:20]),`
324			`.EN(ce),`
325			`.WE(we),`
326			`.DO(do[21:20])`
327			`);`
328
329			`//`
330			`// Block 11`
331			`//`
332			`RAMB4_S2 ramb4_s2_11(`
333			`.CLK(clk),`
334			`.RST(rst),`
335			`.ADDR(addr),`
336			`.DI(di[23:22]),`
337			`.EN(ce),`
338			`.WE(we),`
339			`.DO(do[23:22])`
340			`);`
341
342			`//`
343			`// Block 12`
344			`//`
345			`RAMB4_S2 ramb4_s2_12(`
346			`.CLK(clk),`
347			`.RST(rst),`
348			`.ADDR(addr),`
349			`.DI(di[25:24]),`
350			`.EN(ce),`
351			`.WE(we),`
352			`.DO(do[25:24])`
353			`);`
354
355			`//`
356			`// Block 13`
357			`//`
358			`RAMB4_S2 ramb4_s2_13(`
359			`.CLK(clk),`
360			`.RST(rst),`
361			`.ADDR(addr),`
362			`.DI(di[27:26]),`
363			`.EN(ce),`
364			`.WE(we),`
365			`.DO(do[27:26])`
366			`);`
367
368			`//`
369			`// Block 14`
370			`//`
371			`RAMB4_S2 ramb4_s2_14(`
372			`.CLK(clk),`
373			`.RST(rst),`
374			`.ADDR(addr),`
375			`.DI(di[29:28]),`
376			`.EN(ce),`
377			`.WE(we),`
378			`.DO(do[29:28])`
379			`);`
380
381			`//`
382			`// Block 15`
383			`//`
384			`RAMB4_S2 ramb4_s2_15(`
385			`.CLK(clk),`
386			`.RST(rst),`
387			`.ADDR(addr),`
388			`.DI(di[31:30]),`
389			`.EN(ce),`
390			`.WE(we),`
391			`.DO(do[31:30])`
392			`);`
393
394			`else
395
396			`//`
397			`// Generic single-port synchronous RAM model`
398			`//`
399
400			`//`
401			`// Generic RAM's registers and wires`
402			`//`
403			`reg [dw-1:0] mem [(2<<aw)-1:0]; // RAM content`
404			`reg [dw-1:0] do_reg; // RAM data output register`
405
406			`//`
407			`// Data output drivers`
408			`//`
409			`assign do = (oe) ? do_reg : {dw{1'bz}};`
410
411			`//`
412			`// RAM read and write`
413			`//`
414			`always @(posedge clk)`
415			`if (ce && !we)`
416			`do_reg <= #1 mem[addr];`
417			`else if (ce && we)`
418			`mem[addr] <= #1 di;`
419
420			`endif // !XILINX_RAMB4_S16
421			`endif // !VIRTUALSILICON_SSP
422			`endif // !VIRAGE_SSP
423			`endif // !AVANT_ATP
424			`endif // !ARTISAN_SSP
425
426			`endmodule`