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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs (Altera etc)                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module generic_spram_512x20(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
        .clk(clk),
        .cen(~ce),
        .wen(~we),
        .a(addr),
        .d(di),
        .oen(~oe),
        .q(do)
);
 
`else
 
`ifdef AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:0]),
        .EN(ce),
        .WE(we),
        .DO(do[3:0])
);
 
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:4]),
        .EN(ce),
        .WE(we),
        .DO(do[7:4])
);
 
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:8]),
        .EN(ce),
        .WE(we),
        .DO(do[11:8])
);
 
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:12]),
        .EN(ce),
        .WE(we),
        .DO(do[15:12])
);
 
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:16]),
        .EN(ce),
        .WE(we),
        .DO(do[19:16])
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !XILINX_RAMB4_S16
`endif  // !VIRTUALSILICON_SSP
`endif  // !VIRAGE_SSP
`endif  // !AVANT_ATP
`endif  // !ARTISAN_SSP
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [generic_spram_512x20.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// ////`
27			`//// To Do: ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - fix avant! two-port ram ////`
30			`//// - add additional RAMs (Altera etc) ////`
31			`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65			`// Revision 1.5 2001/10/14 13:12:09 lampret`
66			`// MP3 version.`
67			`//`
68			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
69			`// no message`
70			`//`
71			`// Revision 1.1 2001/08/09 13:39:33 lampret`
72			`// Major clean-up.`
73			`//`
74			`// Revision 1.2 2001/07/30 05:38:02 lampret`
75			`// Adding empty directories required by HDL coding guidelines`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "defines.v"
83
84			`module generic_spram_512x20(`
85			`// Generic synchronous single-port RAM interface`
86			`clk, rst, ce, we, oe, addr, di, do`
87			`);`
88
89			`//`
90			`// Default address and data buses width`
91			`//`
92			`parameter aw = 9;`
93			`parameter dw = 20;`
94
95			`//`
96			`// Generic synchronous single-port RAM interface`
97			`//`
98			`input clk; // Clock`
99			`input rst; // Reset`
100			`input ce; // Chip enable input`
101			`input we; // Write enable input`
102			`input oe; // Output enable input`
103			`input [aw-1:0] addr; // address bus inputs`
104			`input [dw-1:0] di; // input data bus`
105			`output [dw-1:0] do; // output data bus`
106
107			`//`
108			`// Internal wires and registers`
109			`//`
110
111
112			`ifdef ARTISAN_SSP
113
114			`//`
115			`// Instantiation of ASIC memory:`
116			`//`
117			`// Artisan Synchronous Single-Port RAM (ra1sh)`
118			`//`
119			`ifdef UNUSED
120			`art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(`
121			`else
122			`art_hssp_512x20 artisan_ssp(`
123			`endif
124			`.clk(clk),`
125			`.cen(~ce),`
126			`.wen(~we),`
127			`.a(addr),`
128			`.d(di),`
129			`.oen(~oe),`
130			`.q(do)`
131			`);`
132
133			`else
134
135			`ifdef AVANT_ATP
136
137			`//`
138			`// Instantiation of ASIC memory:`
139			`//`
140			`// Avant! Asynchronous Two-Port RAM`
141			`//`
142			`avant_atp avant_atp(`
143			`.web(~we),`
144			`.reb(),`
145			`.oeb(~oe),`
146			`.rcsb(),`
147			`.wcsb(),`
148			`.ra(addr),`
149			`.wa(addr),`
150			`.di(di),`
151			`.do(do)`
152			`);`
153
154			`else
155
156			`ifdef VIRAGE_SSP
157
158			`//`
159			`// Instantiation of ASIC memory:`
160			`//`
161			`// Virage Synchronous 1-port R/W RAM`
162			`//`
163			`virage_ssp virage_ssp(`
164			`.clk(clk),`
165			`.adr(addr),`
166			`.d(di),`
167			`.we(we),`
168			`.oe(oe),`
169			`.me(ce),`
170			`.q(do)`
171			`);`
172
173			`else
174
175			`ifdef VIRTUALSILICON_SSP
176
177			`//`
178			`// Instantiation of ASIC memory:`
179			`//`
180			`// Virtual Silicon Single-Port Synchronous SRAM`
181			`//`
182			`virtualsilicon_ssp #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(`
183			`.CK(clk),`
184			`.ADR(addr),`
185			`.DI(di),`
186			`.WEN(~we),`
187			`.CEN(~ce),`
188			`.OEN(~oe),`
189			`.DOUT(do)`
190			`);`
191
192			`else
193
194			`ifdef XILINX_RAMB4
195
196			`//`
197			`// Instantiation of FPGA memory:`
198			`//`
199			`// Virtex/Spartan2`
200			`//`
201
202			`//`
203			`// Block 0`
204			`//`
205			`RAMB4_S4 ramb4_s4_0(`
206			`.CLK(clk),`
207			`.RST(rst),`
208			`.ADDR(addr),`
209			`.DI(di[3:0]),`
210			`.EN(ce),`
211			`.WE(we),`
212			`.DO(do[3:0])`
213			`);`
214
215			`//`
216			`// Block 1`
217			`//`
218			`RAMB4_S4 ramb4_s4_1(`
219			`.CLK(clk),`
220			`.RST(rst),`
221			`.ADDR(addr),`
222			`.DI(di[7:4]),`
223			`.EN(ce),`
224			`.WE(we),`
225			`.DO(do[7:4])`
226			`);`
227
228			`//`
229			`// Block 2`
230			`//`
231			`RAMB4_S4 ramb4_s4_2(`
232			`.CLK(clk),`
233			`.RST(rst),`
234			`.ADDR(addr),`
235			`.DI(di[11:8]),`
236			`.EN(ce),`
237			`.WE(we),`
238			`.DO(do[11:8])`
239			`);`
240
241			`//`
242			`// Block 3`
243			`//`
244			`RAMB4_S4 ramb4_s4_3(`
245			`.CLK(clk),`
246			`.RST(rst),`
247			`.ADDR(addr),`
248			`.DI(di[15:12]),`
249			`.EN(ce),`
250			`.WE(we),`
251			`.DO(do[15:12])`
252			`);`
253
254			`//`
255			`// Block 4`
256			`//`
257			`RAMB4_S4 ramb4_s4_4(`
258			`.CLK(clk),`
259			`.RST(rst),`
260			`.ADDR(addr),`
261			`.DI(di[19:16]),`
262			`.EN(ce),`
263			`.WE(we),`
264			`.DO(do[19:16])`
265			`);`
266
267			`else
268
269			`//`
270			`// Generic single-port synchronous RAM model`
271			`//`
272
273			`//`
274			`// Generic RAM's registers and wires`
275			`//`
276			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
277			`reg [dw-1:0] do_reg; // RAM data output register`
278
279			`//`
280			`// Data output drivers`
281			`//`
282			`assign do = (oe) ? do_reg : {dw{1'bz}};`
283
284			`//`
285			`// RAM read and write`
286			`//`
287			`always @(posedge clk)`
288			`if (ce && !we)`
289			`do_reg <= #1 mem[addr];`
290			`else if (ce && we)`
291			`mem[addr] <= #1 di;`
292
293			`endif // !XILINX_RAMB4_S16
294			`endif // !VIRTUALSILICON_SSP
295			`endif // !VIRAGE_SSP
296			`endif // !AVANT_ATP
297			`endif // !ARTISAN_SSP
298
299			`endmodule`