URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [ic_fsm.v] - Blame information for rev 176

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instruction cache state machine                             ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
`define ICFSM_IDLE      'd0
`define ICFSM_DOLOAD    'd1
`define ICFSM_LREFILL3  'd2
 
//
// Insn cache FSM for cache line of 16 bytes (4x singleword)
//
module ic_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        fetch_op, miss, biudata_valid, start_addr, saved_addr, refill,
        refill_first, refill_prepare, icram_we, biu_read, refill_rest,
        cntrbusy
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           miss;
input                           biudata_valid;
input   [31:0]                   start_addr;
input   [`FETCHOP_WIDTH-1:0]     fetch_op;
output  [31:0]                   saved_addr;
output                          refill;
output                          refill_first;
output                          refill_prepare;
output  [3:0]                    icram_we;
output                          biu_read;
output                          refill_rest;
output                          cntrbusy;
 
//
// Internal wires and regs
//
wire                            icache_off = 1'b0;
reg     [31:0]                   saved_addr;
reg                             refill;
reg     [3:0]                    icram_we;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             refill_first;
reg                             refill_prepare;
reg                             biu_read;
reg                             refill_rest;
reg                             cntrbusy;
 
//
// Generate ICRAM's write enable
//
always @(refill_first or refill or biudata_valid or fetch_op or start_addr) begin
        if (refill_first || !refill)
                case(fetch_op)
                        `FETCHOP_LW : icram_we <= #1 4'b0000 ^ {4{refill_first}};
                        default : icram_we <= #1 4'b0000;
                endcase
        else
                icram_we <= #1 {4{refill & biudata_valid}};
end
 
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                refill <= #1 1'b0;
                state <= #1 3`ICFSM_IDLE;
                biu_read <= #1 1'b0;
                saved_addr <= #1 32'b0;
                refill_first <= #1 1'b0;
                refill_prepare <= #1 1'b0;
                refill_rest <= #1 1'b0;
                cntrbusy <= #1 1'b0;
                cnt <= #1 3'b0;
        end
        else
        case (state)    // synopsys full_case parallel_case
                `ICFSM_IDLE :
                        case(fetch_op)
                                `FETCHOP_LW: begin
                                        $display("%t: IC_FSM Load op %h  start_addr %h", $time, fetch_op, start_addr);
                                        state <= #1 3`ICFSM_DOLOAD;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                default: begin
                                        state <= #1 3`ICFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                        endcase
                `ICFSM_DOLOAD:
                        if (icache_off) begin
//                              $display("%t: IC_FSM ICache off", $time);
                                state <= #1 3`ICFSM_DOLOAD;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                biu_read <= #1 1'b1;
                                if (biudata_valid) begin
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                end
                        end else
                        if (miss) begin
                                $display("%t: IC_FSM Load miss", $time);
                                state <= #1 3`ICFSM_LREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
                                $display("%t: IC_FSM Load hit", $time);
                                state <= #1 3`ICFSM_DOLOAD;
                                saved_addr <= #1 start_addr;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;
                        end
                `ICFSM_LREFILL3 : begin
                        if (biudata_valid && cnt) begin
                                $display("%t: IC_FSM Load refill %d", $time, cnt);
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
                                $display("%t: IC_FSM Load refill end", $time, cnt);
                                state <= #1 3`ICFSM_DOLOAD;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b0;
                                biu_read <= #1 1'b0;
                                cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instruction cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	176	lampret	`// Revision 1.2 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	168	lampret	`//`
54	161	lampret
55	168	lampret	`include "timescale.v"
56			`include "defines.v"
57	161	lampret
58			`define ICFSM_IDLE 'd0
59			`define ICFSM_DOLOAD 'd1
60			`define ICFSM_LREFILL3 'd2
61
62	168	lampret	`//`
63	161	lampret	`// Insn cache FSM for cache line of 16 bytes (4x singleword)`
64	168	lampret	`//`
65			`module ic_fsm(`
66			`// Clock and reset`
67			`clk, rst,`
68
69			`// Internal i/f`
70			`fetch_op, miss, biudata_valid, start_addr, saved_addr, refill,`
71			`refill_first, refill_prepare, icram_we, biu_read, refill_rest,`
72			`cntrbusy`
73			`);`
74	161	lampret
75	168	lampret	`//`
76			`// I/O`
77			`//`
78			`input clk;`
79			`input rst;`
80			`input miss;`
81			`input biudata_valid;`
82			`input [31:0] start_addr;`
83			input [`FETCHOP_WIDTH-1:0] fetch_op;
84			`output [31:0] saved_addr;`
85			`output refill;`
86			`output refill_first;`
87			`output refill_prepare;`
88			`output [3:0] icram_we;`
89			`output biu_read;`
90			`output refill_rest;`
91			`output cntrbusy;`
92	161	lampret
93	168	lampret	`//`
94			`// Internal wires and regs`
95			`//`
96			`wire icache_off = 1'b0;`
97			`reg [31:0] saved_addr;`
98			`reg refill;`
99			`reg [3:0] icram_we;`
100			`reg [2:0] state;`
101			`reg [2:0] cnt;`
102			`reg refill_first;`
103			`reg refill_prepare;`
104			`reg biu_read;`
105			`reg refill_rest;`
106			`reg cntrbusy;`
107	161	lampret
108	168	lampret	`//`
109			`// Generate ICRAM's write enable`
110			`//`
111	161	lampret	`always @(refill_first or refill or biudata_valid or fetch_op or start_addr) begin`
112			`if (refill_first \|\| !refill)`
113			`case(fetch_op)`
114			`FETCHOP_LW : icram_we <= #1 4'b0000 ^ {4{refill_first}};
115			`default : icram_we <= #1 4'b0000;`
116			`endcase`
117			`else`
118			`icram_we <= #1 {4{refill & biudata_valid}};`
119			`end`
120
121	168	lampret	`//`
122			`// Main IC FSM`
123			`//`
124	161	lampret	`always @(posedge clk or posedge rst) begin`
125			`if (rst) begin`
126			`refill <= #1 1'b0;`
127	176	lampret	state <= #1 3`ICFSM_IDLE;
128	161	lampret	`biu_read <= #1 1'b0;`
129			`saved_addr <= #1 32'b0;`
130			`refill_first <= #1 1'b0;`
131			`refill_prepare <= #1 1'b0;`
132			`refill_rest <= #1 1'b0;`
133			`cntrbusy <= #1 1'b0;`
134			`cnt <= #1 3'b0;`
135			`end`
136			`else`
137			`case (state) // synopsys full_case parallel_case`
138			`ICFSM_IDLE :
139			`case(fetch_op)`
140			`FETCHOP_LW: begin
141			`$display("%t: IC_FSM Load op %h start_addr %h", $time, fetch_op, start_addr);`
142			state <= #1 3`ICFSM_DOLOAD;
143			`refill <= #1 1'b0;`
144			`saved_addr <= #1 start_addr;`
145			`refill_first <= #1 1'b0;`
146			`refill_prepare <= #1 1'b1;`
147			`biu_read <= #1 1'b0;`
148			`refill_rest <= #1 1'b0;`
149			`cntrbusy <= #1 1'b0;`
150			`end`
151			`default: begin`
152			state <= #1 3`ICFSM_IDLE;
153			`refill <= #1 1'b0;`
154			`refill_first <= #1 1'b0;`
155			`refill_prepare <= #1 1'b0;`
156			`refill_rest <= #1 1'b0;`
157			`biu_read <= #1 1'b0;`
158			`cntrbusy <= #1 1'b0;`
159			`end`
160			`endcase`
161			`ICFSM_DOLOAD:
162			`if (icache_off) begin`
163			`// $display("%t: IC_FSM ICache off", $time);`
164			state <= #1 3`ICFSM_DOLOAD;
165			`refill <= #1 1'b1;`
166			`refill_first <= #1 1'b1;`
167			`refill_prepare <= #1 1'b0;`
168			`refill_rest <= #1 1'b0;`
169			`biu_read <= #1 1'b1;`
170			`if (biudata_valid) begin`
171			`refill <= #1 1'b0;`
172			`refill_first <= #1 1'b0;`
173			`biu_read <= #1 1'b0;`
174			`saved_addr <= #1 start_addr;`
175			`end`
176			`end else`
177			`if (miss) begin`
178			`$display("%t: IC_FSM Load miss", $time);`
179			state <= #1 3`ICFSM_LREFILL3;
180			`refill <= #1 1'b1;`
181			`refill_first <= #1 1'b1;`
182			`refill_prepare <= #1 1'b0;`
183			`refill_rest <= #1 1'b0;`
184			`cnt <= #1 3'd3;`
185			`biu_read <= #1 1'b1;`
186			`end`
187			`else begin`
188			`$display("%t: IC_FSM Load hit", $time);`
189			state <= #1 3`ICFSM_DOLOAD;
190			`saved_addr <= #1 start_addr;`
191			`refill <= #1 1'b0;`
192			`refill_first <= #1 1'b0;`
193			`refill_prepare <= #1 1'b0;`
194			`refill_rest <= #1 1'b0;`
195			`cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;`
196			`end`
197			`ICFSM_LREFILL3 : begin
198			`if (biudata_valid && cnt) begin`
199			`$display("%t: IC_FSM Load refill %d", $time, cnt);`
200			`cnt <= #1 cnt - 'd1;`
201			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
202			`refill_first <= #1 1'b0;`
203			`end`
204			`else if (biudata_valid) begin`
205			`$display("%t: IC_FSM Load refill end", $time, cnt);`
206			state <= #1 3`ICFSM_DOLOAD;
207			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
208			`refill <= #1 1'b1;`
209			`refill_first <= #1 1'b0;`
210			`biu_read <= #1 1'b0;`
211			`cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0;`
212			`end`
213			`refill_rest <= #1 ~refill_first & refill;`
214			`end`
215			`endcase`
216			`end`
217
218			`endmodule`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [ic_fsm.v] - Blame information for rev 176