Subversion Repositories or1k

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's IC RAMs                                            ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Instantiation of Instruction cache data rams                ////

////                                                              ////

////  To Do:                                                      ////

////   - make it smaller and faster                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`include "general.h"

//`define XCV_IC

module ic_ram(clk, addr, we, datain, dataout, tp4w, tpdw);

parameter dw = `OPERAND_WIDTH;

parameter aw = `ICINDX;

input [dw-1:0] datain;

output [dw-1:0] dataout;

input [aw-1:0] addr;

input [3:0] we;

input clk;

input [`TP4W_WIDTH-1:0] tp4w;

input [31:0] tpdw;

`ifdef XCV_IC

xcv_2048x16 ic_ram0 (

        .DO(dataout[15:0]),

        .ADDR(addr),

        .DI(datain[15:0]),

        .EN(1'b1),

        .CLK(clk),

        .WE(we[0]),

        .RST(1'b0)

);

xcv_2048x16 ic_ram1 (

        .DO(dataout[31:16]),

        .ADDR(addr),

        .DI(datain[31:16]),

        .EN(1'b1),

        .CLK(clk),

        .WE(we[0]),

        .RST(1'b0)

);

`else

art_hdsp_2048x32 ic_ram0(

        .q(dataout),

        .clk(clk),

        .cen(1'b0),

        .wen(~we[0]),

        .a(addr),

        .d(datain)

);

`endif

endmodule