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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of Instruction cache data rams                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "general.h"
 
//`define XCV_IC
 
module ic_ram(clk, addr, we, datain, dataout, tp4w, tpdw);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `ICINDX;
 
input [dw-1:0] datain;
output [dw-1:0] dataout;
 
input [aw-1:0] addr;
input [3:0] we;
 
input clk;
 
input [`TP4W_WIDTH-1:0] tp4w;
input [31:0] tpdw;
 
`ifdef XCV_IC
xcv_2048x16 ic_ram0 (
        .DO(dataout[15:0]),
        .ADDR(addr),
        .DI(datain[15:0]),
        .EN(1'b1),
        .CLK(clk),
        .WE(we[0]),
        .RST(1'b0)
);
 
xcv_2048x16 ic_ram1 (
        .DO(dataout[31:16]),
        .ADDR(addr),
        .DI(datain[31:16]),
        .EN(1'b1),
        .CLK(clk),
        .WE(we[0]),
        .RST(1'b0)
);
 
`else
art_hdsp_2048x32 ic_ram0(
        .q(dataout),
        .clk(clk),
        .cen(1'b0),
        .oen(1'b0),
        .wen(~we[0]),
        .a(addr),
        .d(datain)
);
`endif
 
endmodule
 

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of Instruction cache data rams ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	166	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
48			`// Development version of RTL. Libraries are missing.`
49	161	lampret	`//`
50	166	lampret	`//`
51	161	lampret
52			`include "general.h"
53
54			//`define XCV_IC
55
56			`module ic_ram(clk, addr, we, datain, dataout, tp4w, tpdw);`
57
58			parameter dw = `OPERAND_WIDTH;
59			parameter aw = `ICINDX;
60
61			`input [dw-1:0] datain;`
62			`output [dw-1:0] dataout;`
63
64			`input [aw-1:0] addr;`
65			`input [3:0] we;`
66
67			`input clk;`
68
69			input [`TP4W_WIDTH-1:0] tp4w;
70			`input [31:0] tpdw;`
71
72			`ifdef XCV_IC
73			`xcv_2048x16 ic_ram0 (`
74			`.DO(dataout[15:0]),`
75			`.ADDR(addr),`
76			`.DI(datain[15:0]),`
77			`.EN(1'b1),`
78			`.CLK(clk),`
79			`.WE(we[0]),`
80			`.RST(1'b0)`
81			`);`
82
83			`xcv_2048x16 ic_ram1 (`
84			`.DO(dataout[31:16]),`
85			`.ADDR(addr),`
86			`.DI(datain[31:16]),`
87			`.EN(1'b1),`
88			`.CLK(clk),`
89			`.WE(we[0]),`
90			`.RST(1'b0)`
91			`);`
92
93			`else
94			`art_hdsp_2048x32 ic_ram0(`
95			`.q(dataout),`
96			`.clk(clk),`
97			`.cen(1'b0),`
98	166	lampret	`.oen(1'b0),`
99	161	lampret	`.wen(~we[0]),`
100			`.a(addr),`
101			`.d(datain)`
102			`);`
103			`endif
104
105			`endmodule`
106

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [ic_ram.v] - Blame information for rev 166