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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction decode                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Majority of instruction decoding is performed here.         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "timescale.v"
`include "defines.v"
 
module id(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        pipeline_freeze, except_flushpipe, if_insn, branch_op,
        rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
        wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
        multicycle, branch_stall, spr_addrimm, wbforw_valid, sig_syscall
);
 
//
// I/O
//
input                                   clk;
input                                   rst;
input                                   pipeline_freeze;
input                                   except_flushpipe;
input   [31:0]                           if_insn;
output  [`BRANCHOP_WIDTH-1:0]            branch_op;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addra;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrb;
output  [`ALUOP_WIDTH-1:0]               alu_op;
output  [`SHROTOP_WIDTH-1:0]             shrot_op;
output  [`RFWBOP_WIDTH-1:0]              rfwb_op;
output  [31:0]                           wb_insn;
output  [31:0]                           simm;
output  [31:2]                          branch_addrofs;
output  [31:0]                           lsu_addrofs;
output  [`SEL_WIDTH-1:0]         sel_a;
output  [`SEL_WIDTH-1:0]         sel_b;
output  [`LSUOP_WIDTH-1:0]               lsu_op;
output  [`COMPOP_WIDTH-1:0]              comp_op;
output  [`MULTICYCLE_WIDTH-1:0]          multicycle;
output                                  branch_stall;
output  [15:0]                           spr_addrimm;
input                                   wbforw_valid;
output                                  sig_syscall;
 
//
// Internal wires and regs
//
reg     [`BRANCHOP_WIDTH-1:0]            pre_branch_op;
reg     [`BRANCHOP_WIDTH-1:0]            branch_op;
reg     [`ALUOP_WIDTH-1:0]               alu_op;
reg     [`SHROTOP_WIDTH-1:0]             shrot_op;
reg     [31:0]                           id_insn;
reg     [31:0]                           ex_insn;
reg     [31:0]                           wb_insn;
reg     [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
reg     [`REGFILE_ADDR_WIDTH-1:0]        wb_rfaddrw;
reg     [`RFWBOP_WIDTH-1:0]              rfwb_op;
reg     [31:0]                           lsu_addrofs;
reg     [`SEL_WIDTH-1:0]         sel_a;
reg     [`SEL_WIDTH-1:0]         sel_b;
reg                                     sel_imm;
reg     [`LSUOP_WIDTH-1:0]               lsu_op;
reg     [`COMPOP_WIDTH-1:0]              comp_op;
reg     [`MULTICYCLE_WIDTH-1:0]          multicycle;
reg                                     imm_signextend;
reg     [15:0]                           spr_addrimm;
reg                                     sig_syscall;
wire                                    rst_or_except_flushpipe;
 
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
 
//
// Sign/Zero extension of immediates
//
assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
 
//
// Sign extension of branch offset
//
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
 
//
// Assert branch_stall if pre_branch_op is a branch operation
//
assign branch_stall = pre_branch_op ? 1'b1 : 1'b0;
 
//
// Async reset for most of pipeline flops
//
assign rst_or_except_flushpipe = rst | except_flushpipe;
 
//
// Generation of sel_a
//
always @(rf_addrw or wb_insn or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
                sel_a <= #1 `SEL_EX_FORW;
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
                sel_a <= #1 `SEL_WB_FORW;
        else
                sel_a <= #1 `SEL_RF;
 
//
// Generation of sel_b
//
always @(rf_addrw or wb_insn or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if (sel_imm)
                sel_b <= #1 `SEL_IMM;
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
                sel_b <= #1 `SEL_EX_FORW;
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
                sel_b <= #1 `SEL_WB_FORW;
        else
                sel_b <= #1 `SEL_RF;
 
//
// Decode of spr_addrimm
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                spr_addrimm <= #1 16'h0000;
        else if (!pipeline_freeze) begin
                case (id_insn[31:26])   // synopsys full_case parallel_case
                        // l.mtspr
                        `OR32_MTSPR:
                                spr_addrimm <= #1 id_insn[15:0];
                        // l.mfspr
                        default:
                                spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
                endcase
        end
end
 
//
// Decode of multicycle
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
    // l.lwz
    `OR32_LWZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lbz
    `OR32_LBZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lbs
    `OR32_LBS:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lhz
    `OR32_LHZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lhs
    `OR32_LHS:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sw
    `OR32_SW:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sb
    `OR32_SB:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sh
    `OR32_SH:
      multicycle <= #1 `TWO_CYCLES;
 
    // ALU instructions except the one with immediate
    `OR32_ALU:
      multicycle <= #1 id_insn[`ALUMCYC_POS];
 
    // Single cycle instructions
    default: begin
      multicycle <= #1 `ONE_CYCLE;
    end
 
  endcase
 
end
 
//
// Decode of imm_signextend
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
        // l.addi
        `OR32_ADDI:
                imm_signextend <= #1 `on;
 
        // l.addic
        `OR32_ADDIC:
                imm_signextend <= #1 `on;
 
        // l.xori
        `OR32_XORI:
                imm_signextend <= #1 `on;
 
        // l.muli
        `OR32_MULI:
                imm_signextend <= #1 `on;
 
        // l.maci
        `OR32_MACI:
                imm_signextend <= #1 `on;
 
        // SFXX insns with immediate
        `OR32_SFXXI:
                imm_signextend <= #1 `on;
 
        // Instructions with no or zero extended immediate
        default: begin
                imm_signextend <= #1 `off;
        end
 
endcase
 
end
 
//
// LSU addr offset
//
always @(lsu_op or ex_insn) begin
        lsu_addrofs[10:0] <= #1 ex_insn[10:0];
        case(lsu_op)    // synopsys parallel_case full_case
                `LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
                        lsu_addrofs[31:11] <= #1 {{16{ex_insn[25]}}, ex_insn[25:21]};
                default :
                        lsu_addrofs[31:11] <= #1 {{16{ex_insn[15]}}, ex_insn[15:11]};
        endcase
end
 
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
        if (rst)
                rf_addrw <= #1 5'd0;
        else if (!pipeline_freeze)
                case (pre_branch_op)    // synopsys parallel_case full_case
                        `BRANCHOP_JR, `BRANCHOP_BAL:
                                rf_addrw <= #1 5'd09;   // link register r9
                        default:
                                rf_addrw <= #1 id_insn[25:21];
                endcase
end
 
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
        if (rst)
                wb_rfaddrw <= #1 5'd0;
        else if (!pipeline_freeze)
                wb_rfaddrw <= #1 rf_addrw;
end
 
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_insn[31:26] <= #1 `OR32_NOP;
                id_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                id_insn <= #1 if_insn;
                $display("%t: id_insn <= %h", $time, if_insn);
        end
end
 
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_insn[31:26] <= #1 `OR32_NOP;
                ex_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                ex_insn <= #1 id_insn;
                $display("%t: ex_insn <= %h", $time, id_insn);
        end
end
 
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_insn[31:26] <= #1 `OR32_NOP;
                wb_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                wb_insn <= #1 ex_insn;
// synopsys translate_off
                #3;
                if ((wb_insn != 32'h1500ffff) && (wb_insn != 32'h14000000))
                        display_arch_state;
                if (ex_insn == 32'h200000cb)  // small hack to stop simulation (l.sys 203)
                        caught_sys203;
// synopsys translate_on
        end
end
 
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sel_imm <= #1 1'b0;
        else if (!pipeline_freeze) begin
          case (if_insn[31:26])         // synopsys full_case parallel_case
 
            // j.jalr
            `OR32_JALR:
              sel_imm <= #1 `off;
 
            // l.jr
            `OR32_JR:
              sel_imm <= #1 `off;
 
            // l.rfe
            `OR32_RFE:
              sel_imm <= #1 `off;
 
            // l.mfspr
            `OR32_MFSPR:
              sel_imm <= #1 `off;
 
            // l.mtspr
            `OR32_MTSPR:
              sel_imm <= #1 `off;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              sel_imm <= #1 `off;
 
            // l.sw
            `OR32_SW:
              sel_imm <= #1 `off;
 
            // l.sb
            `OR32_SB:
              sel_imm <= #1 `off;
 
            // l.sh
            `OR32_SH:
              sel_imm <= #1 `off;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              sel_imm <= #1 `off;
 
            // SFXX instructions
            `OR32_SFXX:
              sel_imm <= #1 `off;
 
            // l.nop
            `OR32_NOP:
              sel_imm <= #1 `off;
 
            // All instructions with immediates
            default: begin
              sel_imm <= #1 `on;
            end
 
          endcase
 
        end
end
 
 
//
// Decode of alu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                alu_op <= #1 `ALUOP_NOP;
        else if (!pipeline_freeze) begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.j
            `OR32_J:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jal
            `OR32_JAL:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jalr
            `OR32_JALR:
              alu_op <= #1 `ALUOP_OR;
 
            // l.jr
            `OR32_JR:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bnf
            `OR32_BNF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bf
            `OR32_BF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.rfe
            `OR32_RFE:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.movhi
            `OR32_MOVHI:
              alu_op <= #1 `ALUOP_MOVHI;
 
            // l.mfspr
            `OR32_MFSPR:
              alu_op <= #1 `ALUOP_MFSR;
 
            // l.mtspr
            `OR32_MTSPR:
              alu_op <= #1 `ALUOP_MTSR;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.lwz
            `OR32_LWZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbz
            `OR32_LBZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbs
            `OR32_LBS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhz
            `OR32_LHZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhs
            `OR32_LHS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addi
            `OR32_ADDI:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addic
            `OR32_ADDIC:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.andi
            `OR32_ANDI:
              alu_op <= #1 `ALUOP_AND;
 
            // l.ori
            `OR32_ORI:
              alu_op <= #1 `ALUOP_OR;
 
            // l.xori
            `OR32_XORI:
              alu_op <= #1 `ALUOP_XOR;
 
            // l.muli
            `OR32_MULI:
              alu_op <= #1 `ALUOP_MUL;
 
            // l.maci
            `OR32_MACI:
              alu_op <= #1 `ALUOP_MAC;
 
            // Shift and rotate insns with immediate
            `OR32_SH_ROTI:
              alu_op <= #1 `ALUOP_SHROT;
 
            // SFXX insns with immediate
            `OR32_SFXXI:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.sw
            `OR32_SW:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sb
            `OR32_SB:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sh
            `OR32_SH:
              alu_op <= #1 `ALUOP_ADD;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              alu_op <= #1 id_insn[3:0];
 
            // SFXX instructions
            `OR32_SFXX:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.nop
            `OR32_NOP:
              alu_op <= #1 `ALUOP_NOP;
 
            // Illegal and OR1200 unsupported instructions
            default: begin
              alu_op <= #1 `ALUOP_NOP;
              $display("%t: Illegal insn.... insn %h", $time, id_insn);
            end
 
          endcase
 
        end
end
 
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!pipeline_freeze) begin
                shrot_op <= #1 id_insn[`SHROTOP_POS];
        end
end
 
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!pipeline_freeze) begin
                case (id_insn[31:26])           // synopsys full_case parallel_case
 
                  // j.jal
                  `OR32_JAL:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // j.jalr
                  `OR32_JALR:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // l.movhi
                  `OR32_MOVHI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.mfspr
                  `OR32_MFSPR:
                    rfwb_op <= #1 `RFWBOP_SPRS;
 
                  // l.lwz
                  `OR32_LWZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbz
                  `OR32_LBZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbs
                  `OR32_LBS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhz
                  `OR32_LHZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhs
                  `OR32_LHS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.addi
                  `OR32_ADDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.addic
                  `OR32_ADDIC:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.andi
                  `OR32_ANDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.ori
                  `OR32_ORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.xori
                  `OR32_XORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.muli
                  `OR32_MULI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.maci
                  `OR32_MACI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Shift and rotate insns with immediate
                  `OR32_SH_ROTI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // ALU instructions except the one with immediate
                  `OR32_ALU:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Instructions w/o register-file write-back
                  default: begin
                    rfwb_op <= #1 `RFWBOP_NOP;
                  end
 
                endcase
        end
end
 
//
// Decode of pre_branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                pre_branch_op <= #1 `BRANCHOP_NOP;
        else if (!pipeline_freeze) begin
                case (if_insn[31:26])           // synopsys full_case parallel_case
 
                  // l.j
                  `OR32_J:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jal
                  `OR32_JAL:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jalr
                  `OR32_JALR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.jr
                  `OR32_JR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.bnf
                  `OR32_BNF:
                    pre_branch_op <= #1 `BRANCHOP_BNF;
 
                  // l.bf
                  `OR32_BF:
                    pre_branch_op <= #1 `BRANCHOP_BF;
 
                  // l.rfe
                  `OR32_RFE:
                    pre_branch_op <= #1 `BRANCHOP_RFE;
 
                  // Non branch instructions
                  default: begin
                    pre_branch_op <= #1 `BRANCHOP_NOP;
                  end
                endcase
        end
end
 
//
// Generation of branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!pipeline_freeze) begin
                branch_op <= #1 pre_branch_op;
        end
end
 
//
// Decode of lsu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!pipeline_freeze)  begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.lwz
            `OR32_LWZ:
              lsu_op <= #1 `LSUOP_LWZ;
 
            // l.lbz
            `OR32_LBZ:
              lsu_op <= #1 `LSUOP_LBZ;
 
            // l.lbs
            `OR32_LBS:
              lsu_op <= #1 `LSUOP_LBS;
 
            // l.lhz
            `OR32_LHZ:
              lsu_op <= #1 `LSUOP_LHZ;
 
            // l.lhs
            `OR32_LHS:
              lsu_op <= #1 `LSUOP_LHS;
 
            // l.sw
            `OR32_SW:
              lsu_op <= #1 `LSUOP_SW;
 
            // l.sb
            `OR32_SB:
              lsu_op <= #1 `LSUOP_SB;
 
            // l.sh
            `OR32_SH:
              lsu_op <= #1 `LSUOP_SH;
 
            // Non load/store instructions
            default: begin
              lsu_op <= #1 `LSUOP_NOP;
            end
          endcase
        end
end
 
//
// Decode of comp_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                comp_op <= #1 4'd0;
        else if (!pipeline_freeze) begin
                comp_op <= #1 id_insn[24:21];
        end
end
 
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_syscall <= #1 1'b0;
        else if (!pipeline_freeze) begin
// synopsys translate_off
                if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
                        $display("Generating sig_syscall");
// synopsys translate_on
                sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00});
        end
end
 
endmodule

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Line No.	Rev	Author	Line
1	168	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction decode ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Majority of instruction decoding is performed here. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`include "timescale.v"
50			`include "defines.v"
51
52			`module id(`
53			`// Clock and reset`
54			`clk, rst,`
55
56			`// Internal i/f`
57			`pipeline_freeze, except_flushpipe, if_insn, branch_op,`
58			`rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,`
59			`wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,`
60			`multicycle, branch_stall, spr_addrimm, wbforw_valid, sig_syscall`
61			`);`
62
63			`//`
64			`// I/O`
65			`//`
66			`input clk;`
67			`input rst;`
68			`input pipeline_freeze;`
69			`input except_flushpipe;`
70			`input [31:0] if_insn;`
71			output [`BRANCHOP_WIDTH-1:0] branch_op;
72			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
73			output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
74			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrb;
75			output [`ALUOP_WIDTH-1:0] alu_op;
76			output [`SHROTOP_WIDTH-1:0] shrot_op;
77			output [`RFWBOP_WIDTH-1:0] rfwb_op;
78			`output [31:0] wb_insn;`
79			`output [31:0] simm;`
80			`output [31:2] branch_addrofs;`
81			`output [31:0] lsu_addrofs;`
82			output [`SEL_WIDTH-1:0] sel_a;
83			output [`SEL_WIDTH-1:0] sel_b;
84			output [`LSUOP_WIDTH-1:0] lsu_op;
85			output [`COMPOP_WIDTH-1:0] comp_op;
86			output [`MULTICYCLE_WIDTH-1:0] multicycle;
87			`output branch_stall;`
88			`output [15:0] spr_addrimm;`
89			`input wbforw_valid;`
90			`output sig_syscall;`
91
92			`//`
93			`// Internal wires and regs`
94			`//`
95			reg [`BRANCHOP_WIDTH-1:0] pre_branch_op;
96			reg [`BRANCHOP_WIDTH-1:0] branch_op;
97			reg [`ALUOP_WIDTH-1:0] alu_op;
98			reg [`SHROTOP_WIDTH-1:0] shrot_op;
99			`reg [31:0] id_insn;`
100			`reg [31:0] ex_insn;`
101			`reg [31:0] wb_insn;`
102			reg [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
103			reg [`REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
104			reg [`RFWBOP_WIDTH-1:0] rfwb_op;
105			`reg [31:0] lsu_addrofs;`
106			reg [`SEL_WIDTH-1:0] sel_a;
107			reg [`SEL_WIDTH-1:0] sel_b;
108			`reg sel_imm;`
109			reg [`LSUOP_WIDTH-1:0] lsu_op;
110			reg [`COMPOP_WIDTH-1:0] comp_op;
111			reg [`MULTICYCLE_WIDTH-1:0] multicycle;
112			`reg imm_signextend;`
113			`reg [15:0] spr_addrimm;`
114			`reg sig_syscall;`
115			`wire rst_or_except_flushpipe;`
116
117			`//`
118			`// Register file read addresses`
119			`//`
120			`assign rf_addra = if_insn[20:16];`
121			`assign rf_addrb = if_insn[15:11];`
122
123			`//`
124			`// Sign/Zero extension of immediates`
125			`//`
126			assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
127
128			`//`
129			`// Sign extension of branch offset`
130			`//`
131			`assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};`
132
133			`//`
134			`// Assert branch_stall if pre_branch_op is a branch operation`
135			`//`
136			`assign branch_stall = pre_branch_op ? 1'b1 : 1'b0;`
137
138			`//`
139			`// Async reset for most of pipeline flops`
140			`//`
141			`assign rst_or_except_flushpipe = rst \| except_flushpipe;`
142
143			`//`
144			`// Generation of sel_a`
145			`//`
146			`always @(rf_addrw or wb_insn or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
147			`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`
148			sel_a <= #1 `SEL_EX_FORW;
149			`else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)`
150			sel_a <= #1 `SEL_WB_FORW;
151			`else`
152			sel_a <= #1 `SEL_RF;
153
154			`//`
155			`// Generation of sel_b`
156			`//`
157			`always @(rf_addrw or wb_insn or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
158			`if (sel_imm)`
159			sel_b <= #1 `SEL_IMM;
160			`else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])`
161			sel_b <= #1 `SEL_EX_FORW;
162			`else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)`
163			sel_b <= #1 `SEL_WB_FORW;
164			`else`
165			sel_b <= #1 `SEL_RF;
166
167			`//`
168			`// Decode of spr_addrimm`
169			`//`
170			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
171			`if (rst_or_except_flushpipe)`
172			`spr_addrimm <= #1 16'h0000;`
173			`else if (!pipeline_freeze) begin`
174			`case (id_insn[31:26]) // synopsys full_case parallel_case`
175			`// l.mtspr`
176			`OR32_MTSPR:
177			`spr_addrimm <= #1 id_insn[15:0];`
178			`// l.mfspr`
179			`default:`
180			`spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};`
181			`endcase`
182			`end`
183			`end`
184
185			`//`
186			`// Decode of multicycle`
187			`//`
188			`always @(id_insn) begin`
189			`case (id_insn[31:26]) // synopsys full_case parallel_case`
190
191			`// l.lwz`
192			`OR32_LWZ:
193			multicycle <= #1 `TWO_CYCLES;
194
195			`// l.lbz`
196			`OR32_LBZ:
197			multicycle <= #1 `TWO_CYCLES;
198
199			`// l.lbs`
200			`OR32_LBS:
201			multicycle <= #1 `TWO_CYCLES;
202
203			`// l.lhz`
204			`OR32_LHZ:
205			multicycle <= #1 `TWO_CYCLES;
206
207			`// l.lhs`
208			`OR32_LHS:
209			multicycle <= #1 `TWO_CYCLES;
210
211			`// l.sw`
212			`OR32_SW:
213			multicycle <= #1 `TWO_CYCLES;
214
215			`// l.sb`
216			`OR32_SB:
217			multicycle <= #1 `TWO_CYCLES;
218
219			`// l.sh`
220			`OR32_SH:
221			multicycle <= #1 `TWO_CYCLES;
222
223			`// ALU instructions except the one with immediate`
224			`OR32_ALU:
225			multicycle <= #1 id_insn[`ALUMCYC_POS];
226
227			`// Single cycle instructions`
228			`default: begin`
229			multicycle <= #1 `ONE_CYCLE;
230			`end`
231
232			`endcase`
233
234			`end`
235
236			`//`
237			`// Decode of imm_signextend`
238			`//`
239			`always @(id_insn) begin`
240			`case (id_insn[31:26]) // synopsys full_case parallel_case`
241
242			`// l.addi`
243			`OR32_ADDI:
244			imm_signextend <= #1 `on;
245
246			`// l.addic`
247			`OR32_ADDIC:
248			imm_signextend <= #1 `on;
249
250			`// l.xori`
251			`OR32_XORI:
252			imm_signextend <= #1 `on;
253
254			`// l.muli`
255			`OR32_MULI:
256			imm_signextend <= #1 `on;
257
258			`// l.maci`
259			`OR32_MACI:
260			imm_signextend <= #1 `on;
261
262			`// SFXX insns with immediate`
263			`OR32_SFXXI:
264			imm_signextend <= #1 `on;
265
266			`// Instructions with no or zero extended immediate`
267			`default: begin`
268			imm_signextend <= #1 `off;
269			`end`
270
271			`endcase`
272
273			`end`
274
275			`//`
276			`// LSU addr offset`
277			`//`
278			`always @(lsu_op or ex_insn) begin`
279			`lsu_addrofs[10:0] <= #1 ex_insn[10:0];`
280			`case(lsu_op) // synopsys parallel_case full_case`
281			`LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
282			`lsu_addrofs[31:11] <= #1 {{16{ex_insn[25]}}, ex_insn[25:21]};`
283			`default :`
284			`lsu_addrofs[31:11] <= #1 {{16{ex_insn[15]}}, ex_insn[15:11]};`
285			`endcase`
286			`end`
287
288			`//`
289			`// Register file write address`
290			`//`
291			`always @(posedge clk or posedge rst) begin`
292			`if (rst)`
293			`rf_addrw <= #1 5'd0;`
294			`else if (!pipeline_freeze)`
295			`case (pre_branch_op) // synopsys parallel_case full_case`
296			`BRANCHOP_JR, `BRANCHOP_BAL:
297			`rf_addrw <= #1 5'd09; // link register r9`
298			`default:`
299			`rf_addrw <= #1 id_insn[25:21];`
300			`endcase`
301			`end`
302
303			`//`
304			`// rf_addrw in wb stage (used in forwarding logic)`
305			`//`
306			`always @(posedge clk or posedge rst) begin`
307			`if (rst)`
308			`wb_rfaddrw <= #1 5'd0;`
309			`else if (!pipeline_freeze)`
310			`wb_rfaddrw <= #1 rf_addrw;`
311			`end`
312
313			`//`
314			`// Instruction latch in id_insn`
315			`//`
316			`always @(posedge clk or posedge rst) begin`
317			`if (rst) begin`
318			id_insn[31:26] <= #1 `OR32_NOP;
319			`id_insn[25:0] <= #1 26'd0;`
320			`end`
321			`else if (!pipeline_freeze) begin`
322			`id_insn <= #1 if_insn;`
323			`$display("%t: id_insn <= %h", $time, if_insn);`
324			`end`
325			`end`
326
327			`//`
328			`// Instruction latch in ex_insn`
329			`//`
330			`always @(posedge clk or posedge rst) begin`
331			`if (rst) begin`
332			ex_insn[31:26] <= #1 `OR32_NOP;
333			`ex_insn[25:0] <= #1 26'd0;`
334			`end`
335			`else if (!pipeline_freeze) begin`
336			`ex_insn <= #1 id_insn;`
337			`$display("%t: ex_insn <= %h", $time, id_insn);`
338			`end`
339			`end`
340
341			`//`
342			`// Instruction latch in wb_insn`
343			`//`
344			`always @(posedge clk or posedge rst) begin`
345			`if (rst) begin`
346			wb_insn[31:26] <= #1 `OR32_NOP;
347			`wb_insn[25:0] <= #1 26'd0;`
348			`end`
349			`else if (!pipeline_freeze) begin`
350			`wb_insn <= #1 ex_insn;`
351			`// synopsys translate_off`
352			`#3;`
353			`if ((wb_insn != 32'h1500ffff) && (wb_insn != 32'h14000000))`
354			`display_arch_state;`
355			`if (ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)`
356			`caught_sys203;`
357			`// synopsys translate_on`
358			`end`
359			`end`
360
361			`//`
362			`// Decode of sel_imm`
363			`//`
364			`always @(posedge clk or posedge rst) begin`
365			`if (rst)`
366			`sel_imm <= #1 1'b0;`
367			`else if (!pipeline_freeze) begin`
368			`case (if_insn[31:26]) // synopsys full_case parallel_case`
369
370			`// j.jalr`
371			`OR32_JALR:
372			sel_imm <= #1 `off;
373
374			`// l.jr`
375			`OR32_JR:
376			sel_imm <= #1 `off;
377
378			`// l.rfe`
379			`OR32_RFE:
380			sel_imm <= #1 `off;
381
382			`// l.mfspr`
383			`OR32_MFSPR:
384			sel_imm <= #1 `off;
385
386			`// l.mtspr`
387			`OR32_MTSPR:
388			sel_imm <= #1 `off;
389
390			`// l.sys, l.brk and all three sync insns`
391			`OR32_XSYNC:
392			sel_imm <= #1 `off;
393
394			`// l.sw`
395			`OR32_SW:
396			sel_imm <= #1 `off;
397
398			`// l.sb`
399			`OR32_SB:
400			sel_imm <= #1 `off;
401
402			`// l.sh`
403			`OR32_SH:
404			sel_imm <= #1 `off;
405
406			`// ALU instructions except the one with immediate`
407			`OR32_ALU:
408			sel_imm <= #1 `off;
409
410			`// SFXX instructions`
411			`OR32_SFXX:
412			sel_imm <= #1 `off;
413
414			`// l.nop`
415			`OR32_NOP:
416			sel_imm <= #1 `off;
417
418			`// All instructions with immediates`
419			`default: begin`
420			sel_imm <= #1 `on;
421			`end`
422
423			`endcase`
424
425			`end`
426			`end`
427
428
429			`//`
430			`// Decode of alu_op`
431			`//`
432			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
433			`if (rst_or_except_flushpipe)`
434			alu_op <= #1 `ALUOP_NOP;
435			`else if (!pipeline_freeze) begin`
436			`case (id_insn[31:26]) // synopsys full_case parallel_case`
437
438			`// l.j`
439			`OR32_J:
440			alu_op <= #1 `ALUOP_IMM;
441
442			`// j.jal`
443			`OR32_JAL:
444			alu_op <= #1 `ALUOP_IMM;
445
446			`// j.jalr`
447			`OR32_JALR:
448			alu_op <= #1 `ALUOP_OR;
449
450			`// l.jr`
451			`OR32_JR:
452			alu_op <= #1 `ALUOP_ADD;
453
454			`// l.bnf`
455			`OR32_BNF:
456			alu_op <= #1 `ALUOP_ADD;
457
458			`// l.bf`
459			`OR32_BF:
460			alu_op <= #1 `ALUOP_ADD;
461
462			`// l.rfe`
463			`OR32_RFE:
464			alu_op <= #1 `ALUOP_NOP;
465
466			`// l.movhi`
467			`OR32_MOVHI:
468			alu_op <= #1 `ALUOP_MOVHI;
469
470			`// l.mfspr`
471			`OR32_MFSPR:
472			alu_op <= #1 `ALUOP_MFSR;
473
474			`// l.mtspr`
475			`OR32_MTSPR:
476			alu_op <= #1 `ALUOP_MTSR;
477
478			`// l.sys, l.brk and all three sync insns`
479			`OR32_XSYNC:
480			alu_op <= #1 `ALUOP_NOP;
481
482			`// l.lwz`
483			`OR32_LWZ:
484			alu_op <= #1 `ALUOP_ADD;
485
486			`// l.lbz`
487			`OR32_LBZ:
488			alu_op <= #1 `ALUOP_ADD;
489
490			`// l.lbs`
491			`OR32_LBS:
492			alu_op <= #1 `ALUOP_ADD;
493
494			`// l.lhz`
495			`OR32_LHZ:
496			alu_op <= #1 `ALUOP_ADD;
497
498			`// l.lhs`
499			`OR32_LHS:
500			alu_op <= #1 `ALUOP_ADD;
501
502			`// l.addi`
503			`OR32_ADDI:
504			alu_op <= #1 `ALUOP_ADD;
505
506			`// l.addic`
507			`OR32_ADDIC:
508			alu_op <= #1 `ALUOP_ADD;
509
510			`// l.andi`
511			`OR32_ANDI:
512			alu_op <= #1 `ALUOP_AND;
513
514			`// l.ori`
515			`OR32_ORI:
516			alu_op <= #1 `ALUOP_OR;
517
518			`// l.xori`
519			`OR32_XORI:
520			alu_op <= #1 `ALUOP_XOR;
521
522			`// l.muli`
523			`OR32_MULI:
524			alu_op <= #1 `ALUOP_MUL;
525
526			`// l.maci`
527			`OR32_MACI:
528			alu_op <= #1 `ALUOP_MAC;
529
530			`// Shift and rotate insns with immediate`
531			`OR32_SH_ROTI:
532			alu_op <= #1 `ALUOP_SHROT;
533
534			`// SFXX insns with immediate`
535			`OR32_SFXXI:
536			alu_op <= #1 `ALUOP_COMP;
537
538			`// l.sw`
539			`OR32_SW:
540			alu_op <= #1 `ALUOP_ADD;
541
542			`// l.sb`
543			`OR32_SB:
544			alu_op <= #1 `ALUOP_ADD;
545
546			`// l.sh`
547			`OR32_SH:
548			alu_op <= #1 `ALUOP_ADD;
549
550			`// ALU instructions except the one with immediate`
551			`OR32_ALU:
552			`alu_op <= #1 id_insn[3:0];`
553
554			`// SFXX instructions`
555			`OR32_SFXX:
556			alu_op <= #1 `ALUOP_COMP;
557
558			`// l.nop`
559			`OR32_NOP:
560			alu_op <= #1 `ALUOP_NOP;
561
562			`// Illegal and OR1200 unsupported instructions`
563			`default: begin`
564			alu_op <= #1 `ALUOP_NOP;
565			`$display("%t: Illegal insn.... insn %h", $time, id_insn);`
566			`end`
567
568			`endcase`
569
570			`end`
571			`end`
572
573			`//`
574			`// Decode of shrot_op`
575			`//`
576			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
577			`if (rst_or_except_flushpipe)`
578			shrot_op <= #1 `SHROTOP_NOP;
579			`else if (!pipeline_freeze) begin`
580			shrot_op <= #1 id_insn[`SHROTOP_POS];
581			`end`
582			`end`
583
584			`//`
585			`// Decode of rfwb_op`
586			`//`
587			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
588			`if (rst_or_except_flushpipe)`
589			rfwb_op <= #1 `RFWBOP_NOP;
590			`else if (!pipeline_freeze) begin`
591			`case (id_insn[31:26]) // synopsys full_case parallel_case`
592
593			`// j.jal`
594			`OR32_JAL:
595			rfwb_op <= #1 `RFWBOP_LR;
596
597			`// j.jalr`
598			`OR32_JALR:
599			rfwb_op <= #1 `RFWBOP_LR;
600
601			`// l.movhi`
602			`OR32_MOVHI:
603			rfwb_op <= #1 `RFWBOP_ALU;
604
605			`// l.mfspr`
606			`OR32_MFSPR:
607			rfwb_op <= #1 `RFWBOP_SPRS;
608
609			`// l.lwz`
610			`OR32_LWZ:
611			rfwb_op <= #1 `RFWBOP_LSU;
612
613			`// l.lbz`
614			`OR32_LBZ:
615			rfwb_op <= #1 `RFWBOP_LSU;
616
617			`// l.lbs`
618			`OR32_LBS:
619			rfwb_op <= #1 `RFWBOP_LSU;
620
621			`// l.lhz`
622			`OR32_LHZ:
623			rfwb_op <= #1 `RFWBOP_LSU;
624
625			`// l.lhs`
626			`OR32_LHS:
627			rfwb_op <= #1 `RFWBOP_LSU;
628
629			`// l.addi`
630			`OR32_ADDI:
631			rfwb_op <= #1 `RFWBOP_ALU;
632
633			`// l.addic`
634			`OR32_ADDIC:
635			rfwb_op <= #1 `RFWBOP_ALU;
636
637			`// l.andi`
638			`OR32_ANDI:
639			rfwb_op <= #1 `RFWBOP_ALU;
640
641			`// l.ori`
642			`OR32_ORI:
643			rfwb_op <= #1 `RFWBOP_ALU;
644
645			`// l.xori`
646			`OR32_XORI:
647			rfwb_op <= #1 `RFWBOP_ALU;
648
649			`// l.muli`
650			`OR32_MULI:
651			rfwb_op <= #1 `RFWBOP_ALU;
652
653			`// l.maci`
654			`OR32_MACI:
655			rfwb_op <= #1 `RFWBOP_ALU;
656
657			`// Shift and rotate insns with immediate`
658			`OR32_SH_ROTI:
659			rfwb_op <= #1 `RFWBOP_ALU;
660
661			`// ALU instructions except the one with immediate`
662			`OR32_ALU:
663			rfwb_op <= #1 `RFWBOP_ALU;
664
665			`// Instructions w/o register-file write-back`
666			`default: begin`
667			rfwb_op <= #1 `RFWBOP_NOP;
668			`end`
669
670			`endcase`
671			`end`
672			`end`
673
674			`//`
675			`// Decode of pre_branch_op`
676			`//`
677			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
678			`if (rst_or_except_flushpipe)`
679			pre_branch_op <= #1 `BRANCHOP_NOP;
680			`else if (!pipeline_freeze) begin`
681			`case (if_insn[31:26]) // synopsys full_case parallel_case`
682
683			`// l.j`
684			`OR32_J:
685			pre_branch_op <= #1 `BRANCHOP_BAL;
686
687			`// j.jal`
688			`OR32_JAL:
689			pre_branch_op <= #1 `BRANCHOP_BAL;
690
691			`// j.jalr`
692			`OR32_JALR:
693			pre_branch_op <= #1 `BRANCHOP_JR;
694
695			`// l.jr`
696			`OR32_JR:
697			pre_branch_op <= #1 `BRANCHOP_JR;
698
699			`// l.bnf`
700			`OR32_BNF:
701			pre_branch_op <= #1 `BRANCHOP_BNF;
702
703			`// l.bf`
704			`OR32_BF:
705			pre_branch_op <= #1 `BRANCHOP_BF;
706
707			`// l.rfe`
708			`OR32_RFE:
709			pre_branch_op <= #1 `BRANCHOP_RFE;
710
711			`// Non branch instructions`
712			`default: begin`
713			pre_branch_op <= #1 `BRANCHOP_NOP;
714			`end`
715			`endcase`
716			`end`
717			`end`
718
719			`//`
720			`// Generation of branch_op`
721			`//`
722			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
723			`if (rst_or_except_flushpipe)`
724			branch_op <= #1 `BRANCHOP_NOP;
725			`else if (!pipeline_freeze) begin`
726			`branch_op <= #1 pre_branch_op;`
727			`end`
728			`end`
729
730			`//`
731			`// Decode of lsu_op`
732			`//`
733			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
734			`if (rst_or_except_flushpipe)`
735			lsu_op <= #1 `LSUOP_NOP;
736			`else if (!pipeline_freeze) begin`
737			`case (id_insn[31:26]) // synopsys full_case parallel_case`
738
739			`// l.lwz`
740			`OR32_LWZ:
741			lsu_op <= #1 `LSUOP_LWZ;
742
743			`// l.lbz`
744			`OR32_LBZ:
745			lsu_op <= #1 `LSUOP_LBZ;
746
747			`// l.lbs`
748			`OR32_LBS:
749			lsu_op <= #1 `LSUOP_LBS;
750
751			`// l.lhz`
752			`OR32_LHZ:
753			lsu_op <= #1 `LSUOP_LHZ;
754
755			`// l.lhs`
756			`OR32_LHS:
757			lsu_op <= #1 `LSUOP_LHS;
758
759			`// l.sw`
760			`OR32_SW:
761			lsu_op <= #1 `LSUOP_SW;
762
763			`// l.sb`
764			`OR32_SB:
765			lsu_op <= #1 `LSUOP_SB;
766
767			`// l.sh`
768			`OR32_SH:
769			lsu_op <= #1 `LSUOP_SH;
770
771			`// Non load/store instructions`
772			`default: begin`
773			lsu_op <= #1 `LSUOP_NOP;
774			`end`
775			`endcase`
776			`end`
777			`end`
778
779			`//`
780			`// Decode of comp_op`
781			`//`
782			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
783			`if (rst_or_except_flushpipe)`
784			`comp_op <= #1 4'd0;`
785			`else if (!pipeline_freeze) begin`
786			`comp_op <= #1 id_insn[24:21];`
787			`end`
788			`end`
789
790			`//`
791			`// Decode of l.sys`
792			`//`
793			`always @(posedge clk or posedge rst) begin`
794			`if (rst)`
795			`sig_syscall <= #1 1'b0;`
796			`else if (!pipeline_freeze) begin`
797			`// synopsys translate_off`
798			if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
799			`$display("Generating sig_syscall");`
800			`// synopsys translate_on`
801			sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00});
802			`end`
803			`end`
804
805			`endmodule`