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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction decode                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Majority of instruction decoding is performed here.         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module id(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        pipeline_freeze, except_flushpipe, if_insn, branch_op,
        rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
        wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
        multicycle, branch_stall, spr_addrimm, wbforw_valid, sig_syscall
);
 
//
// I/O
//
input                                   clk;
input                                   rst;
input                                   pipeline_freeze;
input                                   except_flushpipe;
input   [31:0]                           if_insn;
output  [`BRANCHOP_WIDTH-1:0]            branch_op;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addra;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrb;
output  [`ALUOP_WIDTH-1:0]               alu_op;
output  [`SHROTOP_WIDTH-1:0]             shrot_op;
output  [`RFWBOP_WIDTH-1:0]              rfwb_op;
output  [31:0]                           wb_insn;
output  [31:0]                           simm;
output  [31:2]                          branch_addrofs;
output  [31:0]                           lsu_addrofs;
output  [`SEL_WIDTH-1:0]         sel_a;
output  [`SEL_WIDTH-1:0]         sel_b;
output  [`LSUOP_WIDTH-1:0]               lsu_op;
output  [`COMPOP_WIDTH-1:0]              comp_op;
output  [`MULTICYCLE_WIDTH-1:0]          multicycle;
output                                  branch_stall;
output  [15:0]                           spr_addrimm;
input                                   wbforw_valid;
output                                  sig_syscall;
 
//
// Internal wires and regs
//
reg     [`BRANCHOP_WIDTH-1:0]            pre_branch_op;
reg     [`BRANCHOP_WIDTH-1:0]            branch_op;
reg     [`ALUOP_WIDTH-1:0]               alu_op;
reg     [`SHROTOP_WIDTH-1:0]             shrot_op;
reg     [31:0]                           id_insn;
reg     [31:0]                           ex_insn;
reg     [31:0]                           wb_insn;
reg     [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
reg     [`REGFILE_ADDR_WIDTH-1:0]        wb_rfaddrw;
reg     [`RFWBOP_WIDTH-1:0]              rfwb_op;
reg     [31:0]                           lsu_addrofs;
reg     [`SEL_WIDTH-1:0]         sel_a;
reg     [`SEL_WIDTH-1:0]         sel_b;
reg                                     sel_imm;
reg     [`LSUOP_WIDTH-1:0]               lsu_op;
reg     [`COMPOP_WIDTH-1:0]              comp_op;
reg     [`MULTICYCLE_WIDTH-1:0]          multicycle;
reg                                     imm_signextend;
reg     [15:0]                           spr_addrimm;
reg                                     sig_syscall;
wire                                    rst_or_except_flushpipe;
 
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
 
//
// Sign/Zero extension of immediates
//
assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
 
//
// Sign extension of branch offset
//
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
 
//
// Assert branch_stall if pre_branch_op is a branch operation
//
assign branch_stall = pre_branch_op ? 1'b1 : 1'b0;
 
//
// Async reset for most of pipeline flops
//
assign rst_or_except_flushpipe = rst | except_flushpipe;
 
//
// Generation of sel_a
//
always @(rf_addrw or wb_insn or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
                sel_a <= #1 `SEL_EX_FORW;
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
                sel_a <= #1 `SEL_WB_FORW;
        else
                sel_a <= #1 `SEL_RF;
 
//
// Generation of sel_b
//
always @(rf_addrw or wb_insn or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if (sel_imm)
                sel_b <= #1 `SEL_IMM;
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
                sel_b <= #1 `SEL_EX_FORW;
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
                sel_b <= #1 `SEL_WB_FORW;
        else
                sel_b <= #1 `SEL_RF;
 
//
// Decode of spr_addrimm
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                spr_addrimm <= #1 16'h0000;
        else if (!pipeline_freeze) begin
                case (id_insn[31:26])   // synopsys full_case parallel_case
                        // l.mtspr
                        `OR32_MTSPR:
                                spr_addrimm <= #1 id_insn[15:0];
                        // l.mfspr
                        default:
                                spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
                endcase
        end
end
 
//
// Decode of multicycle
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
    // l.lwz
    `OR32_LWZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lbz
    `OR32_LBZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lbs
    `OR32_LBS:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lhz
    `OR32_LHZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lhs
    `OR32_LHS:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sw
    `OR32_SW:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sb
    `OR32_SB:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sh
    `OR32_SH:
      multicycle <= #1 `TWO_CYCLES;
 
    // ALU instructions except the one with immediate
    `OR32_ALU:
      multicycle <= #1 id_insn[`ALUMCYC_POS];
 
    // Single cycle instructions
    default: begin
      multicycle <= #1 `ONE_CYCLE;
    end
 
  endcase
 
end
 
//
// Decode of imm_signextend
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
        // l.addi
        `OR32_ADDI:
                imm_signextend <= #1 `on;
 
        // l.addic
        `OR32_ADDIC:
                imm_signextend <= #1 `on;
 
        // l.xori
        `OR32_XORI:
                imm_signextend <= #1 `on;
 
        // l.muli
        `OR32_MULI:
                imm_signextend <= #1 `on;
 
        // l.maci
        `OR32_MACI:
                imm_signextend <= #1 `on;
 
        // SFXX insns with immediate
        `OR32_SFXXI:
                imm_signextend <= #1 `on;
 
        // Instructions with no or zero extended immediate
        default: begin
                imm_signextend <= #1 `off;
        end
 
endcase
 
end
 
//
// LSU addr offset
//
always @(lsu_op or ex_insn) begin
        lsu_addrofs[10:0] <= #1 ex_insn[10:0];
        case(lsu_op)    // synopsys parallel_case full_case
                `LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
                        lsu_addrofs[31:11] <= #1 {{16{ex_insn[25]}}, ex_insn[25:21]};
                default :
                        lsu_addrofs[31:11] <= #1 {{16{ex_insn[15]}}, ex_insn[15:11]};
        endcase
end
 
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
        if (rst)
                rf_addrw <= #1 5'd0;
        else if (!pipeline_freeze)
                case (pre_branch_op)    // synopsys parallel_case full_case
                        `BRANCHOP_JR, `BRANCHOP_BAL:
                                rf_addrw <= #1 5'd09;   // link register r9
                        default:
                                rf_addrw <= #1 id_insn[25:21];
                endcase
end
 
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
        if (rst)
                wb_rfaddrw <= #1 5'd0;
        else if (!pipeline_freeze)
                wb_rfaddrw <= #1 rf_addrw;
end
 
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_insn[31:26] <= #1 `OR32_NOP;
                id_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                id_insn <= #1 if_insn;
                $display("%t: id_insn <= %h", $time, if_insn);
        end
end
 
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_insn[31:26] <= #1 `OR32_NOP;
                ex_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                ex_insn <= #1 id_insn;
                $display("%t: ex_insn <= %h", $time, id_insn);
        end
end
 
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_insn[31:26] <= #1 `OR32_NOP;
                wb_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                wb_insn <= #1 ex_insn;
        end
end
 
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sel_imm <= #1 1'b0;
        else if (!pipeline_freeze) begin
          case (if_insn[31:26])         // synopsys full_case parallel_case
 
            // j.jalr
            `OR32_JALR:
              sel_imm <= #1 `off;
 
            // l.jr
            `OR32_JR:
              sel_imm <= #1 `off;
 
            // l.rfe
            `OR32_RFE:
              sel_imm <= #1 `off;
 
            // l.mfspr
            `OR32_MFSPR:
              sel_imm <= #1 `off;
 
            // l.mtspr
            `OR32_MTSPR:
              sel_imm <= #1 `off;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              sel_imm <= #1 `off;
 
            // l.sw
            `OR32_SW:
              sel_imm <= #1 `off;
 
            // l.sb
            `OR32_SB:
              sel_imm <= #1 `off;
 
            // l.sh
            `OR32_SH:
              sel_imm <= #1 `off;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              sel_imm <= #1 `off;
 
            // SFXX instructions
            `OR32_SFXX:
              sel_imm <= #1 `off;
 
            // l.nop
            `OR32_NOP:
              sel_imm <= #1 `off;
 
            // All instructions with immediates
            default: begin
              sel_imm <= #1 `on;
            end
 
          endcase
 
        end
end
 
 
//
// Decode of alu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                alu_op <= #1 `ALUOP_NOP;
        else if (!pipeline_freeze) begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.j
            `OR32_J:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jal
            `OR32_JAL:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jalr
            `OR32_JALR:
              alu_op <= #1 `ALUOP_OR;
 
            // l.jr
            `OR32_JR:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bnf
            `OR32_BNF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bf
            `OR32_BF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.rfe
            `OR32_RFE:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.movhi
            `OR32_MOVHI:
              alu_op <= #1 `ALUOP_MOVHI;
 
            // l.mfspr
            `OR32_MFSPR:
              alu_op <= #1 `ALUOP_MFSR;
 
            // l.mtspr
            `OR32_MTSPR:
              alu_op <= #1 `ALUOP_MTSR;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.lwz
            `OR32_LWZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbz
            `OR32_LBZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbs
            `OR32_LBS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhz
            `OR32_LHZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhs
            `OR32_LHS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addi
            `OR32_ADDI:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addic
            `OR32_ADDIC:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.andi
            `OR32_ANDI:
              alu_op <= #1 `ALUOP_AND;
 
            // l.ori
            `OR32_ORI:
              alu_op <= #1 `ALUOP_OR;
 
            // l.xori
            `OR32_XORI:
              alu_op <= #1 `ALUOP_XOR;
 
            // l.muli
            `OR32_MULI:
              alu_op <= #1 `ALUOP_MUL;
 
            // l.maci
            `OR32_MACI:
              alu_op <= #1 `ALUOP_MAC;
 
            // Shift and rotate insns with immediate
            `OR32_SH_ROTI:
              alu_op <= #1 `ALUOP_SHROT;
 
            // SFXX insns with immediate
            `OR32_SFXXI:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.sw
            `OR32_SW:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sb
            `OR32_SB:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sh
            `OR32_SH:
              alu_op <= #1 `ALUOP_ADD;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              alu_op <= #1 id_insn[3:0];
 
            // SFXX instructions
            `OR32_SFXX:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.nop
            `OR32_NOP:
              alu_op <= #1 `ALUOP_NOP;
 
            // Illegal and OR1200 unsupported instructions
            default: begin
              alu_op <= #1 `ALUOP_NOP;
              $display("%t: Illegal insn.... insn %h", $time, id_insn);
            end
 
          endcase
 
        end
end
 
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!pipeline_freeze) begin
                shrot_op <= #1 id_insn[`SHROTOP_POS];
        end
end
 
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!pipeline_freeze) begin
                case (id_insn[31:26])           // synopsys full_case parallel_case
 
                  // j.jal
                  `OR32_JAL:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // j.jalr
                  `OR32_JALR:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // l.movhi
                  `OR32_MOVHI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.mfspr
                  `OR32_MFSPR:
                    rfwb_op <= #1 `RFWBOP_SPRS;
 
                  // l.lwz
                  `OR32_LWZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbz
                  `OR32_LBZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbs
                  `OR32_LBS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhz
                  `OR32_LHZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhs
                  `OR32_LHS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.addi
                  `OR32_ADDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.addic
                  `OR32_ADDIC:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.andi
                  `OR32_ANDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.ori
                  `OR32_ORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.xori
                  `OR32_XORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.muli
                  `OR32_MULI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.maci
                  `OR32_MACI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Shift and rotate insns with immediate
                  `OR32_SH_ROTI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // ALU instructions except the one with immediate
                  `OR32_ALU:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Instructions w/o register-file write-back
                  default: begin
                    rfwb_op <= #1 `RFWBOP_NOP;
                  end
 
                endcase
        end
end
 
//
// Decode of pre_branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                pre_branch_op <= #1 `BRANCHOP_NOP;
        else if (!pipeline_freeze) begin
                case (if_insn[31:26])           // synopsys full_case parallel_case
 
                  // l.j
                  `OR32_J:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jal
                  `OR32_JAL:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jalr
                  `OR32_JALR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.jr
                  `OR32_JR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.bnf
                  `OR32_BNF:
                    pre_branch_op <= #1 `BRANCHOP_BNF;
 
                  // l.bf
                  `OR32_BF:
                    pre_branch_op <= #1 `BRANCHOP_BF;
 
                  // l.rfe
                  `OR32_RFE:
                    pre_branch_op <= #1 `BRANCHOP_RFE;
 
                  // Non branch instructions
                  default: begin
                    pre_branch_op <= #1 `BRANCHOP_NOP;
                  end
                endcase
        end
end
 
//
// Generation of branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!pipeline_freeze) begin
                branch_op <= #1 pre_branch_op;
        end
end
 
//
// Decode of lsu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!pipeline_freeze)  begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.lwz
            `OR32_LWZ:
              lsu_op <= #1 `LSUOP_LWZ;
 
            // l.lbz
            `OR32_LBZ:
              lsu_op <= #1 `LSUOP_LBZ;
 
            // l.lbs
            `OR32_LBS:
              lsu_op <= #1 `LSUOP_LBS;
 
            // l.lhz
            `OR32_LHZ:
              lsu_op <= #1 `LSUOP_LHZ;
 
            // l.lhs
            `OR32_LHS:
              lsu_op <= #1 `LSUOP_LHS;
 
            // l.sw
            `OR32_SW:
              lsu_op <= #1 `LSUOP_SW;
 
            // l.sb
            `OR32_SB:
              lsu_op <= #1 `LSUOP_SB;
 
            // l.sh
            `OR32_SH:
              lsu_op <= #1 `LSUOP_SH;
 
            // Non load/store instructions
            default: begin
              lsu_op <= #1 `LSUOP_NOP;
            end
          endcase
        end
end
 
//
// Decode of comp_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                comp_op <= #1 4'd0;
        else if (!pipeline_freeze) begin
                comp_op <= #1 id_insn[24:21];
        end
end
 
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_syscall <= #1 1'b0;
        else if (!pipeline_freeze) begin
// synopsys translate_off
                if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
                        $display("Generating sig_syscall");
// synopsys translate_on
//              sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00});
        end
end
 
endmodule

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Line No.	Rev	Author	Line
1	168	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction decode ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Majority of instruction decoding is performed here. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	170	lampret	`// Revision 1.1 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49	168	lampret	`//`
50	170	lampret	`//`
51	168	lampret
52			`include "timescale.v"
53			`include "defines.v"
54
55			`module id(`
56			`// Clock and reset`
57			`clk, rst,`
58
59			`// Internal i/f`
60			`pipeline_freeze, except_flushpipe, if_insn, branch_op,`
61			`rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,`
62			`wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,`
63			`multicycle, branch_stall, spr_addrimm, wbforw_valid, sig_syscall`
64			`);`
65
66			`//`
67			`// I/O`
68			`//`
69			`input clk;`
70			`input rst;`
71			`input pipeline_freeze;`
72			`input except_flushpipe;`
73			`input [31:0] if_insn;`
74			output [`BRANCHOP_WIDTH-1:0] branch_op;
75			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
76			output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
77			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrb;
78			output [`ALUOP_WIDTH-1:0] alu_op;
79			output [`SHROTOP_WIDTH-1:0] shrot_op;
80			output [`RFWBOP_WIDTH-1:0] rfwb_op;
81			`output [31:0] wb_insn;`
82			`output [31:0] simm;`
83			`output [31:2] branch_addrofs;`
84			`output [31:0] lsu_addrofs;`
85			output [`SEL_WIDTH-1:0] sel_a;
86			output [`SEL_WIDTH-1:0] sel_b;
87			output [`LSUOP_WIDTH-1:0] lsu_op;
88			output [`COMPOP_WIDTH-1:0] comp_op;
89			output [`MULTICYCLE_WIDTH-1:0] multicycle;
90			`output branch_stall;`
91			`output [15:0] spr_addrimm;`
92			`input wbforw_valid;`
93			`output sig_syscall;`
94
95			`//`
96			`// Internal wires and regs`
97			`//`
98			reg [`BRANCHOP_WIDTH-1:0] pre_branch_op;
99			reg [`BRANCHOP_WIDTH-1:0] branch_op;
100			reg [`ALUOP_WIDTH-1:0] alu_op;
101			reg [`SHROTOP_WIDTH-1:0] shrot_op;
102			`reg [31:0] id_insn;`
103			`reg [31:0] ex_insn;`
104			`reg [31:0] wb_insn;`
105			reg [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
106			reg [`REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
107			reg [`RFWBOP_WIDTH-1:0] rfwb_op;
108			`reg [31:0] lsu_addrofs;`
109			reg [`SEL_WIDTH-1:0] sel_a;
110			reg [`SEL_WIDTH-1:0] sel_b;
111			`reg sel_imm;`
112			reg [`LSUOP_WIDTH-1:0] lsu_op;
113			reg [`COMPOP_WIDTH-1:0] comp_op;
114			reg [`MULTICYCLE_WIDTH-1:0] multicycle;
115			`reg imm_signextend;`
116			`reg [15:0] spr_addrimm;`
117			`reg sig_syscall;`
118			`wire rst_or_except_flushpipe;`
119
120			`//`
121			`// Register file read addresses`
122			`//`
123			`assign rf_addra = if_insn[20:16];`
124			`assign rf_addrb = if_insn[15:11];`
125
126			`//`
127			`// Sign/Zero extension of immediates`
128			`//`
129			assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
130
131			`//`
132			`// Sign extension of branch offset`
133			`//`
134			`assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};`
135
136			`//`
137			`// Assert branch_stall if pre_branch_op is a branch operation`
138			`//`
139			`assign branch_stall = pre_branch_op ? 1'b1 : 1'b0;`
140
141			`//`
142			`// Async reset for most of pipeline flops`
143			`//`
144			`assign rst_or_except_flushpipe = rst \| except_flushpipe;`
145
146			`//`
147			`// Generation of sel_a`
148			`//`
149			`always @(rf_addrw or wb_insn or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
150			`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`
151			sel_a <= #1 `SEL_EX_FORW;
152			`else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)`
153			sel_a <= #1 `SEL_WB_FORW;
154			`else`
155			sel_a <= #1 `SEL_RF;
156
157			`//`
158			`// Generation of sel_b`
159			`//`
160			`always @(rf_addrw or wb_insn or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
161			`if (sel_imm)`
162			sel_b <= #1 `SEL_IMM;
163			`else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])`
164			sel_b <= #1 `SEL_EX_FORW;
165			`else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)`
166			sel_b <= #1 `SEL_WB_FORW;
167			`else`
168			sel_b <= #1 `SEL_RF;
169
170			`//`
171			`// Decode of spr_addrimm`
172			`//`
173			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
174			`if (rst_or_except_flushpipe)`
175			`spr_addrimm <= #1 16'h0000;`
176			`else if (!pipeline_freeze) begin`
177			`case (id_insn[31:26]) // synopsys full_case parallel_case`
178			`// l.mtspr`
179			`OR32_MTSPR:
180			`spr_addrimm <= #1 id_insn[15:0];`
181			`// l.mfspr`
182			`default:`
183			`spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};`
184			`endcase`
185			`end`
186			`end`
187
188			`//`
189			`// Decode of multicycle`
190			`//`
191			`always @(id_insn) begin`
192			`case (id_insn[31:26]) // synopsys full_case parallel_case`
193
194			`// l.lwz`
195			`OR32_LWZ:
196			multicycle <= #1 `TWO_CYCLES;
197
198			`// l.lbz`
199			`OR32_LBZ:
200			multicycle <= #1 `TWO_CYCLES;
201
202			`// l.lbs`
203			`OR32_LBS:
204			multicycle <= #1 `TWO_CYCLES;
205
206			`// l.lhz`
207			`OR32_LHZ:
208			multicycle <= #1 `TWO_CYCLES;
209
210			`// l.lhs`
211			`OR32_LHS:
212			multicycle <= #1 `TWO_CYCLES;
213
214			`// l.sw`
215			`OR32_SW:
216			multicycle <= #1 `TWO_CYCLES;
217
218			`// l.sb`
219			`OR32_SB:
220			multicycle <= #1 `TWO_CYCLES;
221
222			`// l.sh`
223			`OR32_SH:
224			multicycle <= #1 `TWO_CYCLES;
225
226			`// ALU instructions except the one with immediate`
227			`OR32_ALU:
228			multicycle <= #1 id_insn[`ALUMCYC_POS];
229
230			`// Single cycle instructions`
231			`default: begin`
232			multicycle <= #1 `ONE_CYCLE;
233			`end`
234
235			`endcase`
236
237			`end`
238
239			`//`
240			`// Decode of imm_signextend`
241			`//`
242			`always @(id_insn) begin`
243			`case (id_insn[31:26]) // synopsys full_case parallel_case`
244
245			`// l.addi`
246			`OR32_ADDI:
247			imm_signextend <= #1 `on;
248
249			`// l.addic`
250			`OR32_ADDIC:
251			imm_signextend <= #1 `on;
252
253			`// l.xori`
254			`OR32_XORI:
255			imm_signextend <= #1 `on;
256
257			`// l.muli`
258			`OR32_MULI:
259			imm_signextend <= #1 `on;
260
261			`// l.maci`
262			`OR32_MACI:
263			imm_signextend <= #1 `on;
264
265			`// SFXX insns with immediate`
266			`OR32_SFXXI:
267			imm_signextend <= #1 `on;
268
269			`// Instructions with no or zero extended immediate`
270			`default: begin`
271			imm_signextend <= #1 `off;
272			`end`
273
274			`endcase`
275
276			`end`
277
278			`//`
279			`// LSU addr offset`
280			`//`
281			`always @(lsu_op or ex_insn) begin`
282			`lsu_addrofs[10:0] <= #1 ex_insn[10:0];`
283			`case(lsu_op) // synopsys parallel_case full_case`
284			`LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
285			`lsu_addrofs[31:11] <= #1 {{16{ex_insn[25]}}, ex_insn[25:21]};`
286			`default :`
287			`lsu_addrofs[31:11] <= #1 {{16{ex_insn[15]}}, ex_insn[15:11]};`
288			`endcase`
289			`end`
290
291			`//`
292			`// Register file write address`
293			`//`
294			`always @(posedge clk or posedge rst) begin`
295			`if (rst)`
296			`rf_addrw <= #1 5'd0;`
297			`else if (!pipeline_freeze)`
298			`case (pre_branch_op) // synopsys parallel_case full_case`
299			`BRANCHOP_JR, `BRANCHOP_BAL:
300			`rf_addrw <= #1 5'd09; // link register r9`
301			`default:`
302			`rf_addrw <= #1 id_insn[25:21];`
303			`endcase`
304			`end`
305
306			`//`
307			`// rf_addrw in wb stage (used in forwarding logic)`
308			`//`
309			`always @(posedge clk or posedge rst) begin`
310			`if (rst)`
311			`wb_rfaddrw <= #1 5'd0;`
312			`else if (!pipeline_freeze)`
313			`wb_rfaddrw <= #1 rf_addrw;`
314			`end`
315
316			`//`
317			`// Instruction latch in id_insn`
318			`//`
319			`always @(posedge clk or posedge rst) begin`
320			`if (rst) begin`
321			id_insn[31:26] <= #1 `OR32_NOP;
322			`id_insn[25:0] <= #1 26'd0;`
323			`end`
324			`else if (!pipeline_freeze) begin`
325			`id_insn <= #1 if_insn;`
326			`$display("%t: id_insn <= %h", $time, if_insn);`
327			`end`
328			`end`
329
330			`//`
331			`// Instruction latch in ex_insn`
332			`//`
333			`always @(posedge clk or posedge rst) begin`
334			`if (rst) begin`
335			ex_insn[31:26] <= #1 `OR32_NOP;
336			`ex_insn[25:0] <= #1 26'd0;`
337			`end`
338			`else if (!pipeline_freeze) begin`
339			`ex_insn <= #1 id_insn;`
340			`$display("%t: ex_insn <= %h", $time, id_insn);`
341			`end`
342			`end`
343
344			`//`
345			`// Instruction latch in wb_insn`
346			`//`
347			`always @(posedge clk or posedge rst) begin`
348			`if (rst) begin`
349			wb_insn[31:26] <= #1 `OR32_NOP;
350			`wb_insn[25:0] <= #1 26'd0;`
351			`end`
352			`else if (!pipeline_freeze) begin`
353			`wb_insn <= #1 ex_insn;`
354			`end`
355			`end`
356
357			`//`
358			`// Decode of sel_imm`
359			`//`
360			`always @(posedge clk or posedge rst) begin`
361			`if (rst)`
362			`sel_imm <= #1 1'b0;`
363			`else if (!pipeline_freeze) begin`
364			`case (if_insn[31:26]) // synopsys full_case parallel_case`
365
366			`// j.jalr`
367			`OR32_JALR:
368			sel_imm <= #1 `off;
369
370			`// l.jr`
371			`OR32_JR:
372			sel_imm <= #1 `off;
373
374			`// l.rfe`
375			`OR32_RFE:
376			sel_imm <= #1 `off;
377
378			`// l.mfspr`
379			`OR32_MFSPR:
380			sel_imm <= #1 `off;
381
382			`// l.mtspr`
383			`OR32_MTSPR:
384			sel_imm <= #1 `off;
385
386			`// l.sys, l.brk and all three sync insns`
387			`OR32_XSYNC:
388			sel_imm <= #1 `off;
389
390			`// l.sw`
391			`OR32_SW:
392			sel_imm <= #1 `off;
393
394			`// l.sb`
395			`OR32_SB:
396			sel_imm <= #1 `off;
397
398			`// l.sh`
399			`OR32_SH:
400			sel_imm <= #1 `off;
401
402			`// ALU instructions except the one with immediate`
403			`OR32_ALU:
404			sel_imm <= #1 `off;
405
406			`// SFXX instructions`
407			`OR32_SFXX:
408			sel_imm <= #1 `off;
409
410			`// l.nop`
411			`OR32_NOP:
412			sel_imm <= #1 `off;
413
414			`// All instructions with immediates`
415			`default: begin`
416			sel_imm <= #1 `on;
417			`end`
418
419			`endcase`
420
421			`end`
422			`end`
423
424
425			`//`
426			`// Decode of alu_op`
427			`//`
428			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
429			`if (rst_or_except_flushpipe)`
430			alu_op <= #1 `ALUOP_NOP;
431			`else if (!pipeline_freeze) begin`
432			`case (id_insn[31:26]) // synopsys full_case parallel_case`
433
434			`// l.j`
435			`OR32_J:
436			alu_op <= #1 `ALUOP_IMM;
437
438			`// j.jal`
439			`OR32_JAL:
440			alu_op <= #1 `ALUOP_IMM;
441
442			`// j.jalr`
443			`OR32_JALR:
444			alu_op <= #1 `ALUOP_OR;
445
446			`// l.jr`
447			`OR32_JR:
448			alu_op <= #1 `ALUOP_ADD;
449
450			`// l.bnf`
451			`OR32_BNF:
452			alu_op <= #1 `ALUOP_ADD;
453
454			`// l.bf`
455			`OR32_BF:
456			alu_op <= #1 `ALUOP_ADD;
457
458			`// l.rfe`
459			`OR32_RFE:
460			alu_op <= #1 `ALUOP_NOP;
461
462			`// l.movhi`
463			`OR32_MOVHI:
464			alu_op <= #1 `ALUOP_MOVHI;
465
466			`// l.mfspr`
467			`OR32_MFSPR:
468			alu_op <= #1 `ALUOP_MFSR;
469
470			`// l.mtspr`
471			`OR32_MTSPR:
472			alu_op <= #1 `ALUOP_MTSR;
473
474			`// l.sys, l.brk and all three sync insns`
475			`OR32_XSYNC:
476			alu_op <= #1 `ALUOP_NOP;
477
478			`// l.lwz`
479			`OR32_LWZ:
480			alu_op <= #1 `ALUOP_ADD;
481
482			`// l.lbz`
483			`OR32_LBZ:
484			alu_op <= #1 `ALUOP_ADD;
485
486			`// l.lbs`
487			`OR32_LBS:
488			alu_op <= #1 `ALUOP_ADD;
489
490			`// l.lhz`
491			`OR32_LHZ:
492			alu_op <= #1 `ALUOP_ADD;
493
494			`// l.lhs`
495			`OR32_LHS:
496			alu_op <= #1 `ALUOP_ADD;
497
498			`// l.addi`
499			`OR32_ADDI:
500			alu_op <= #1 `ALUOP_ADD;
501
502			`// l.addic`
503			`OR32_ADDIC:
504			alu_op <= #1 `ALUOP_ADD;
505
506			`// l.andi`
507			`OR32_ANDI:
508			alu_op <= #1 `ALUOP_AND;
509
510			`// l.ori`
511			`OR32_ORI:
512			alu_op <= #1 `ALUOP_OR;
513
514			`// l.xori`
515			`OR32_XORI:
516			alu_op <= #1 `ALUOP_XOR;
517
518			`// l.muli`
519			`OR32_MULI:
520			alu_op <= #1 `ALUOP_MUL;
521
522			`// l.maci`
523			`OR32_MACI:
524			alu_op <= #1 `ALUOP_MAC;
525
526			`// Shift and rotate insns with immediate`
527			`OR32_SH_ROTI:
528			alu_op <= #1 `ALUOP_SHROT;
529
530			`// SFXX insns with immediate`
531			`OR32_SFXXI:
532			alu_op <= #1 `ALUOP_COMP;
533
534			`// l.sw`
535			`OR32_SW:
536			alu_op <= #1 `ALUOP_ADD;
537
538			`// l.sb`
539			`OR32_SB:
540			alu_op <= #1 `ALUOP_ADD;
541
542			`// l.sh`
543			`OR32_SH:
544			alu_op <= #1 `ALUOP_ADD;
545
546			`// ALU instructions except the one with immediate`
547			`OR32_ALU:
548			`alu_op <= #1 id_insn[3:0];`
549
550			`// SFXX instructions`
551			`OR32_SFXX:
552			alu_op <= #1 `ALUOP_COMP;
553
554			`// l.nop`
555			`OR32_NOP:
556			alu_op <= #1 `ALUOP_NOP;
557
558			`// Illegal and OR1200 unsupported instructions`
559			`default: begin`
560			alu_op <= #1 `ALUOP_NOP;
561			`$display("%t: Illegal insn.... insn %h", $time, id_insn);`
562			`end`
563
564			`endcase`
565
566			`end`
567			`end`
568
569			`//`
570			`// Decode of shrot_op`
571			`//`
572			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
573			`if (rst_or_except_flushpipe)`
574			shrot_op <= #1 `SHROTOP_NOP;
575			`else if (!pipeline_freeze) begin`
576			shrot_op <= #1 id_insn[`SHROTOP_POS];
577			`end`
578			`end`
579
580			`//`
581			`// Decode of rfwb_op`
582			`//`
583			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
584			`if (rst_or_except_flushpipe)`
585			rfwb_op <= #1 `RFWBOP_NOP;
586			`else if (!pipeline_freeze) begin`
587			`case (id_insn[31:26]) // synopsys full_case parallel_case`
588
589			`// j.jal`
590			`OR32_JAL:
591			rfwb_op <= #1 `RFWBOP_LR;
592
593			`// j.jalr`
594			`OR32_JALR:
595			rfwb_op <= #1 `RFWBOP_LR;
596
597			`// l.movhi`
598			`OR32_MOVHI:
599			rfwb_op <= #1 `RFWBOP_ALU;
600
601			`// l.mfspr`
602			`OR32_MFSPR:
603			rfwb_op <= #1 `RFWBOP_SPRS;
604
605			`// l.lwz`
606			`OR32_LWZ:
607			rfwb_op <= #1 `RFWBOP_LSU;
608
609			`// l.lbz`
610			`OR32_LBZ:
611			rfwb_op <= #1 `RFWBOP_LSU;
612
613			`// l.lbs`
614			`OR32_LBS:
615			rfwb_op <= #1 `RFWBOP_LSU;
616
617			`// l.lhz`
618			`OR32_LHZ:
619			rfwb_op <= #1 `RFWBOP_LSU;
620
621			`// l.lhs`
622			`OR32_LHS:
623			rfwb_op <= #1 `RFWBOP_LSU;
624
625			`// l.addi`
626			`OR32_ADDI:
627			rfwb_op <= #1 `RFWBOP_ALU;
628
629			`// l.addic`
630			`OR32_ADDIC:
631			rfwb_op <= #1 `RFWBOP_ALU;
632
633			`// l.andi`
634			`OR32_ANDI:
635			rfwb_op <= #1 `RFWBOP_ALU;
636
637			`// l.ori`
638			`OR32_ORI:
639			rfwb_op <= #1 `RFWBOP_ALU;
640
641			`// l.xori`
642			`OR32_XORI:
643			rfwb_op <= #1 `RFWBOP_ALU;
644
645			`// l.muli`
646			`OR32_MULI:
647			rfwb_op <= #1 `RFWBOP_ALU;
648
649			`// l.maci`
650			`OR32_MACI:
651			rfwb_op <= #1 `RFWBOP_ALU;
652
653			`// Shift and rotate insns with immediate`
654			`OR32_SH_ROTI:
655			rfwb_op <= #1 `RFWBOP_ALU;
656
657			`// ALU instructions except the one with immediate`
658			`OR32_ALU:
659			rfwb_op <= #1 `RFWBOP_ALU;
660
661			`// Instructions w/o register-file write-back`
662			`default: begin`
663			rfwb_op <= #1 `RFWBOP_NOP;
664			`end`
665
666			`endcase`
667			`end`
668			`end`
669
670			`//`
671			`// Decode of pre_branch_op`
672			`//`
673			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
674			`if (rst_or_except_flushpipe)`
675			pre_branch_op <= #1 `BRANCHOP_NOP;
676			`else if (!pipeline_freeze) begin`
677			`case (if_insn[31:26]) // synopsys full_case parallel_case`
678
679			`// l.j`
680			`OR32_J:
681			pre_branch_op <= #1 `BRANCHOP_BAL;
682
683			`// j.jal`
684			`OR32_JAL:
685			pre_branch_op <= #1 `BRANCHOP_BAL;
686
687			`// j.jalr`
688			`OR32_JALR:
689			pre_branch_op <= #1 `BRANCHOP_JR;
690
691			`// l.jr`
692			`OR32_JR:
693			pre_branch_op <= #1 `BRANCHOP_JR;
694
695			`// l.bnf`
696			`OR32_BNF:
697			pre_branch_op <= #1 `BRANCHOP_BNF;
698
699			`// l.bf`
700			`OR32_BF:
701			pre_branch_op <= #1 `BRANCHOP_BF;
702
703			`// l.rfe`
704			`OR32_RFE:
705			pre_branch_op <= #1 `BRANCHOP_RFE;
706
707			`// Non branch instructions`
708			`default: begin`
709			pre_branch_op <= #1 `BRANCHOP_NOP;
710			`end`
711			`endcase`
712			`end`
713			`end`
714
715			`//`
716			`// Generation of branch_op`
717			`//`
718			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
719			`if (rst_or_except_flushpipe)`
720			branch_op <= #1 `BRANCHOP_NOP;
721			`else if (!pipeline_freeze) begin`
722			`branch_op <= #1 pre_branch_op;`
723			`end`
724			`end`
725
726			`//`
727			`// Decode of lsu_op`
728			`//`
729			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
730			`if (rst_or_except_flushpipe)`
731			lsu_op <= #1 `LSUOP_NOP;
732			`else if (!pipeline_freeze) begin`
733			`case (id_insn[31:26]) // synopsys full_case parallel_case`
734
735			`// l.lwz`
736			`OR32_LWZ:
737			lsu_op <= #1 `LSUOP_LWZ;
738
739			`// l.lbz`
740			`OR32_LBZ:
741			lsu_op <= #1 `LSUOP_LBZ;
742
743			`// l.lbs`
744			`OR32_LBS:
745			lsu_op <= #1 `LSUOP_LBS;
746
747			`// l.lhz`
748			`OR32_LHZ:
749			lsu_op <= #1 `LSUOP_LHZ;
750
751			`// l.lhs`
752			`OR32_LHS:
753			lsu_op <= #1 `LSUOP_LHS;
754
755			`// l.sw`
756			`OR32_SW:
757			lsu_op <= #1 `LSUOP_SW;
758
759			`// l.sb`
760			`OR32_SB:
761			lsu_op <= #1 `LSUOP_SB;
762
763			`// l.sh`
764			`OR32_SH:
765			lsu_op <= #1 `LSUOP_SH;
766
767			`// Non load/store instructions`
768			`default: begin`
769			lsu_op <= #1 `LSUOP_NOP;
770			`end`
771			`endcase`
772			`end`
773			`end`
774
775			`//`
776			`// Decode of comp_op`
777			`//`
778			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
779			`if (rst_or_except_flushpipe)`
780			`comp_op <= #1 4'd0;`
781			`else if (!pipeline_freeze) begin`
782			`comp_op <= #1 id_insn[24:21];`
783			`end`
784			`end`
785
786			`//`
787			`// Decode of l.sys`
788			`//`
789			`always @(posedge clk or posedge rst) begin`
790			`if (rst)`
791			`sig_syscall <= #1 1'b0;`
792			`else if (!pipeline_freeze) begin`
793			`// synopsys translate_off`
794			if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
795			`$display("Generating sig_syscall");`
796			`// synopsys translate_on`
797	170	lampret	// sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00});
798	168	lampret	`end`
799			`end`
800
801			`endmodule`