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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction decode                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Majority of instruction decoding is performed here.         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module id(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        pipeline_freeze, except_flushpipe, if_insn, branch_op,
        rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
        wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
        multicycle, spr_addrimm, wbforw_valid, sig_syscall,
        force_dslot_fetch
);
 
//
// I/O
//
input                                   clk;
input                                   rst;
input                                   pipeline_freeze;
input                                   except_flushpipe;
input   [31:0]                           if_insn;
output  [`BRANCHOP_WIDTH-1:0]            branch_op;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addra;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrb;
output  [`ALUOP_WIDTH-1:0]               alu_op;
output  [`SHROTOP_WIDTH-1:0]             shrot_op;
output  [`RFWBOP_WIDTH-1:0]              rfwb_op;
output  [31:0]                           wb_insn;
output  [31:0]                           simm;
output  [31:2]                          branch_addrofs;
output  [31:0]                           lsu_addrofs;
output  [`SEL_WIDTH-1:0]         sel_a;
output  [`SEL_WIDTH-1:0]         sel_b;
output  [`LSUOP_WIDTH-1:0]               lsu_op;
output  [`COMPOP_WIDTH-1:0]              comp_op;
output  [`MULTICYCLE_WIDTH-1:0]          multicycle;
output  [15:0]                           spr_addrimm;
input                                   wbforw_valid;
output                                  sig_syscall;
output                                  force_dslot_fetch;
 
//
// Internal wires and regs
//
reg     [`BRANCHOP_WIDTH-1:0]            pre_branch_op;
reg     [`BRANCHOP_WIDTH-1:0]            branch_op;
reg     [`ALUOP_WIDTH-1:0]               alu_op;
reg     [`SHROTOP_WIDTH-1:0]             shrot_op;
reg     [31:0]                           id_insn;
reg     [31:0]                           ex_insn;
reg     [31:0]                           wb_insn;
reg     [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
reg     [`REGFILE_ADDR_WIDTH-1:0]        wb_rfaddrw;
reg     [`RFWBOP_WIDTH-1:0]              rfwb_op;
reg     [31:0]                           lsu_addrofs;
reg     [`SEL_WIDTH-1:0]         sel_a;
reg     [`SEL_WIDTH-1:0]         sel_b;
reg                                     sel_imm;
reg     [`LSUOP_WIDTH-1:0]               lsu_op;
reg     [`COMPOP_WIDTH-1:0]              comp_op;
reg     [`MULTICYCLE_WIDTH-1:0]          multicycle;
reg                                     imm_signextend;
reg     [15:0]                           spr_addrimm;
reg                                     sig_syscall;
wire                                    rst_or_except_flushpipe;
 
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
 
//
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
// instructions
//
assign force_dslot_fetch = (pre_branch_op && lsu_op);
 
//
// Sign/Zero extension of immediates
//
assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
 
//
// Sign extension of branch offset
//
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
 
//
// Async reset for most of pipeline flops
//
assign rst_or_except_flushpipe = rst | except_flushpipe;
 
//
// Generation of sel_a
//
always @(rf_addrw or wb_insn or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
                sel_a <= #1 `SEL_EX_FORW;
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
                sel_a <= #1 `SEL_WB_FORW;
        else
                sel_a <= #1 `SEL_RF;
 
//
// Generation of sel_b
//
always @(rf_addrw or wb_insn or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if (sel_imm)
                sel_b <= #1 `SEL_IMM;
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
                sel_b <= #1 `SEL_EX_FORW;
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
                sel_b <= #1 `SEL_WB_FORW;
        else
                sel_b <= #1 `SEL_RF;
 
//
// Decode of spr_addrimm
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                spr_addrimm <= #1 16'h0000;
        else if (!pipeline_freeze) begin
                case (id_insn[31:26])   // synopsys full_case parallel_case
                        // l.mtspr
                        `OR32_MTSPR:
                                spr_addrimm <= #1 id_insn[15:0];
                        // l.mfspr
                        default:
                                spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
                endcase
        end
end
 
//
// Decode of multicycle
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
    // l.lwz
    `OR32_LWZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lbz
    `OR32_LBZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lbs
    `OR32_LBS:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lhz
    `OR32_LHZ:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.lhs
    `OR32_LHS:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sw
    `OR32_SW:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sb
    `OR32_SB:
      multicycle <= #1 `TWO_CYCLES;
 
    // l.sh
    `OR32_SH:
      multicycle <= #1 `TWO_CYCLES;
 
    // ALU instructions except the one with immediate
    `OR32_ALU:
      multicycle <= #1 id_insn[`ALUMCYC_POS];
 
    // Single cycle instructions
    default: begin
      multicycle <= #1 `ONE_CYCLE;
    end
 
  endcase
 
end
 
//
// Decode of imm_signextend
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
        // l.addi
        `OR32_ADDI:
                imm_signextend <= #1 `on;
 
        // l.addic
        `OR32_ADDIC:
                imm_signextend <= #1 `on;
 
        // l.xori
        `OR32_XORI:
                imm_signextend <= #1 `on;
 
        // l.muli
        `OR32_MULI:
                imm_signextend <= #1 `on;
 
        // l.maci
        `OR32_MACI:
                imm_signextend <= #1 `on;
 
        // SFXX insns with immediate
        `OR32_SFXXI:
                imm_signextend <= #1 `on;
 
        // Instructions with no or zero extended immediate
        default: begin
                imm_signextend <= #1 `off;
        end
 
endcase
 
end
 
//
// LSU addr offset
//
always @(lsu_op or ex_insn) begin
        lsu_addrofs[10:0] <= #1 ex_insn[10:0];
        case(lsu_op)    // synopsys parallel_case full_case
                `LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
                        lsu_addrofs[31:11] <= #1 {{16{ex_insn[25]}}, ex_insn[25:21]};
                default :
                        lsu_addrofs[31:11] <= #1 {{16{ex_insn[15]}}, ex_insn[15:11]};
        endcase
end
 
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
        if (rst)
                rf_addrw <= #1 5'd0;
        else if (!pipeline_freeze)
                case (pre_branch_op)    // synopsys parallel_case full_case
                        `BRANCHOP_JR, `BRANCHOP_BAL:
                                rf_addrw <= #1 5'd09;   // link register r9
                        default:
                                rf_addrw <= #1 id_insn[25:21];
                endcase
end
 
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
        if (rst)
                wb_rfaddrw <= #1 5'd0;
        else if (!pipeline_freeze)
                wb_rfaddrw <= #1 rf_addrw;
end
 
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_insn[31:26] <= #1 `OR32_NOP;
                id_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                id_insn <= #1 if_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: id_insn <= %h", $time, if_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_insn[31:26] <= #1 `OR32_NOP;
                ex_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                ex_insn <= #1 id_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_insn <= %h", $time, id_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_insn[31:26] <= #1 `OR32_NOP;
                wb_insn[25:0] <= #1 26'd0;
        end
        else if (!pipeline_freeze) begin
                wb_insn <= #1 ex_insn;
        end
end
 
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sel_imm <= #1 1'b0;
        else if (!pipeline_freeze) begin
          case (if_insn[31:26])         // synopsys full_case parallel_case
 
            // j.jalr
            `OR32_JALR:
              sel_imm <= #1 `off;
 
            // l.jr
            `OR32_JR:
              sel_imm <= #1 `off;
 
            // l.rfe
            `OR32_RFE:
              sel_imm <= #1 `off;
 
            // l.mfspr
            `OR32_MFSPR:
              sel_imm <= #1 `off;
 
            // l.mtspr
            `OR32_MTSPR:
              sel_imm <= #1 `off;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              sel_imm <= #1 `off;
 
            // l.sw
            `OR32_SW:
              sel_imm <= #1 `off;
 
            // l.sb
            `OR32_SB:
              sel_imm <= #1 `off;
 
            // l.sh
            `OR32_SH:
              sel_imm <= #1 `off;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              sel_imm <= #1 `off;
 
            // SFXX instructions
            `OR32_SFXX:
              sel_imm <= #1 `off;
 
            // l.nop
            `OR32_NOP:
              sel_imm <= #1 `off;
 
            // All instructions with immediates
            default: begin
              sel_imm <= #1 `on;
            end
 
          endcase
 
        end
end
 
 
//
// Decode of alu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                alu_op <= #1 `ALUOP_NOP;
        else if (!pipeline_freeze) begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.j
            `OR32_J:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jal
            `OR32_JAL:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jalr
            `OR32_JALR:
              alu_op <= #1 `ALUOP_OR;
 
            // l.jr
            `OR32_JR:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bnf
            `OR32_BNF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bf
            `OR32_BF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.rfe
            `OR32_RFE:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.movhi
            `OR32_MOVHI:
              alu_op <= #1 `ALUOP_MOVHI;
 
            // l.mfspr
            `OR32_MFSPR:
              alu_op <= #1 `ALUOP_MFSR;
 
            // l.mtspr
            `OR32_MTSPR:
              alu_op <= #1 `ALUOP_MTSR;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.lwz
            `OR32_LWZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbz
            `OR32_LBZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbs
            `OR32_LBS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhz
            `OR32_LHZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhs
            `OR32_LHS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addi
            `OR32_ADDI:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addic
            `OR32_ADDIC:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.andi
            `OR32_ANDI:
              alu_op <= #1 `ALUOP_AND;
 
            // l.ori
            `OR32_ORI:
              alu_op <= #1 `ALUOP_OR;
 
            // l.xori
            `OR32_XORI:
              alu_op <= #1 `ALUOP_XOR;
 
            // l.muli
            `OR32_MULI:
              alu_op <= #1 `ALUOP_MUL;
 
            // l.maci
            `OR32_MACI:
              alu_op <= #1 `ALUOP_MAC;
 
            // Shift and rotate insns with immediate
            `OR32_SH_ROTI:
              alu_op <= #1 `ALUOP_SHROT;
 
            // SFXX insns with immediate
            `OR32_SFXXI:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.sw
            `OR32_SW:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sb
            `OR32_SB:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sh
            `OR32_SH:
              alu_op <= #1 `ALUOP_ADD;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              alu_op <= #1 id_insn[3:0];
 
            // SFXX instructions
            `OR32_SFXX:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.nop
            `OR32_NOP:
              alu_op <= #1 `ALUOP_NOP;
 
            // Illegal and OR1200 unsupported instructions
            default: begin
              alu_op <= #1 `ALUOP_NOP;
`ifdef OR1200_VERBOSE
// synopsys translate_off
              $display("%t: Illegal insn.... insn %h", $time, id_insn);
// synopsys translate_on
`endif
            end
 
          endcase
 
        end
end
 
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!pipeline_freeze) begin
                shrot_op <= #1 id_insn[`SHROTOP_POS];
        end
end
 
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!pipeline_freeze) begin
                case (id_insn[31:26])           // synopsys full_case parallel_case
 
                  // j.jal
                  `OR32_JAL:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // j.jalr
                  `OR32_JALR:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // l.movhi
                  `OR32_MOVHI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.mfspr
                  `OR32_MFSPR:
                    rfwb_op <= #1 `RFWBOP_SPRS;
 
                  // l.lwz
                  `OR32_LWZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbz
                  `OR32_LBZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbs
                  `OR32_LBS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhz
                  `OR32_LHZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhs
                  `OR32_LHS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.addi
                  `OR32_ADDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.addic
                  `OR32_ADDIC:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.andi
                  `OR32_ANDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.ori
                  `OR32_ORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.xori
                  `OR32_XORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.muli
                  `OR32_MULI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.maci
                  `OR32_MACI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Shift and rotate insns with immediate
                  `OR32_SH_ROTI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // ALU instructions except the one with immediate
                  `OR32_ALU:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Instructions w/o register-file write-back
                  default: begin
                    rfwb_op <= #1 `RFWBOP_NOP;
                  end
 
                endcase
        end
end
 
//
// Decode of pre_branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                pre_branch_op <= #1 `BRANCHOP_NOP;
        else if (!pipeline_freeze) begin
                case (if_insn[31:26])           // synopsys full_case parallel_case
 
                  // l.j
                  `OR32_J:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jal
                  `OR32_JAL:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jalr
                  `OR32_JALR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.jr
                  `OR32_JR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.bnf
                  `OR32_BNF:
                    pre_branch_op <= #1 `BRANCHOP_BNF;
 
                  // l.bf
                  `OR32_BF:
                    pre_branch_op <= #1 `BRANCHOP_BF;
 
                  // l.rfe
                  `OR32_RFE:
                    pre_branch_op <= #1 `BRANCHOP_RFE;
 
                  // Non branch instructions
                  default: begin
                    pre_branch_op <= #1 `BRANCHOP_NOP;
                  end
                endcase
        end
end
 
//
// Generation of branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!pipeline_freeze) begin
                branch_op <= #1 pre_branch_op;
        end
end
 
//
// Decode of lsu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!pipeline_freeze)  begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.lwz
            `OR32_LWZ:
              lsu_op <= #1 `LSUOP_LWZ;
 
            // l.lbz
            `OR32_LBZ:
              lsu_op <= #1 `LSUOP_LBZ;
 
            // l.lbs
            `OR32_LBS:
              lsu_op <= #1 `LSUOP_LBS;
 
            // l.lhz
            `OR32_LHZ:
              lsu_op <= #1 `LSUOP_LHZ;
 
            // l.lhs
            `OR32_LHS:
              lsu_op <= #1 `LSUOP_LHS;
 
            // l.sw
            `OR32_SW:
              lsu_op <= #1 `LSUOP_SW;
 
            // l.sb
            `OR32_SB:
              lsu_op <= #1 `LSUOP_SB;
 
            // l.sh
            `OR32_SH:
              lsu_op <= #1 `LSUOP_SH;
 
            // Non load/store instructions
            default: begin
              lsu_op <= #1 `LSUOP_NOP;
            end
          endcase
        end
end
 
//
// Decode of comp_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                comp_op <= #1 4'd0;
        else if (!pipeline_freeze) begin
                comp_op <= #1 id_insn[24:21];
        end
end
 
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_syscall <= #1 1'b0;
        else if (!pipeline_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
                        $display("Generating sig_syscall");
// synopsys translate_on
`endif
//              sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00});
        end
end
 
endmodule

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Line No.	Rev	Author	Line
1	168	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction decode ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Majority of instruction decoding is performed here. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.2 2001/08/13 03:36:20 lampret`
48			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
49			`//`
50	170	lampret	`// Revision 1.1 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52	168	lampret	`//`
53	170	lampret	`//`
54	168	lampret
55			`include "timescale.v"
56			`include "defines.v"
57
58			`module id(`
59			`// Clock and reset`
60			`clk, rst,`
61
62			`// Internal i/f`
63			`pipeline_freeze, except_flushpipe, if_insn, branch_op,`
64			`rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,`
65			`wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,`
66	203	lampret	`multicycle, spr_addrimm, wbforw_valid, sig_syscall,`
67			`force_dslot_fetch`
68	168	lampret	`);`
69
70			`//`
71			`// I/O`
72			`//`
73			`input clk;`
74			`input rst;`
75			`input pipeline_freeze;`
76			`input except_flushpipe;`
77			`input [31:0] if_insn;`
78			output [`BRANCHOP_WIDTH-1:0] branch_op;
79			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
80			output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
81			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrb;
82			output [`ALUOP_WIDTH-1:0] alu_op;
83			output [`SHROTOP_WIDTH-1:0] shrot_op;
84			output [`RFWBOP_WIDTH-1:0] rfwb_op;
85			`output [31:0] wb_insn;`
86			`output [31:0] simm;`
87			`output [31:2] branch_addrofs;`
88			`output [31:0] lsu_addrofs;`
89			output [`SEL_WIDTH-1:0] sel_a;
90			output [`SEL_WIDTH-1:0] sel_b;
91			output [`LSUOP_WIDTH-1:0] lsu_op;
92			output [`COMPOP_WIDTH-1:0] comp_op;
93			output [`MULTICYCLE_WIDTH-1:0] multicycle;
94			`output [15:0] spr_addrimm;`
95			`input wbforw_valid;`
96			`output sig_syscall;`
97	203	lampret	`output force_dslot_fetch;`
98	168	lampret
99			`//`
100			`// Internal wires and regs`
101			`//`
102			reg [`BRANCHOP_WIDTH-1:0] pre_branch_op;
103			reg [`BRANCHOP_WIDTH-1:0] branch_op;
104			reg [`ALUOP_WIDTH-1:0] alu_op;
105			reg [`SHROTOP_WIDTH-1:0] shrot_op;
106			`reg [31:0] id_insn;`
107			`reg [31:0] ex_insn;`
108			`reg [31:0] wb_insn;`
109			reg [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
110			reg [`REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
111			reg [`RFWBOP_WIDTH-1:0] rfwb_op;
112			`reg [31:0] lsu_addrofs;`
113			reg [`SEL_WIDTH-1:0] sel_a;
114			reg [`SEL_WIDTH-1:0] sel_b;
115			`reg sel_imm;`
116			reg [`LSUOP_WIDTH-1:0] lsu_op;
117			reg [`COMPOP_WIDTH-1:0] comp_op;
118			reg [`MULTICYCLE_WIDTH-1:0] multicycle;
119			`reg imm_signextend;`
120			`reg [15:0] spr_addrimm;`
121			`reg sig_syscall;`
122			`wire rst_or_except_flushpipe;`
123
124			`//`
125			`// Register file read addresses`
126			`//`
127			`assign rf_addra = if_insn[20:16];`
128			`assign rf_addrb = if_insn[15:11];`
129
130			`//`
131	203	lampret	`// Force fetch of delay slot instruction when jump/branch is preceeded by load/store`
132			`// instructions`
133			`//`
134			`assign force_dslot_fetch = (pre_branch_op && lsu_op);`
135
136			`//`
137	168	lampret	`// Sign/Zero extension of immediates`
138			`//`
139			assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
140
141			`//`
142			`// Sign extension of branch offset`
143			`//`
144			`assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};`
145
146			`//`
147			`// Async reset for most of pipeline flops`
148			`//`
149			`assign rst_or_except_flushpipe = rst \| except_flushpipe;`
150
151			`//`
152			`// Generation of sel_a`
153			`//`
154			`always @(rf_addrw or wb_insn or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
155			`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`
156			sel_a <= #1 `SEL_EX_FORW;
157			`else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)`
158			sel_a <= #1 `SEL_WB_FORW;
159			`else`
160			sel_a <= #1 `SEL_RF;
161
162			`//`
163			`// Generation of sel_b`
164			`//`
165			`always @(rf_addrw or wb_insn or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
166			`if (sel_imm)`
167			sel_b <= #1 `SEL_IMM;
168			`else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])`
169			sel_b <= #1 `SEL_EX_FORW;
170			`else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)`
171			sel_b <= #1 `SEL_WB_FORW;
172			`else`
173			sel_b <= #1 `SEL_RF;
174
175			`//`
176			`// Decode of spr_addrimm`
177			`//`
178			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
179			`if (rst_or_except_flushpipe)`
180			`spr_addrimm <= #1 16'h0000;`
181			`else if (!pipeline_freeze) begin`
182			`case (id_insn[31:26]) // synopsys full_case parallel_case`
183			`// l.mtspr`
184			`OR32_MTSPR:
185			`spr_addrimm <= #1 id_insn[15:0];`
186			`// l.mfspr`
187			`default:`
188			`spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};`
189			`endcase`
190			`end`
191			`end`
192
193			`//`
194			`// Decode of multicycle`
195			`//`
196			`always @(id_insn) begin`
197			`case (id_insn[31:26]) // synopsys full_case parallel_case`
198
199			`// l.lwz`
200			`OR32_LWZ:
201			multicycle <= #1 `TWO_CYCLES;
202
203			`// l.lbz`
204			`OR32_LBZ:
205			multicycle <= #1 `TWO_CYCLES;
206
207			`// l.lbs`
208			`OR32_LBS:
209			multicycle <= #1 `TWO_CYCLES;
210
211			`// l.lhz`
212			`OR32_LHZ:
213			multicycle <= #1 `TWO_CYCLES;
214
215			`// l.lhs`
216			`OR32_LHS:
217			multicycle <= #1 `TWO_CYCLES;
218
219			`// l.sw`
220			`OR32_SW:
221			multicycle <= #1 `TWO_CYCLES;
222
223			`// l.sb`
224			`OR32_SB:
225			multicycle <= #1 `TWO_CYCLES;
226
227			`// l.sh`
228			`OR32_SH:
229			multicycle <= #1 `TWO_CYCLES;
230
231			`// ALU instructions except the one with immediate`
232			`OR32_ALU:
233			multicycle <= #1 id_insn[`ALUMCYC_POS];
234
235			`// Single cycle instructions`
236			`default: begin`
237			multicycle <= #1 `ONE_CYCLE;
238			`end`
239
240			`endcase`
241
242			`end`
243
244			`//`
245			`// Decode of imm_signextend`
246			`//`
247			`always @(id_insn) begin`
248			`case (id_insn[31:26]) // synopsys full_case parallel_case`
249
250			`// l.addi`
251			`OR32_ADDI:
252			imm_signextend <= #1 `on;
253
254			`// l.addic`
255			`OR32_ADDIC:
256			imm_signextend <= #1 `on;
257
258			`// l.xori`
259			`OR32_XORI:
260			imm_signextend <= #1 `on;
261
262			`// l.muli`
263			`OR32_MULI:
264			imm_signextend <= #1 `on;
265
266			`// l.maci`
267			`OR32_MACI:
268			imm_signextend <= #1 `on;
269
270			`// SFXX insns with immediate`
271			`OR32_SFXXI:
272			imm_signextend <= #1 `on;
273
274			`// Instructions with no or zero extended immediate`
275			`default: begin`
276			imm_signextend <= #1 `off;
277			`end`
278
279			`endcase`
280
281			`end`
282
283			`//`
284			`// LSU addr offset`
285			`//`
286			`always @(lsu_op or ex_insn) begin`
287			`lsu_addrofs[10:0] <= #1 ex_insn[10:0];`
288			`case(lsu_op) // synopsys parallel_case full_case`
289			`LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
290			`lsu_addrofs[31:11] <= #1 {{16{ex_insn[25]}}, ex_insn[25:21]};`
291			`default :`
292			`lsu_addrofs[31:11] <= #1 {{16{ex_insn[15]}}, ex_insn[15:11]};`
293			`endcase`
294			`end`
295
296			`//`
297			`// Register file write address`
298			`//`
299			`always @(posedge clk or posedge rst) begin`
300			`if (rst)`
301			`rf_addrw <= #1 5'd0;`
302			`else if (!pipeline_freeze)`
303			`case (pre_branch_op) // synopsys parallel_case full_case`
304			`BRANCHOP_JR, `BRANCHOP_BAL:
305			`rf_addrw <= #1 5'd09; // link register r9`
306			`default:`
307			`rf_addrw <= #1 id_insn[25:21];`
308			`endcase`
309			`end`
310
311			`//`
312			`// rf_addrw in wb stage (used in forwarding logic)`
313			`//`
314			`always @(posedge clk or posedge rst) begin`
315			`if (rst)`
316			`wb_rfaddrw <= #1 5'd0;`
317			`else if (!pipeline_freeze)`
318			`wb_rfaddrw <= #1 rf_addrw;`
319			`end`
320
321			`//`
322			`// Instruction latch in id_insn`
323			`//`
324			`always @(posedge clk or posedge rst) begin`
325			`if (rst) begin`
326			id_insn[31:26] <= #1 `OR32_NOP;
327			`id_insn[25:0] <= #1 26'd0;`
328			`end`
329			`else if (!pipeline_freeze) begin`
330			`id_insn <= #1 if_insn;`
331	203	lampret	`ifdef OR1200_VERBOSE
332			`// synopsys translate_off`
333	168	lampret	`$display("%t: id_insn <= %h", $time, if_insn);`
334	203	lampret	`// synopsys translate_on`
335			`endif
336	168	lampret	`end`
337			`end`
338
339			`//`
340			`// Instruction latch in ex_insn`
341			`//`
342			`always @(posedge clk or posedge rst) begin`
343			`if (rst) begin`
344			ex_insn[31:26] <= #1 `OR32_NOP;
345			`ex_insn[25:0] <= #1 26'd0;`
346			`end`
347			`else if (!pipeline_freeze) begin`
348			`ex_insn <= #1 id_insn;`
349	203	lampret	`ifdef OR1200_VERBOSE
350			`// synopsys translate_off`
351	168	lampret	`$display("%t: ex_insn <= %h", $time, id_insn);`
352	203	lampret	`// synopsys translate_on`
353			`endif
354	168	lampret	`end`
355			`end`
356
357			`//`
358			`// Instruction latch in wb_insn`
359			`//`
360			`always @(posedge clk or posedge rst) begin`
361			`if (rst) begin`
362			wb_insn[31:26] <= #1 `OR32_NOP;
363			`wb_insn[25:0] <= #1 26'd0;`
364			`end`
365			`else if (!pipeline_freeze) begin`
366			`wb_insn <= #1 ex_insn;`
367			`end`
368			`end`
369
370			`//`
371			`// Decode of sel_imm`
372			`//`
373			`always @(posedge clk or posedge rst) begin`
374			`if (rst)`
375			`sel_imm <= #1 1'b0;`
376			`else if (!pipeline_freeze) begin`
377			`case (if_insn[31:26]) // synopsys full_case parallel_case`
378
379			`// j.jalr`
380			`OR32_JALR:
381			sel_imm <= #1 `off;
382
383			`// l.jr`
384			`OR32_JR:
385			sel_imm <= #1 `off;
386
387			`// l.rfe`
388			`OR32_RFE:
389			sel_imm <= #1 `off;
390
391			`// l.mfspr`
392			`OR32_MFSPR:
393			sel_imm <= #1 `off;
394
395			`// l.mtspr`
396			`OR32_MTSPR:
397			sel_imm <= #1 `off;
398
399			`// l.sys, l.brk and all three sync insns`
400			`OR32_XSYNC:
401			sel_imm <= #1 `off;
402
403			`// l.sw`
404			`OR32_SW:
405			sel_imm <= #1 `off;
406
407			`// l.sb`
408			`OR32_SB:
409			sel_imm <= #1 `off;
410
411			`// l.sh`
412			`OR32_SH:
413			sel_imm <= #1 `off;
414
415			`// ALU instructions except the one with immediate`
416			`OR32_ALU:
417			sel_imm <= #1 `off;
418
419			`// SFXX instructions`
420			`OR32_SFXX:
421			sel_imm <= #1 `off;
422
423			`// l.nop`
424			`OR32_NOP:
425			sel_imm <= #1 `off;
426
427			`// All instructions with immediates`
428			`default: begin`
429			sel_imm <= #1 `on;
430			`end`
431
432			`endcase`
433
434			`end`
435			`end`
436
437
438			`//`
439			`// Decode of alu_op`
440			`//`
441			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
442			`if (rst_or_except_flushpipe)`
443			alu_op <= #1 `ALUOP_NOP;
444			`else if (!pipeline_freeze) begin`
445			`case (id_insn[31:26]) // synopsys full_case parallel_case`
446
447			`// l.j`
448			`OR32_J:
449			alu_op <= #1 `ALUOP_IMM;
450
451			`// j.jal`
452			`OR32_JAL:
453			alu_op <= #1 `ALUOP_IMM;
454
455			`// j.jalr`
456			`OR32_JALR:
457			alu_op <= #1 `ALUOP_OR;
458
459			`// l.jr`
460			`OR32_JR:
461			alu_op <= #1 `ALUOP_ADD;
462
463			`// l.bnf`
464			`OR32_BNF:
465			alu_op <= #1 `ALUOP_ADD;
466
467			`// l.bf`
468			`OR32_BF:
469			alu_op <= #1 `ALUOP_ADD;
470
471			`// l.rfe`
472			`OR32_RFE:
473			alu_op <= #1 `ALUOP_NOP;
474
475			`// l.movhi`
476			`OR32_MOVHI:
477			alu_op <= #1 `ALUOP_MOVHI;
478
479			`// l.mfspr`
480			`OR32_MFSPR:
481			alu_op <= #1 `ALUOP_MFSR;
482
483			`// l.mtspr`
484			`OR32_MTSPR:
485			alu_op <= #1 `ALUOP_MTSR;
486
487			`// l.sys, l.brk and all three sync insns`
488			`OR32_XSYNC:
489			alu_op <= #1 `ALUOP_NOP;
490
491			`// l.lwz`
492			`OR32_LWZ:
493			alu_op <= #1 `ALUOP_ADD;
494
495			`// l.lbz`
496			`OR32_LBZ:
497			alu_op <= #1 `ALUOP_ADD;
498
499			`// l.lbs`
500			`OR32_LBS:
501			alu_op <= #1 `ALUOP_ADD;
502
503			`// l.lhz`
504			`OR32_LHZ:
505			alu_op <= #1 `ALUOP_ADD;
506
507			`// l.lhs`
508			`OR32_LHS:
509			alu_op <= #1 `ALUOP_ADD;
510
511			`// l.addi`
512			`OR32_ADDI:
513			alu_op <= #1 `ALUOP_ADD;
514
515			`// l.addic`
516			`OR32_ADDIC:
517			alu_op <= #1 `ALUOP_ADD;
518
519			`// l.andi`
520			`OR32_ANDI:
521			alu_op <= #1 `ALUOP_AND;
522
523			`// l.ori`
524			`OR32_ORI:
525			alu_op <= #1 `ALUOP_OR;
526
527			`// l.xori`
528			`OR32_XORI:
529			alu_op <= #1 `ALUOP_XOR;
530
531			`// l.muli`
532			`OR32_MULI:
533			alu_op <= #1 `ALUOP_MUL;
534
535			`// l.maci`
536			`OR32_MACI:
537			alu_op <= #1 `ALUOP_MAC;
538
539			`// Shift and rotate insns with immediate`
540			`OR32_SH_ROTI:
541			alu_op <= #1 `ALUOP_SHROT;
542
543			`// SFXX insns with immediate`
544			`OR32_SFXXI:
545			alu_op <= #1 `ALUOP_COMP;
546
547			`// l.sw`
548			`OR32_SW:
549			alu_op <= #1 `ALUOP_ADD;
550
551			`// l.sb`
552			`OR32_SB:
553			alu_op <= #1 `ALUOP_ADD;
554
555			`// l.sh`
556			`OR32_SH:
557			alu_op <= #1 `ALUOP_ADD;
558
559			`// ALU instructions except the one with immediate`
560			`OR32_ALU:
561			`alu_op <= #1 id_insn[3:0];`
562
563			`// SFXX instructions`
564			`OR32_SFXX:
565			alu_op <= #1 `ALUOP_COMP;
566
567			`// l.nop`
568			`OR32_NOP:
569			alu_op <= #1 `ALUOP_NOP;
570
571			`// Illegal and OR1200 unsupported instructions`
572			`default: begin`
573			alu_op <= #1 `ALUOP_NOP;
574	203	lampret	`ifdef OR1200_VERBOSE
575			`// synopsys translate_off`
576	168	lampret	`$display("%t: Illegal insn.... insn %h", $time, id_insn);`
577	203	lampret	`// synopsys translate_on`
578			`endif
579	168	lampret	`end`
580
581			`endcase`
582
583			`end`
584			`end`
585
586			`//`
587			`// Decode of shrot_op`
588			`//`
589			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
590			`if (rst_or_except_flushpipe)`
591			shrot_op <= #1 `SHROTOP_NOP;
592			`else if (!pipeline_freeze) begin`
593			shrot_op <= #1 id_insn[`SHROTOP_POS];
594			`end`
595			`end`
596
597			`//`
598			`// Decode of rfwb_op`
599			`//`
600			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
601			`if (rst_or_except_flushpipe)`
602			rfwb_op <= #1 `RFWBOP_NOP;
603			`else if (!pipeline_freeze) begin`
604			`case (id_insn[31:26]) // synopsys full_case parallel_case`
605
606			`// j.jal`
607			`OR32_JAL:
608			rfwb_op <= #1 `RFWBOP_LR;
609
610			`// j.jalr`
611			`OR32_JALR:
612			rfwb_op <= #1 `RFWBOP_LR;
613
614			`// l.movhi`
615			`OR32_MOVHI:
616			rfwb_op <= #1 `RFWBOP_ALU;
617
618			`// l.mfspr`
619			`OR32_MFSPR:
620			rfwb_op <= #1 `RFWBOP_SPRS;
621
622			`// l.lwz`
623			`OR32_LWZ:
624			rfwb_op <= #1 `RFWBOP_LSU;
625
626			`// l.lbz`
627			`OR32_LBZ:
628			rfwb_op <= #1 `RFWBOP_LSU;
629
630			`// l.lbs`
631			`OR32_LBS:
632			rfwb_op <= #1 `RFWBOP_LSU;
633
634			`// l.lhz`
635			`OR32_LHZ:
636			rfwb_op <= #1 `RFWBOP_LSU;
637
638			`// l.lhs`
639			`OR32_LHS:
640			rfwb_op <= #1 `RFWBOP_LSU;
641
642			`// l.addi`
643			`OR32_ADDI:
644			rfwb_op <= #1 `RFWBOP_ALU;
645
646			`// l.addic`
647			`OR32_ADDIC:
648			rfwb_op <= #1 `RFWBOP_ALU;
649
650			`// l.andi`
651			`OR32_ANDI:
652			rfwb_op <= #1 `RFWBOP_ALU;
653
654			`// l.ori`
655			`OR32_ORI:
656			rfwb_op <= #1 `RFWBOP_ALU;
657
658			`// l.xori`
659			`OR32_XORI:
660			rfwb_op <= #1 `RFWBOP_ALU;
661
662			`// l.muli`
663			`OR32_MULI:
664			rfwb_op <= #1 `RFWBOP_ALU;
665
666			`// l.maci`
667			`OR32_MACI:
668			rfwb_op <= #1 `RFWBOP_ALU;
669
670			`// Shift and rotate insns with immediate`
671			`OR32_SH_ROTI:
672			rfwb_op <= #1 `RFWBOP_ALU;
673
674			`// ALU instructions except the one with immediate`
675			`OR32_ALU:
676			rfwb_op <= #1 `RFWBOP_ALU;
677
678			`// Instructions w/o register-file write-back`
679			`default: begin`
680			rfwb_op <= #1 `RFWBOP_NOP;
681			`end`
682
683			`endcase`
684			`end`
685			`end`
686
687			`//`
688			`// Decode of pre_branch_op`
689			`//`
690			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
691			`if (rst_or_except_flushpipe)`
692			pre_branch_op <= #1 `BRANCHOP_NOP;
693			`else if (!pipeline_freeze) begin`
694			`case (if_insn[31:26]) // synopsys full_case parallel_case`
695
696			`// l.j`
697			`OR32_J:
698			pre_branch_op <= #1 `BRANCHOP_BAL;
699
700			`// j.jal`
701			`OR32_JAL:
702			pre_branch_op <= #1 `BRANCHOP_BAL;
703
704			`// j.jalr`
705			`OR32_JALR:
706			pre_branch_op <= #1 `BRANCHOP_JR;
707
708			`// l.jr`
709			`OR32_JR:
710			pre_branch_op <= #1 `BRANCHOP_JR;
711
712			`// l.bnf`
713			`OR32_BNF:
714			pre_branch_op <= #1 `BRANCHOP_BNF;
715
716			`// l.bf`
717			`OR32_BF:
718			pre_branch_op <= #1 `BRANCHOP_BF;
719
720			`// l.rfe`
721			`OR32_RFE:
722			pre_branch_op <= #1 `BRANCHOP_RFE;
723
724			`// Non branch instructions`
725			`default: begin`
726			pre_branch_op <= #1 `BRANCHOP_NOP;
727			`end`
728			`endcase`
729			`end`
730			`end`
731
732			`//`
733			`// Generation of branch_op`
734			`//`
735			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
736			`if (rst_or_except_flushpipe)`
737			branch_op <= #1 `BRANCHOP_NOP;
738			`else if (!pipeline_freeze) begin`
739			`branch_op <= #1 pre_branch_op;`
740			`end`
741			`end`
742
743			`//`
744			`// Decode of lsu_op`
745			`//`
746			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
747			`if (rst_or_except_flushpipe)`
748			lsu_op <= #1 `LSUOP_NOP;
749			`else if (!pipeline_freeze) begin`
750			`case (id_insn[31:26]) // synopsys full_case parallel_case`
751
752			`// l.lwz`
753			`OR32_LWZ:
754			lsu_op <= #1 `LSUOP_LWZ;
755
756			`// l.lbz`
757			`OR32_LBZ:
758			lsu_op <= #1 `LSUOP_LBZ;
759
760			`// l.lbs`
761			`OR32_LBS:
762			lsu_op <= #1 `LSUOP_LBS;
763
764			`// l.lhz`
765			`OR32_LHZ:
766			lsu_op <= #1 `LSUOP_LHZ;
767
768			`// l.lhs`
769			`OR32_LHS:
770			lsu_op <= #1 `LSUOP_LHS;
771
772			`// l.sw`
773			`OR32_SW:
774			lsu_op <= #1 `LSUOP_SW;
775
776			`// l.sb`
777			`OR32_SB:
778			lsu_op <= #1 `LSUOP_SB;
779
780			`// l.sh`
781			`OR32_SH:
782			lsu_op <= #1 `LSUOP_SH;
783
784			`// Non load/store instructions`
785			`default: begin`
786			lsu_op <= #1 `LSUOP_NOP;
787			`end`
788			`endcase`
789			`end`
790			`end`
791
792			`//`
793			`// Decode of comp_op`
794			`//`
795			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
796			`if (rst_or_except_flushpipe)`
797			`comp_op <= #1 4'd0;`
798			`else if (!pipeline_freeze) begin`
799			`comp_op <= #1 id_insn[24:21];`
800			`end`
801			`end`
802
803			`//`
804			`// Decode of l.sys`
805			`//`
806			`always @(posedge clk or posedge rst) begin`
807			`if (rst)`
808			`sig_syscall <= #1 1'b0;`
809			`else if (!pipeline_freeze) begin`
810	203	lampret	`ifdef OR1200_VERBOSE
811	168	lampret	`// synopsys translate_off`
812			if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
813			`$display("Generating sig_syscall");`
814			`// synopsys translate_on`
815	203	lampret	`endif
816	170	lampret	// sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00});
817	168	lampret	`end`
818			`end`
819
820			`endmodule`