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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction decode                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Majority of instruction decoding is performed here.         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module id(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,
        rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
        wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
        multicycle, spr_addrimm, wbforw_valid, sig_syscall,
        force_dslot_fetch, id_macrc_op, ex_macrc_op
);
 
//
// I/O
//
input                                   clk;
input                                   rst;
input                                   id_freeze;
input                                   ex_freeze;
input                                   wb_freeze;
input                                   except_flushpipe;
input   [31:0]                           if_insn;
output  [`BRANCHOP_WIDTH-1:0]            branch_op;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addra;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrb;
output  [`ALUOP_WIDTH-1:0]               alu_op;
output  [`SHROTOP_WIDTH-1:0]             shrot_op;
output  [`RFWBOP_WIDTH-1:0]              rfwb_op;
output  [31:0]                           wb_insn;
output  [31:0]                           simm;
output  [31:2]                          branch_addrofs;
output  [31:0]                           lsu_addrofs;
output  [`SEL_WIDTH-1:0]         sel_a;
output  [`SEL_WIDTH-1:0]         sel_b;
output  [`LSUOP_WIDTH-1:0]               lsu_op;
output  [`COMPOP_WIDTH-1:0]              comp_op;
output  [`MULTICYCLE_WIDTH-1:0]          multicycle;
output  [15:0]                           spr_addrimm;
input                                   wbforw_valid;
output                                  sig_syscall;
output                                  force_dslot_fetch;
output                                  id_macrc_op;
output                                  ex_macrc_op;
 
//
// Internal wires and regs
//
reg     [`BRANCHOP_WIDTH-1:0]            pre_branch_op;
reg     [`BRANCHOP_WIDTH-1:0]            branch_op;
reg     [`ALUOP_WIDTH-1:0]               alu_op;
reg     [`SHROTOP_WIDTH-1:0]             shrot_op;
reg     [31:0]                           id_insn;
reg     [31:0]                           ex_insn;
reg     [31:0]                           wb_insn;
reg     [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
reg     [`REGFILE_ADDR_WIDTH-1:0]        wb_rfaddrw;
reg     [`RFWBOP_WIDTH-1:0]              rfwb_op;
reg     [31:0]                           lsu_addrofs;
reg     [`SEL_WIDTH-1:0]         sel_a;
reg     [`SEL_WIDTH-1:0]         sel_b;
reg                                     sel_imm;
reg     [`LSUOP_WIDTH-1:0]               lsu_op;
reg     [`COMPOP_WIDTH-1:0]              comp_op;
reg     [`MULTICYCLE_WIDTH-1:0]          multicycle;
reg                                     imm_signextend;
reg     [15:0]                           spr_addrimm;
reg                                     sig_syscall;
wire                                    rst_or_except_flushpipe;
reg                                     ex_macrc_op;
 
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
 
//
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
// instructions
//
assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
 
//
// Sign/Zero extension of immediates
//
assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
 
//
// Sign extension of branch offset
//
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
 
//
// Async reset for most of pipeline flops
//
assign rst_or_except_flushpipe = rst | except_flushpipe;
 
//
// l.macrc in ID stage
//
assign id_macrc_op = (id_insn[31:26] == 6'b00_0110) & id_insn[16];
 
//
// Generation of sel_a
//
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
                sel_a = `SEL_EX_FORW;
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
                sel_a = `SEL_WB_FORW;
        else
                sel_a = `SEL_RF;
 
//
// Generation of sel_b
//
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if (sel_imm)
                sel_b = `SEL_IMM;
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
                sel_b = `SEL_EX_FORW;
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
                sel_b = `SEL_WB_FORW;
        else
                sel_b = `SEL_RF;
 
//
// l.macrc in EX stage
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                ex_macrc_op <= #1 1'b0;
        else if (!ex_freeze & id_freeze)
                ex_macrc_op <= #1 1'b0;
        else if (!ex_freeze)
                ex_macrc_op <= #1 id_macrc_op;
end
 
//
// Decode of spr_addrimm
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                spr_addrimm <= #1 16'h0000;
        else if (!ex_freeze & id_freeze)
                spr_addrimm <= #1 16'h0000;
        else if (!ex_freeze) begin
                case (id_insn[31:26])   // synopsys full_case parallel_case
                        // l.mtspr
                        `OR32_MTSPR:
                                spr_addrimm <= #1 id_insn[15:0];
                        // l.mfspr
                        default:
                                spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
                endcase
        end
end
 
//
// Decode of multicycle
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
    // l.lwz
    `OR32_LWZ:
      multicycle = `TWO_CYCLES;
 
    // l.lbz
    `OR32_LBZ:
      multicycle = `TWO_CYCLES;
 
    // l.lbs
    `OR32_LBS:
      multicycle = `TWO_CYCLES;
 
    // l.lhz
    `OR32_LHZ:
      multicycle = `TWO_CYCLES;
 
    // l.lhs
    `OR32_LHS:
      multicycle = `TWO_CYCLES;
 
    // l.sw
    `OR32_SW:
      multicycle = `TWO_CYCLES;
 
    // l.sb
    `OR32_SB:
      multicycle = `TWO_CYCLES;
 
    // l.sh
    `OR32_SH:
      multicycle = `TWO_CYCLES;
 
    // ALU instructions except the one with immediate
    `OR32_ALU:
      multicycle = id_insn[`ALUMCYC_POS];
 
    // Single cycle instructions
    default: begin
      multicycle = `ONE_CYCLE;
    end
 
  endcase
 
end
 
//
// Decode of imm_signextend
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
        // l.addi
        `OR32_ADDI:
                imm_signextend = `on;
 
        // l.addic
        `OR32_ADDIC:
                imm_signextend = `on;
 
        // l.xori
        `OR32_XORI:
                imm_signextend = `on;
 
        // l.muli
        `OR32_MULI:
                imm_signextend = `on;
 
        // l.maci
        `OR32_MACI:
                imm_signextend = `on;
 
        // SFXX insns with immediate
        `OR32_SFXXI:
                imm_signextend = `on;
 
        // Instructions with no or zero extended immediate
        default: begin
                imm_signextend = `off;
        end
 
endcase
 
end
 
//
// LSU addr offset
//
always @(lsu_op or ex_insn) begin
        lsu_addrofs[10:0] = ex_insn[10:0];
        case(lsu_op)    // synopsys parallel_case full_case
                `LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
                        lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
                default :
                        lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
        endcase
end
 
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
        if (rst)
                rf_addrw <= #1 5'd0;
        else if (!ex_freeze & id_freeze)
                rf_addrw <= #1 5'd00;
        else if (!ex_freeze)
                case (pre_branch_op)    // synopsys parallel_case full_case
                        `BRANCHOP_JR, `BRANCHOP_BAL:
                                rf_addrw <= #1 5'd09;   // link register r9
                        default:
                                rf_addrw <= #1 id_insn[25:21];
                endcase
end
 
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
        if (rst)
                wb_rfaddrw <= #1 5'd0;
        else if (!wb_freeze)
                wb_rfaddrw <= #1 rf_addrw;
end
 
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_insn[31:26] <= #1 `OR32_NOP;
                id_insn[25:0] <= #1 26'd0;
        end
        else if (!id_freeze) begin
                id_insn <= #1 if_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: id_insn <= %h", $time, if_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_insn[31:26] <= #1 `OR32_NOP;
                ex_insn[25:0] <= #1 26'd0;
        end
        else if (!ex_freeze & id_freeze)
                ex_insn <= #1 {`OR32_NOP, 26'h000_4444};
        else if (!ex_freeze) begin
                ex_insn <= #1 id_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_insn <= %h", $time, id_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_insn[31:26] <= #1 `OR32_NOP;
                wb_insn[25:0] <= #1 26'd0;
        end
        else if (!wb_freeze) begin
                wb_insn <= #1 ex_insn;
        end
end
 
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sel_imm <= #1 1'b0;
        else if (!id_freeze) begin
          case (if_insn[31:26])         // synopsys full_case parallel_case
 
            // j.jalr
            `OR32_JALR:
              sel_imm <= #1 `off;
 
            // l.jr
            `OR32_JR:
              sel_imm <= #1 `off;
 
            // l.rfe
            `OR32_RFE:
              sel_imm <= #1 `off;
 
            // l.mfspr
            `OR32_MFSPR:
              sel_imm <= #1 `off;
 
            // l.mtspr
            `OR32_MTSPR:
              sel_imm <= #1 `off;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              sel_imm <= #1 `off;
 
            // l.sw
            `OR32_SW:
              sel_imm <= #1 `off;
 
            // l.sb
            `OR32_SB:
              sel_imm <= #1 `off;
 
            // l.sh
            `OR32_SH:
              sel_imm <= #1 `off;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              sel_imm <= #1 `off;
 
            // SFXX instructions
            `OR32_SFXX:
              sel_imm <= #1 `off;
 
            // l.nop
            `OR32_NOP:
              sel_imm <= #1 `off;
 
            // All instructions with immediates
            default: begin
              sel_imm <= #1 `on;
            end
 
          endcase
 
        end
end
 
 
//
// Decode of alu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                alu_op <= #1 `ALUOP_NOP;
        else if (!ex_freeze & id_freeze)
                alu_op <= #1 `ALUOP_NOP;
        else if (!ex_freeze) begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.j
            `OR32_J:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jal
            `OR32_JAL:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jalr
            `OR32_JALR:
              alu_op <= #1 `ALUOP_OR;
 
            // l.jr
            `OR32_JR:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bnf
            `OR32_BNF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bf
            `OR32_BF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.rfe
            `OR32_RFE:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.movhi
            `OR32_MOVHI:
              alu_op <= #1 `ALUOP_MOVHI;
 
            // l.mfspr
            `OR32_MFSPR:
              alu_op <= #1 `ALUOP_MFSR;
 
            // l.mtspr
            `OR32_MTSPR:
              alu_op <= #1 `ALUOP_MTSR;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.lwz
            `OR32_LWZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbz
            `OR32_LBZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbs
            `OR32_LBS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhz
            `OR32_LHZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhs
            `OR32_LHS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addi
            `OR32_ADDI:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addic
            `OR32_ADDIC:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.andi
            `OR32_ANDI:
              alu_op <= #1 `ALUOP_AND;
 
            // l.ori
            `OR32_ORI:
              alu_op <= #1 `ALUOP_OR;
 
            // l.xori
            `OR32_XORI:
              alu_op <= #1 `ALUOP_XOR;
 
            // l.muli
            `OR32_MULI:
              alu_op <= #1 `ALUOP_MUL;
 
            // l.maci
            `OR32_MACI:
              alu_op <= #1 `ALUOP_MAC;
 
            // Shift and rotate insns with immediate
            `OR32_SH_ROTI:
              alu_op <= #1 `ALUOP_SHROT;
 
            // SFXX insns with immediate
            `OR32_SFXXI:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.sw
            `OR32_SW:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sb
            `OR32_SB:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sh
            `OR32_SH:
              alu_op <= #1 `ALUOP_ADD;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              alu_op <= #1 id_insn[3:0];
 
            // SFXX instructions
            `OR32_SFXX:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.nop
            `OR32_NOP:
              alu_op <= #1 `ALUOP_NOP;
 
            // Illegal and OR1200 unsupported instructions
            default: begin
              alu_op <= #1 `ALUOP_NOP;
`ifdef OR1200_VERBOSE
// synopsys translate_off
              $display("%t: Illegal insn.... insn %h", $time, id_insn);
// synopsys translate_on
`endif
            end
 
          endcase
 
        end
end
 
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!ex_freeze & id_freeze)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!ex_freeze) begin
                shrot_op <= #1 id_insn[`SHROTOP_POS];
        end
end
 
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!ex_freeze & id_freeze)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!ex_freeze) begin
                case (id_insn[31:26])           // synopsys full_case parallel_case
 
                  // j.jal
                  `OR32_JAL:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // j.jalr
                  `OR32_JALR:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // l.movhi
                  `OR32_MOVHI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.mfspr
                  `OR32_MFSPR:
                    rfwb_op <= #1 `RFWBOP_SPRS;
 
                  // l.lwz
                  `OR32_LWZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbz
                  `OR32_LBZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbs
                  `OR32_LBS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhz
                  `OR32_LHZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhs
                  `OR32_LHS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.addi
                  `OR32_ADDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.addic
                  `OR32_ADDIC:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.andi
                  `OR32_ANDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.ori
                  `OR32_ORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.xori
                  `OR32_XORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.muli
                  `OR32_MULI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.maci
                  `OR32_MACI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Shift and rotate insns with immediate
                  `OR32_SH_ROTI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // ALU instructions except the one with immediate
                  `OR32_ALU:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Instructions w/o register-file write-back
                  default: begin
                    rfwb_op <= #1 `RFWBOP_NOP;
                  end
 
                endcase
        end
end
 
//
// Decode of pre_branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                pre_branch_op <= #1 `BRANCHOP_NOP;
        else if (!id_freeze) begin
                case (if_insn[31:26])           // synopsys full_case parallel_case
 
                  // l.j
                  `OR32_J:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jal
                  `OR32_JAL:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jalr
                  `OR32_JALR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.jr
                  `OR32_JR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.bnf
                  `OR32_BNF:
                    pre_branch_op <= #1 `BRANCHOP_BNF;
 
                  // l.bf
                  `OR32_BF:
                    pre_branch_op <= #1 `BRANCHOP_BF;
 
                  // l.rfe
                  `OR32_RFE:
                    pre_branch_op <= #1 `BRANCHOP_RFE;
 
                  // Non branch instructions
                  default: begin
                    pre_branch_op <= #1 `BRANCHOP_NOP;
                  end
                endcase
        end
end
 
//
// Generation of branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!ex_freeze & id_freeze)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!ex_freeze) begin
                branch_op <= #1 pre_branch_op;
        end
end
 
//
// Decode of lsu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!ex_freeze & id_freeze)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!ex_freeze)  begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.lwz
            `OR32_LWZ:
              lsu_op <= #1 `LSUOP_LWZ;
 
            // l.lbz
            `OR32_LBZ:
              lsu_op <= #1 `LSUOP_LBZ;
 
            // l.lbs
            `OR32_LBS:
              lsu_op <= #1 `LSUOP_LBS;
 
            // l.lhz
            `OR32_LHZ:
              lsu_op <= #1 `LSUOP_LHZ;
 
            // l.lhs
            `OR32_LHS:
              lsu_op <= #1 `LSUOP_LHS;
 
            // l.sw
            `OR32_SW:
              lsu_op <= #1 `LSUOP_SW;
 
            // l.sb
            `OR32_SB:
              lsu_op <= #1 `LSUOP_SB;
 
            // l.sh
            `OR32_SH:
              lsu_op <= #1 `LSUOP_SH;
 
            // Non load/store instructions
            default: begin
              lsu_op <= #1 `LSUOP_NOP;
            end
          endcase
        end
end
 
//
// Decode of comp_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                comp_op <= #1 4'd0;
        else if (!ex_freeze & id_freeze)
                comp_op <= #1 4'd0;
        else if (!ex_freeze) begin
                comp_op <= #1 id_insn[24:21];
        end
end
 
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_syscall <= #1 1'b0;
        else if (!wb_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                if (wb_insn[31:24] == {`OR32_XSYNC, 2'b00})
                        $display("Generating sig_syscall");
// synopsys translate_on
`endif
//              sig_syscall <= #1 (wb_insn[31:24] == {`OR32_XSYNC, 2'b00});
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	168	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction decode ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Majority of instruction decoding is performed here. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.2 2001/08/13 03:36:20 lampret`
48			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
49			`//`
50	170	lampret	`// Revision 1.1 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52	168	lampret	`//`
53	170	lampret	`//`
54	168	lampret
55			`include "timescale.v"
56			`include "defines.v"
57
58			`module id(`
59			`// Clock and reset`
60			`clk, rst,`
61
62			`// Internal i/f`
63	205	lampret	`id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,`
64	168	lampret	`rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,`
65			`wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,`
66	203	lampret	`multicycle, spr_addrimm, wbforw_valid, sig_syscall,`
67	209	lampret	`force_dslot_fetch, id_macrc_op, ex_macrc_op`
68	168	lampret	`);`
69
70			`//`
71			`// I/O`
72			`//`
73			`input clk;`
74			`input rst;`
75	205	lampret	`input id_freeze;`
76			`input ex_freeze;`
77			`input wb_freeze;`
78	168	lampret	`input except_flushpipe;`
79			`input [31:0] if_insn;`
80			output [`BRANCHOP_WIDTH-1:0] branch_op;
81			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
82			output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
83			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrb;
84			output [`ALUOP_WIDTH-1:0] alu_op;
85			output [`SHROTOP_WIDTH-1:0] shrot_op;
86			output [`RFWBOP_WIDTH-1:0] rfwb_op;
87			`output [31:0] wb_insn;`
88			`output [31:0] simm;`
89			`output [31:2] branch_addrofs;`
90			`output [31:0] lsu_addrofs;`
91			output [`SEL_WIDTH-1:0] sel_a;
92			output [`SEL_WIDTH-1:0] sel_b;
93			output [`LSUOP_WIDTH-1:0] lsu_op;
94			output [`COMPOP_WIDTH-1:0] comp_op;
95			output [`MULTICYCLE_WIDTH-1:0] multicycle;
96			`output [15:0] spr_addrimm;`
97			`input wbforw_valid;`
98			`output sig_syscall;`
99	203	lampret	`output force_dslot_fetch;`
100	209	lampret	`output id_macrc_op;`
101			`output ex_macrc_op;`
102	168	lampret
103			`//`
104			`// Internal wires and regs`
105			`//`
106			reg [`BRANCHOP_WIDTH-1:0] pre_branch_op;
107			reg [`BRANCHOP_WIDTH-1:0] branch_op;
108			reg [`ALUOP_WIDTH-1:0] alu_op;
109			reg [`SHROTOP_WIDTH-1:0] shrot_op;
110			`reg [31:0] id_insn;`
111			`reg [31:0] ex_insn;`
112			`reg [31:0] wb_insn;`
113			reg [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
114			reg [`REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
115			reg [`RFWBOP_WIDTH-1:0] rfwb_op;
116			`reg [31:0] lsu_addrofs;`
117			reg [`SEL_WIDTH-1:0] sel_a;
118			reg [`SEL_WIDTH-1:0] sel_b;
119			`reg sel_imm;`
120			reg [`LSUOP_WIDTH-1:0] lsu_op;
121			reg [`COMPOP_WIDTH-1:0] comp_op;
122			reg [`MULTICYCLE_WIDTH-1:0] multicycle;
123			`reg imm_signextend;`
124			`reg [15:0] spr_addrimm;`
125			`reg sig_syscall;`
126			`wire rst_or_except_flushpipe;`
127	209	lampret	`reg ex_macrc_op;`
128	168	lampret
129			`//`
130			`// Register file read addresses`
131			`//`
132			`assign rf_addra = if_insn[20:16];`
133			`assign rf_addrb = if_insn[15:11];`
134
135			`//`
136	203	lampret	`// Force fetch of delay slot instruction when jump/branch is preceeded by load/store`
137			`// instructions`
138			`//`
139	209	lampret	`assign force_dslot_fetch = ((\|pre_branch_op) & (\|lsu_op));`
140	203	lampret
141			`//`
142	168	lampret	`// Sign/Zero extension of immediates`
143			`//`
144			assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
145
146			`//`
147			`// Sign extension of branch offset`
148			`//`
149			`assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};`
150
151			`//`
152			`// Async reset for most of pipeline flops`
153			`//`
154			`assign rst_or_except_flushpipe = rst \| except_flushpipe;`
155
156			`//`
157	209	lampret	`// l.macrc in ID stage`
158			`//`
159			`assign id_macrc_op = (id_insn[31:26] == 6'b00_0110) & id_insn[16];`
160
161			`//`
162	168	lampret	`// Generation of sel_a`
163			`//`
164	209	lampret	`always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
165	168	lampret	`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`
166	209	lampret	sel_a = `SEL_EX_FORW;
167	168	lampret	`else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)`
168	209	lampret	sel_a = `SEL_WB_FORW;
169	168	lampret	`else`
170	209	lampret	sel_a = `SEL_RF;
171	168	lampret
172			`//`
173			`// Generation of sel_b`
174			`//`
175	209	lampret	`always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
176	168	lampret	`if (sel_imm)`
177	209	lampret	sel_b = `SEL_IMM;
178	168	lampret	`else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])`
179	209	lampret	sel_b = `SEL_EX_FORW;
180	168	lampret	`else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)`
181	209	lampret	sel_b = `SEL_WB_FORW;
182	168	lampret	`else`
183	209	lampret	sel_b = `SEL_RF;
184	168	lampret
185			`//`
186	209	lampret	`// l.macrc in EX stage`
187			`//`
188			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
189			`if (rst_or_except_flushpipe)`
190			`ex_macrc_op <= #1 1'b0;`
191			`else if (!ex_freeze & id_freeze)`
192			`ex_macrc_op <= #1 1'b0;`
193			`else if (!ex_freeze)`
194			`ex_macrc_op <= #1 id_macrc_op;`
195			`end`
196
197			`//`
198	168	lampret	`// Decode of spr_addrimm`
199			`//`
200			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
201			`if (rst_or_except_flushpipe)`
202			`spr_addrimm <= #1 16'h0000;`
203	205	lampret	`else if (!ex_freeze & id_freeze)`
204			`spr_addrimm <= #1 16'h0000;`
205			`else if (!ex_freeze) begin`
206	168	lampret	`case (id_insn[31:26]) // synopsys full_case parallel_case`
207			`// l.mtspr`
208			`OR32_MTSPR:
209			`spr_addrimm <= #1 id_insn[15:0];`
210			`// l.mfspr`
211			`default:`
212			`spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};`
213			`endcase`
214			`end`
215			`end`
216
217			`//`
218			`// Decode of multicycle`
219			`//`
220			`always @(id_insn) begin`
221			`case (id_insn[31:26]) // synopsys full_case parallel_case`
222
223			`// l.lwz`
224			`OR32_LWZ:
225	209	lampret	multicycle = `TWO_CYCLES;
226	168	lampret
227			`// l.lbz`
228			`OR32_LBZ:
229	209	lampret	multicycle = `TWO_CYCLES;
230	168	lampret
231			`// l.lbs`
232			`OR32_LBS:
233	209	lampret	multicycle = `TWO_CYCLES;
234	168	lampret
235			`// l.lhz`
236			`OR32_LHZ:
237	209	lampret	multicycle = `TWO_CYCLES;
238	168	lampret
239			`// l.lhs`
240			`OR32_LHS:
241	209	lampret	multicycle = `TWO_CYCLES;
242	168	lampret
243			`// l.sw`
244			`OR32_SW:
245	209	lampret	multicycle = `TWO_CYCLES;
246	168	lampret
247			`// l.sb`
248			`OR32_SB:
249	209	lampret	multicycle = `TWO_CYCLES;
250	168	lampret
251			`// l.sh`
252			`OR32_SH:
253	209	lampret	multicycle = `TWO_CYCLES;
254	168	lampret
255			`// ALU instructions except the one with immediate`
256			`OR32_ALU:
257	209	lampret	multicycle = id_insn[`ALUMCYC_POS];
258	168	lampret
259			`// Single cycle instructions`
260			`default: begin`
261	209	lampret	multicycle = `ONE_CYCLE;
262	168	lampret	`end`
263
264			`endcase`
265
266			`end`
267
268			`//`
269			`// Decode of imm_signextend`
270			`//`
271			`always @(id_insn) begin`
272			`case (id_insn[31:26]) // synopsys full_case parallel_case`
273
274			`// l.addi`
275			`OR32_ADDI:
276	209	lampret	imm_signextend = `on;
277	168	lampret
278			`// l.addic`
279			`OR32_ADDIC:
280	209	lampret	imm_signextend = `on;
281	168	lampret
282			`// l.xori`
283			`OR32_XORI:
284	209	lampret	imm_signextend = `on;
285	168	lampret
286			`// l.muli`
287			`OR32_MULI:
288	209	lampret	imm_signextend = `on;
289	168	lampret
290			`// l.maci`
291			`OR32_MACI:
292	209	lampret	imm_signextend = `on;
293	168	lampret
294			`// SFXX insns with immediate`
295			`OR32_SFXXI:
296	209	lampret	imm_signextend = `on;
297	168	lampret
298			`// Instructions with no or zero extended immediate`
299			`default: begin`
300	209	lampret	imm_signextend = `off;
301	168	lampret	`end`
302
303			`endcase`
304
305			`end`
306
307			`//`
308			`// LSU addr offset`
309			`//`
310			`always @(lsu_op or ex_insn) begin`
311	209	lampret	`lsu_addrofs[10:0] = ex_insn[10:0];`
312	168	lampret	`case(lsu_op) // synopsys parallel_case full_case`
313			`LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
314	209	lampret	`lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};`
315	168	lampret	`default :`
316	209	lampret	`lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};`
317	168	lampret	`endcase`
318			`end`
319
320			`//`
321			`// Register file write address`
322			`//`
323			`always @(posedge clk or posedge rst) begin`
324			`if (rst)`
325			`rf_addrw <= #1 5'd0;`
326	205	lampret	`else if (!ex_freeze & id_freeze)`
327			`rf_addrw <= #1 5'd00;`
328			`else if (!ex_freeze)`
329	168	lampret	`case (pre_branch_op) // synopsys parallel_case full_case`
330			`BRANCHOP_JR, `BRANCHOP_BAL:
331			`rf_addrw <= #1 5'd09; // link register r9`
332			`default:`
333			`rf_addrw <= #1 id_insn[25:21];`
334			`endcase`
335			`end`
336
337			`//`
338			`// rf_addrw in wb stage (used in forwarding logic)`
339			`//`
340			`always @(posedge clk or posedge rst) begin`
341			`if (rst)`
342			`wb_rfaddrw <= #1 5'd0;`
343	205	lampret	`else if (!wb_freeze)`
344	168	lampret	`wb_rfaddrw <= #1 rf_addrw;`
345			`end`
346
347			`//`
348			`// Instruction latch in id_insn`
349			`//`
350			`always @(posedge clk or posedge rst) begin`
351			`if (rst) begin`
352			id_insn[31:26] <= #1 `OR32_NOP;
353			`id_insn[25:0] <= #1 26'd0;`
354			`end`
355	205	lampret	`else if (!id_freeze) begin`
356	168	lampret	`id_insn <= #1 if_insn;`
357	203	lampret	`ifdef OR1200_VERBOSE
358			`// synopsys translate_off`
359	168	lampret	`$display("%t: id_insn <= %h", $time, if_insn);`
360	203	lampret	`// synopsys translate_on`
361			`endif
362	168	lampret	`end`
363			`end`
364
365			`//`
366			`// Instruction latch in ex_insn`
367			`//`
368			`always @(posedge clk or posedge rst) begin`
369			`if (rst) begin`
370			ex_insn[31:26] <= #1 `OR32_NOP;
371			`ex_insn[25:0] <= #1 26'd0;`
372			`end`
373	205	lampret	`else if (!ex_freeze & id_freeze)`
374			ex_insn <= #1 {`OR32_NOP, 26'h000_4444};
375			`else if (!ex_freeze) begin`
376	168	lampret	`ex_insn <= #1 id_insn;`
377	203	lampret	`ifdef OR1200_VERBOSE
378			`// synopsys translate_off`
379	168	lampret	`$display("%t: ex_insn <= %h", $time, id_insn);`
380	203	lampret	`// synopsys translate_on`
381			`endif
382	168	lampret	`end`
383			`end`
384
385			`//`
386			`// Instruction latch in wb_insn`
387			`//`
388			`always @(posedge clk or posedge rst) begin`
389			`if (rst) begin`
390			wb_insn[31:26] <= #1 `OR32_NOP;
391			`wb_insn[25:0] <= #1 26'd0;`
392			`end`
393	205	lampret	`else if (!wb_freeze) begin`
394	168	lampret	`wb_insn <= #1 ex_insn;`
395			`end`
396			`end`
397
398			`//`
399			`// Decode of sel_imm`
400			`//`
401			`always @(posedge clk or posedge rst) begin`
402			`if (rst)`
403			`sel_imm <= #1 1'b0;`
404	205	lampret	`else if (!id_freeze) begin`
405	168	lampret	`case (if_insn[31:26]) // synopsys full_case parallel_case`
406
407			`// j.jalr`
408			`OR32_JALR:
409			sel_imm <= #1 `off;
410
411			`// l.jr`
412			`OR32_JR:
413			sel_imm <= #1 `off;
414
415			`// l.rfe`
416			`OR32_RFE:
417			sel_imm <= #1 `off;
418
419			`// l.mfspr`
420			`OR32_MFSPR:
421			sel_imm <= #1 `off;
422
423			`// l.mtspr`
424			`OR32_MTSPR:
425			sel_imm <= #1 `off;
426
427			`// l.sys, l.brk and all three sync insns`
428			`OR32_XSYNC:
429			sel_imm <= #1 `off;
430
431			`// l.sw`
432			`OR32_SW:
433			sel_imm <= #1 `off;
434
435			`// l.sb`
436			`OR32_SB:
437			sel_imm <= #1 `off;
438
439			`// l.sh`
440			`OR32_SH:
441			sel_imm <= #1 `off;
442
443			`// ALU instructions except the one with immediate`
444			`OR32_ALU:
445			sel_imm <= #1 `off;
446
447			`// SFXX instructions`
448			`OR32_SFXX:
449			sel_imm <= #1 `off;
450
451			`// l.nop`
452			`OR32_NOP:
453			sel_imm <= #1 `off;
454
455			`// All instructions with immediates`
456			`default: begin`
457			sel_imm <= #1 `on;
458			`end`
459
460			`endcase`
461
462			`end`
463			`end`
464
465
466			`//`
467			`// Decode of alu_op`
468			`//`
469			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
470			`if (rst_or_except_flushpipe)`
471			alu_op <= #1 `ALUOP_NOP;
472	205	lampret	`else if (!ex_freeze & id_freeze)`
473			alu_op <= #1 `ALUOP_NOP;
474			`else if (!ex_freeze) begin`
475	168	lampret	`case (id_insn[31:26]) // synopsys full_case parallel_case`
476
477			`// l.j`
478			`OR32_J:
479			alu_op <= #1 `ALUOP_IMM;
480
481			`// j.jal`
482			`OR32_JAL:
483			alu_op <= #1 `ALUOP_IMM;
484
485			`// j.jalr`
486			`OR32_JALR:
487			alu_op <= #1 `ALUOP_OR;
488
489			`// l.jr`
490			`OR32_JR:
491			alu_op <= #1 `ALUOP_ADD;
492
493			`// l.bnf`
494			`OR32_BNF:
495			alu_op <= #1 `ALUOP_ADD;
496
497			`// l.bf`
498			`OR32_BF:
499			alu_op <= #1 `ALUOP_ADD;
500

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