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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction decode                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Majority of instruction decoding is performed here.         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module id(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,
        rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
        wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
        multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
        force_dslot_fetch, id_macrc_op, ex_macrc_op
);
 
//
// I/O
//
input                                   clk;
input                                   rst;
input                                   id_freeze;
input                                   ex_freeze;
input                                   wb_freeze;
input                                   except_flushpipe;
input   [31:0]                           if_insn;
output  [`BRANCHOP_WIDTH-1:0]            branch_op;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addra;
output  [`REGFILE_ADDR_WIDTH-1:0]        rf_addrb;
output  [`ALUOP_WIDTH-1:0]               alu_op;
output  [`SHROTOP_WIDTH-1:0]             shrot_op;
output  [`RFWBOP_WIDTH-1:0]              rfwb_op;
output  [31:0]                           wb_insn;
output  [31:0]                           simm;
output  [31:2]                          branch_addrofs;
output  [31:0]                           lsu_addrofs;
output  [`SEL_WIDTH-1:0]         sel_a;
output  [`SEL_WIDTH-1:0]         sel_b;
output  [`LSUOP_WIDTH-1:0]               lsu_op;
output  [`COMPOP_WIDTH-1:0]              comp_op;
output  [`MULTICYCLE_WIDTH-1:0]          multicycle;
output  [15:0]                           spr_addrimm;
input                                   wbforw_valid;
output                                  sig_syscall;
output                                  sig_trap;
output                                  force_dslot_fetch;
output                                  id_macrc_op;
output                                  ex_macrc_op;
 
//
// Internal wires and regs
//
reg     [`BRANCHOP_WIDTH-1:0]            pre_branch_op;
reg     [`BRANCHOP_WIDTH-1:0]            branch_op;
reg     [`ALUOP_WIDTH-1:0]               alu_op;
reg     [`SHROTOP_WIDTH-1:0]             shrot_op;
reg     [31:0]                           id_insn;
reg     [31:0]                           ex_insn;
reg     [31:0]                           wb_insn;
reg     [`REGFILE_ADDR_WIDTH-1:0]        rf_addrw;
reg     [`REGFILE_ADDR_WIDTH-1:0]        wb_rfaddrw;
reg     [`RFWBOP_WIDTH-1:0]              rfwb_op;
reg     [31:0]                           lsu_addrofs;
reg     [`SEL_WIDTH-1:0]         sel_a;
reg     [`SEL_WIDTH-1:0]         sel_b;
reg                                     sel_imm;
reg     [`LSUOP_WIDTH-1:0]               lsu_op;
reg     [`COMPOP_WIDTH-1:0]              comp_op;
reg     [`MULTICYCLE_WIDTH-1:0]          multicycle;
reg                                     imm_signextend;
reg     [15:0]                           spr_addrimm;
reg                                     sig_syscall;
reg                                     sig_trap;
wire                                    rst_or_except_flushpipe;
reg                                     ex_macrc_op;
 
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
 
//
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
// instructions
//
assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
 
//
// Sign/Zero extension of immediates
//
assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
 
//
// Sign extension of branch offset
//
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
 
//
// Async reset for most of pipeline flops
//
assign rst_or_except_flushpipe = rst | except_flushpipe;
 
//
// l.macrc in ID stage
//
assign id_macrc_op = (id_insn[31:26] == 6'b00_0110) & id_insn[16];
 
//
// Generation of sel_a
//
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
                sel_a = `SEL_EX_FORW;
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
                sel_a = `SEL_WB_FORW;
        else
                sel_a = `SEL_RF;
 
//
// Generation of sel_b
//
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if (sel_imm)
                sel_b = `SEL_IMM;
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
                sel_b = `SEL_EX_FORW;
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
                sel_b = `SEL_WB_FORW;
        else
                sel_b = `SEL_RF;
 
//
// l.macrc in EX stage
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                ex_macrc_op <= #1 1'b0;
        else if (!ex_freeze & id_freeze)
                ex_macrc_op <= #1 1'b0;
        else if (!ex_freeze)
                ex_macrc_op <= #1 id_macrc_op;
end
 
//
// Decode of spr_addrimm
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                spr_addrimm <= #1 16'h0000;
        else if (!ex_freeze & id_freeze)
                spr_addrimm <= #1 16'h0000;
        else if (!ex_freeze) begin
                case (id_insn[31:26])   // synopsys full_case parallel_case
                        // l.mfspr
                        `OR32_MFSPR:
                                spr_addrimm <= #1 id_insn[15:0];
                        // l.mtspr
                        default:
                                spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
                endcase
        end
end
 
//
// Decode of multicycle
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
    // l.lwz
    `OR32_LWZ:
      multicycle = `TWO_CYCLES;
 
    // l.lbz
    `OR32_LBZ:
      multicycle = `TWO_CYCLES;
 
    // l.lbs
    `OR32_LBS:
      multicycle = `TWO_CYCLES;
 
    // l.lhz
    `OR32_LHZ:
      multicycle = `TWO_CYCLES;
 
    // l.lhs
    `OR32_LHS:
      multicycle = `TWO_CYCLES;
 
    // l.sw
    `OR32_SW:
      multicycle = `TWO_CYCLES;
 
    // l.sb
    `OR32_SB:
      multicycle = `TWO_CYCLES;
 
    // l.sh
    `OR32_SH:
      multicycle = `TWO_CYCLES;
 
    // ALU instructions except the one with immediate
    `OR32_ALU:
      multicycle = id_insn[`ALUMCYC_POS];
 
    // Single cycle instructions
    default: begin
      multicycle = `ONE_CYCLE;
    end
 
  endcase
 
end
 
//
// Decode of imm_signextend
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys full_case parallel_case
 
        // l.addi
        `OR32_ADDI:
                imm_signextend = `on;
 
        // l.addic
        `OR32_ADDIC:
                imm_signextend = `on;
 
        // l.xori
        `OR32_XORI:
                imm_signextend = `on;
 
        // l.muli
        `OR32_MULI:
                imm_signextend = `on;
 
        // l.maci
        `OR32_MACI:
                imm_signextend = `on;
 
        // SFXX insns with immediate
        `OR32_SFXXI:
                imm_signextend = `on;
 
        // Instructions with no or zero extended immediate
        default: begin
                imm_signextend = `off;
        end
 
endcase
 
end
 
//
// LSU addr offset
//
always @(lsu_op or ex_insn) begin
        lsu_addrofs[10:0] = ex_insn[10:0];
        case(lsu_op)    // synopsys parallel_case full_case
                `LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
                        lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
                default :
                        lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
        endcase
end
 
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
        if (rst)
                rf_addrw <= #1 5'd0;
        else if (!ex_freeze & id_freeze)
                rf_addrw <= #1 5'd00;
        else if (!ex_freeze)
                case (pre_branch_op)    // synopsys parallel_case full_case
                        `BRANCHOP_JR, `BRANCHOP_BAL:
                                rf_addrw <= #1 5'd09;   // link register r9
                        default:
                                rf_addrw <= #1 id_insn[25:21];
                endcase
end
 
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
        if (rst)
                wb_rfaddrw <= #1 5'd0;
        else if (!wb_freeze)
                wb_rfaddrw <= #1 rf_addrw;
end
 
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_insn[31:26] <= #1 `OR32_NOP;
                id_insn[25:0] <= #1 26'd0;
        end
        else if (!id_freeze) begin
                id_insn <= #1 if_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: id_insn <= %h", $time, if_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_insn[31:26] <= #1 `OR32_NOP;
                ex_insn[25:0] <= #1 26'd0;
        end
        else if (!ex_freeze & id_freeze)
                ex_insn <= #1 {`OR32_NOP, 26'h000_4444};
        else if (!ex_freeze) begin
                ex_insn <= #1 id_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_insn <= %h", $time, id_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_insn[31:26] <= #1 `OR32_NOP;
                wb_insn[25:0] <= #1 26'd0;
        end
        else if (!wb_freeze) begin
                wb_insn <= #1 ex_insn;
        end
end
 
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sel_imm <= #1 1'b0;
        else if (!id_freeze) begin
          case (if_insn[31:26])         // synopsys full_case parallel_case
 
            // j.jalr
            `OR32_JALR:
              sel_imm <= #1 `off;
 
            // l.jr
            `OR32_JR:
              sel_imm <= #1 `off;
 
            // l.rfe
            `OR32_RFE:
              sel_imm <= #1 `off;
 
            // l.mfspr
            `OR32_MFSPR:
              sel_imm <= #1 `off;
 
            // l.mtspr
            `OR32_MTSPR:
              sel_imm <= #1 `off;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              sel_imm <= #1 `off;
 
            // l.sw
            `OR32_SW:
              sel_imm <= #1 `off;
 
            // l.sb
            `OR32_SB:
              sel_imm <= #1 `off;
 
            // l.sh
            `OR32_SH:
              sel_imm <= #1 `off;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              sel_imm <= #1 `off;
 
            // SFXX instructions
            `OR32_SFXX:
              sel_imm <= #1 `off;
 
            // l.nop
            `OR32_NOP:
              sel_imm <= #1 `off;
 
            // All instructions with immediates
            default: begin
              sel_imm <= #1 `on;
            end
 
          endcase
 
        end
end
 
 
//
// Decode of alu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                alu_op <= #1 `ALUOP_NOP;
        else if (!ex_freeze & id_freeze)
                alu_op <= #1 `ALUOP_NOP;
        else if (!ex_freeze) begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.j
            `OR32_J:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jal
            `OR32_JAL:
              alu_op <= #1 `ALUOP_IMM;
 
            // j.jalr
            `OR32_JALR:
              alu_op <= #1 `ALUOP_OR;
 
            // l.jr
            `OR32_JR:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bnf
            `OR32_BNF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.bf
            `OR32_BF:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.rfe
            `OR32_RFE:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.movhi
            `OR32_MOVHI:
              alu_op <= #1 `ALUOP_MOVHI;
 
            // l.mfspr
            `OR32_MFSPR:
              alu_op <= #1 `ALUOP_MFSR;
 
            // l.mtspr
            `OR32_MTSPR:
              alu_op <= #1 `ALUOP_MTSR;
 
            // l.sys, l.brk and all three sync insns
            `OR32_XSYNC:
              alu_op <= #1 `ALUOP_NOP;
 
            // l.lwz
            `OR32_LWZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbz
            `OR32_LBZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lbs
            `OR32_LBS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhz
            `OR32_LHZ:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.lhs
            `OR32_LHS:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addi
            `OR32_ADDI:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.addic
            `OR32_ADDIC:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.andi
            `OR32_ANDI:
              alu_op <= #1 `ALUOP_AND;
 
            // l.ori
            `OR32_ORI:
              alu_op <= #1 `ALUOP_OR;
 
            // l.xori
            `OR32_XORI:
              alu_op <= #1 `ALUOP_XOR;
 
            // l.muli
            `OR32_MULI:
              alu_op <= #1 `ALUOP_MUL;
 
            // l.maci
            `OR32_MACI:
              alu_op <= #1 `ALUOP_MAC;
 
            // Shift and rotate insns with immediate
            `OR32_SH_ROTI:
              alu_op <= #1 `ALUOP_SHROT;
 
            // SFXX insns with immediate
            `OR32_SFXXI:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.sw
            `OR32_SW:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sb
            `OR32_SB:
              alu_op <= #1 `ALUOP_ADD;
 
            // l.sh
            `OR32_SH:
              alu_op <= #1 `ALUOP_ADD;
 
            // ALU instructions except the one with immediate
            `OR32_ALU:
              alu_op <= #1 id_insn[3:0];
 
            // SFXX instructions
            `OR32_SFXX:
              alu_op <= #1 `ALUOP_COMP;
 
            // l.nop
            `OR32_NOP:
              alu_op <= #1 `ALUOP_NOP;
 
            // Illegal and OR1200 unsupported instructions
            default: begin
              alu_op <= #1 `ALUOP_NOP;
`ifdef OR1200_VERBOSE
// synopsys translate_off
              $display("%t: Illegal insn.... insn %h", $time, id_insn);
// synopsys translate_on
`endif
            end
 
          endcase
 
        end
end
 
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!ex_freeze & id_freeze)
                shrot_op <= #1 `SHROTOP_NOP;
        else if (!ex_freeze) begin
                shrot_op <= #1 id_insn[`SHROTOP_POS];
        end
end
 
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!ex_freeze & id_freeze)
                rfwb_op <= #1 `RFWBOP_NOP;
        else  if (!ex_freeze) begin
                case (id_insn[31:26])           // synopsys full_case parallel_case
 
                  // j.jal
                  `OR32_JAL:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // j.jalr
                  `OR32_JALR:
                    rfwb_op <= #1 `RFWBOP_LR;
 
                  // l.movhi
                  `OR32_MOVHI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.mfspr
                  `OR32_MFSPR:
                    rfwb_op <= #1 `RFWBOP_SPRS;
 
                  // l.lwz
                  `OR32_LWZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbz
                  `OR32_LBZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lbs
                  `OR32_LBS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhz
                  `OR32_LHZ:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.lhs
                  `OR32_LHS:
                    rfwb_op <= #1 `RFWBOP_LSU;
 
                  // l.addi
                  `OR32_ADDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.addic
                  `OR32_ADDIC:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.andi
                  `OR32_ANDI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.ori
                  `OR32_ORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.xori
                  `OR32_XORI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.muli
                  `OR32_MULI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // l.maci
                  `OR32_MACI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Shift and rotate insns with immediate
                  `OR32_SH_ROTI:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // ALU instructions except the one with immediate
                  `OR32_ALU:
                    rfwb_op <= #1 `RFWBOP_ALU;
 
                  // Instructions w/o register-file write-back
                  default: begin
                    rfwb_op <= #1 `RFWBOP_NOP;
                  end
 
                endcase
        end
end
 
//
// Decode of pre_branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                pre_branch_op <= #1 `BRANCHOP_NOP;
        else if (!id_freeze) begin
                case (if_insn[31:26])           // synopsys full_case parallel_case
 
                  // l.j
                  `OR32_J:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jal
                  `OR32_JAL:
                    pre_branch_op <= #1 `BRANCHOP_BAL;
 
                  // j.jalr
                  `OR32_JALR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.jr
                  `OR32_JR:
                    pre_branch_op <= #1 `BRANCHOP_JR;
 
                  // l.bnf
                  `OR32_BNF:
                    pre_branch_op <= #1 `BRANCHOP_BNF;
 
                  // l.bf
                  `OR32_BF:
                    pre_branch_op <= #1 `BRANCHOP_BF;
 
                  // l.rfe
                  `OR32_RFE:
                    pre_branch_op <= #1 `BRANCHOP_RFE;
 
                  // Non branch instructions
                  default: begin
                    pre_branch_op <= #1 `BRANCHOP_NOP;
                  end
                endcase
        end
end
 
//
// Generation of branch_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!ex_freeze & id_freeze)
                branch_op <= #1 `BRANCHOP_NOP;
        else if (!ex_freeze) begin
                branch_op <= #1 pre_branch_op;
        end
end
 
//
// Decode of lsu_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!ex_freeze & id_freeze)
                lsu_op <= #1 `LSUOP_NOP;
        else if (!ex_freeze)  begin
          case (id_insn[31:26])         // synopsys full_case parallel_case
 
            // l.lwz
            `OR32_LWZ:
              lsu_op <= #1 `LSUOP_LWZ;
 
            // l.lbz
            `OR32_LBZ:
              lsu_op <= #1 `LSUOP_LBZ;
 
            // l.lbs
            `OR32_LBS:
              lsu_op <= #1 `LSUOP_LBS;
 
            // l.lhz
            `OR32_LHZ:
              lsu_op <= #1 `LSUOP_LHZ;
 
            // l.lhs
            `OR32_LHS:
              lsu_op <= #1 `LSUOP_LHS;
 
            // l.sw
            `OR32_SW:
              lsu_op <= #1 `LSUOP_SW;
 
            // l.sb
            `OR32_SB:
              lsu_op <= #1 `LSUOP_SB;
 
            // l.sh
            `OR32_SH:
              lsu_op <= #1 `LSUOP_SH;
 
            // Non load/store instructions
            default: begin
              lsu_op <= #1 `LSUOP_NOP;
            end
          endcase
        end
end
 
//
// Decode of comp_op
//
always @(posedge clk or posedge rst_or_except_flushpipe) begin
        if (rst_or_except_flushpipe)
                comp_op <= #1 4'd0;
        else if (!ex_freeze & id_freeze)
                comp_op <= #1 4'd0;
        else if (!ex_freeze) begin
                comp_op <= #1 id_insn[24:21];
        end
end
 
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_syscall <= #1 1'b0;
        else if (!ex_freeze & id_freeze)
                sig_syscall <= #1 1'b0;
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                if (id_insn[31:23] == {`OR32_XSYNC, 3'b000})
                        $display("Generating sig_syscall");
// synopsys translate_on
`endif
                sig_syscall <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b000});
        end
end
 
//
// Decode of l.trap
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_trap <= #1 1'b0;
        else if (!ex_freeze & id_freeze)
                sig_trap <= #1 1'b0;
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                if (id_insn[31:23] == {`OR32_XSYNC, 3'b010})
                        $display("Generating sig_trap");
// synopsys translate_on
`endif
                sig_trap <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b010});
        end
end
 
endmodule

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Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction decode ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Majority of instruction decoding is performed here. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.7 2001/10/14 13:12:09 lampret`
48			`// MP3 version.`
49			`//`
50			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
51			`// no message`
52			`//`
53			`// Revision 1.2 2001/08/13 03:36:20 lampret`
54			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
55			`//`
56			`// Revision 1.1 2001/08/09 13:39:33 lampret`
57			`// Major clean-up.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "defines.v"
65
66			`module id(`
67			`// Clock and reset`
68			`clk, rst,`
69
70			`// Internal i/f`
71			`id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,`
72			`rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,`
73			`wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,`
74			`multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,`
75			`force_dslot_fetch, id_macrc_op, ex_macrc_op`
76			`);`
77
78			`//`
79			`// I/O`
80			`//`
81			`input clk;`
82			`input rst;`
83			`input id_freeze;`
84			`input ex_freeze;`
85			`input wb_freeze;`
86			`input except_flushpipe;`
87			`input [31:0] if_insn;`
88			output [`BRANCHOP_WIDTH-1:0] branch_op;
89			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
90			output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
91			output [`REGFILE_ADDR_WIDTH-1:0] rf_addrb;
92			output [`ALUOP_WIDTH-1:0] alu_op;
93			output [`SHROTOP_WIDTH-1:0] shrot_op;
94			output [`RFWBOP_WIDTH-1:0] rfwb_op;
95			`output [31:0] wb_insn;`
96			`output [31:0] simm;`
97			`output [31:2] branch_addrofs;`
98			`output [31:0] lsu_addrofs;`
99			output [`SEL_WIDTH-1:0] sel_a;
100			output [`SEL_WIDTH-1:0] sel_b;
101			output [`LSUOP_WIDTH-1:0] lsu_op;
102			output [`COMPOP_WIDTH-1:0] comp_op;
103			output [`MULTICYCLE_WIDTH-1:0] multicycle;
104			`output [15:0] spr_addrimm;`
105			`input wbforw_valid;`
106			`output sig_syscall;`
107			`output sig_trap;`
108			`output force_dslot_fetch;`
109			`output id_macrc_op;`
110			`output ex_macrc_op;`
111
112			`//`
113			`// Internal wires and regs`
114			`//`
115			reg [`BRANCHOP_WIDTH-1:0] pre_branch_op;
116			reg [`BRANCHOP_WIDTH-1:0] branch_op;
117			reg [`ALUOP_WIDTH-1:0] alu_op;
118			reg [`SHROTOP_WIDTH-1:0] shrot_op;
119			`reg [31:0] id_insn;`
120			`reg [31:0] ex_insn;`
121			`reg [31:0] wb_insn;`
122			reg [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
123			reg [`REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
124			reg [`RFWBOP_WIDTH-1:0] rfwb_op;
125			`reg [31:0] lsu_addrofs;`
126			reg [`SEL_WIDTH-1:0] sel_a;
127			reg [`SEL_WIDTH-1:0] sel_b;
128			`reg sel_imm;`
129			reg [`LSUOP_WIDTH-1:0] lsu_op;
130			reg [`COMPOP_WIDTH-1:0] comp_op;
131			reg [`MULTICYCLE_WIDTH-1:0] multicycle;
132			`reg imm_signextend;`
133			`reg [15:0] spr_addrimm;`
134			`reg sig_syscall;`
135			`reg sig_trap;`
136			`wire rst_or_except_flushpipe;`
137			`reg ex_macrc_op;`
138
139			`//`
140			`// Register file read addresses`
141			`//`
142			`assign rf_addra = if_insn[20:16];`
143			`assign rf_addrb = if_insn[15:11];`
144
145			`//`
146			`// Force fetch of delay slot instruction when jump/branch is preceeded by load/store`
147			`// instructions`
148			`//`
149			`assign force_dslot_fetch = ((\|pre_branch_op) & (\|lsu_op));`
150
151			`//`
152			`// Sign/Zero extension of immediates`
153			`//`
154			assign simm = (imm_signextend == `on) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
155
156			`//`
157			`// Sign extension of branch offset`
158			`//`
159			`assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};`
160
161			`//`
162			`// Async reset for most of pipeline flops`
163			`//`
164			`assign rst_or_except_flushpipe = rst \| except_flushpipe;`
165
166			`//`
167			`// l.macrc in ID stage`
168			`//`
169			`assign id_macrc_op = (id_insn[31:26] == 6'b00_0110) & id_insn[16];`
170
171			`//`
172			`// Generation of sel_a`
173			`//`
174			`always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
175			`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`
176			sel_a = `SEL_EX_FORW;
177			`else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)`
178			sel_a = `SEL_WB_FORW;
179			`else`
180			sel_a = `SEL_RF;
181
182			`//`
183			`// Generation of sel_b`
184			`//`
185			`always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
186			`if (sel_imm)`
187			sel_b = `SEL_IMM;
188			`else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])`
189			sel_b = `SEL_EX_FORW;
190			`else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)`
191			sel_b = `SEL_WB_FORW;
192			`else`
193			sel_b = `SEL_RF;
194
195			`//`
196			`// l.macrc in EX stage`
197			`//`
198			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
199			`if (rst_or_except_flushpipe)`
200			`ex_macrc_op <= #1 1'b0;`
201			`else if (!ex_freeze & id_freeze)`
202			`ex_macrc_op <= #1 1'b0;`
203			`else if (!ex_freeze)`
204			`ex_macrc_op <= #1 id_macrc_op;`
205			`end`
206
207			`//`
208			`// Decode of spr_addrimm`
209			`//`
210			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
211			`if (rst_or_except_flushpipe)`
212			`spr_addrimm <= #1 16'h0000;`
213			`else if (!ex_freeze & id_freeze)`
214			`spr_addrimm <= #1 16'h0000;`
215			`else if (!ex_freeze) begin`
216			`case (id_insn[31:26]) // synopsys full_case parallel_case`
217			`// l.mfspr`
218			`OR32_MFSPR:
219			`spr_addrimm <= #1 id_insn[15:0];`
220			`// l.mtspr`
221			`default:`
222			`spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};`
223			`endcase`
224			`end`
225			`end`
226
227			`//`
228			`// Decode of multicycle`
229			`//`
230			`always @(id_insn) begin`
231			`case (id_insn[31:26]) // synopsys full_case parallel_case`
232
233			`// l.lwz`
234			`OR32_LWZ:
235			multicycle = `TWO_CYCLES;
236
237			`// l.lbz`
238			`OR32_LBZ:
239			multicycle = `TWO_CYCLES;
240
241			`// l.lbs`
242			`OR32_LBS:
243			multicycle = `TWO_CYCLES;
244
245			`// l.lhz`
246			`OR32_LHZ:
247			multicycle = `TWO_CYCLES;
248
249			`// l.lhs`
250			`OR32_LHS:
251			multicycle = `TWO_CYCLES;
252
253			`// l.sw`
254			`OR32_SW:
255			multicycle = `TWO_CYCLES;
256
257			`// l.sb`
258			`OR32_SB:
259			multicycle = `TWO_CYCLES;
260
261			`// l.sh`
262			`OR32_SH:
263			multicycle = `TWO_CYCLES;
264
265			`// ALU instructions except the one with immediate`
266			`OR32_ALU:
267			multicycle = id_insn[`ALUMCYC_POS];
268
269			`// Single cycle instructions`
270			`default: begin`
271			multicycle = `ONE_CYCLE;
272			`end`
273
274			`endcase`
275
276			`end`
277
278			`//`
279			`// Decode of imm_signextend`
280			`//`
281			`always @(id_insn) begin`
282			`case (id_insn[31:26]) // synopsys full_case parallel_case`
283
284			`// l.addi`
285			`OR32_ADDI:
286			imm_signextend = `on;
287
288			`// l.addic`
289			`OR32_ADDIC:
290			imm_signextend = `on;
291
292			`// l.xori`
293			`OR32_XORI:
294			imm_signextend = `on;
295
296			`// l.muli`
297			`OR32_MULI:
298			imm_signextend = `on;
299
300			`// l.maci`
301			`OR32_MACI:
302			imm_signextend = `on;
303
304			`// SFXX insns with immediate`
305			`OR32_SFXXI:
306			imm_signextend = `on;
307
308			`// Instructions with no or zero extended immediate`
309			`default: begin`
310			imm_signextend = `off;
311			`end`
312
313			`endcase`
314
315			`end`
316
317			`//`
318			`// LSU addr offset`
319			`//`
320			`always @(lsu_op or ex_insn) begin`
321			`lsu_addrofs[10:0] = ex_insn[10:0];`
322			`case(lsu_op) // synopsys parallel_case full_case`
323			`LSUOP_SW, `LSUOP_SH, `LSUOP_SB :
324			`lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};`
325			`default :`
326			`lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};`
327			`endcase`
328			`end`
329
330			`//`
331			`// Register file write address`
332			`//`
333			`always @(posedge clk or posedge rst) begin`
334			`if (rst)`
335			`rf_addrw <= #1 5'd0;`
336			`else if (!ex_freeze & id_freeze)`
337			`rf_addrw <= #1 5'd00;`
338			`else if (!ex_freeze)`
339			`case (pre_branch_op) // synopsys parallel_case full_case`
340			`BRANCHOP_JR, `BRANCHOP_BAL:
341			`rf_addrw <= #1 5'd09; // link register r9`
342			`default:`
343			`rf_addrw <= #1 id_insn[25:21];`
344			`endcase`
345			`end`
346
347			`//`
348			`// rf_addrw in wb stage (used in forwarding logic)`
349			`//`
350			`always @(posedge clk or posedge rst) begin`
351			`if (rst)`
352			`wb_rfaddrw <= #1 5'd0;`
353			`else if (!wb_freeze)`
354			`wb_rfaddrw <= #1 rf_addrw;`
355			`end`
356
357			`//`
358			`// Instruction latch in id_insn`
359			`//`
360			`always @(posedge clk or posedge rst) begin`
361			`if (rst) begin`
362			id_insn[31:26] <= #1 `OR32_NOP;
363			`id_insn[25:0] <= #1 26'd0;`
364			`end`
365			`else if (!id_freeze) begin`
366			`id_insn <= #1 if_insn;`
367			`ifdef OR1200_VERBOSE
368			`// synopsys translate_off`
369			`$display("%t: id_insn <= %h", $time, if_insn);`
370			`// synopsys translate_on`
371			`endif
372			`end`
373			`end`
374
375			`//`
376			`// Instruction latch in ex_insn`
377			`//`
378			`always @(posedge clk or posedge rst) begin`
379			`if (rst) begin`
380			ex_insn[31:26] <= #1 `OR32_NOP;
381			`ex_insn[25:0] <= #1 26'd0;`
382			`end`
383			`else if (!ex_freeze & id_freeze)`
384			ex_insn <= #1 {`OR32_NOP, 26'h000_4444};
385			`else if (!ex_freeze) begin`
386			`ex_insn <= #1 id_insn;`
387			`ifdef OR1200_VERBOSE
388			`// synopsys translate_off`
389			`$display("%t: ex_insn <= %h", $time, id_insn);`
390			`// synopsys translate_on`
391			`endif
392			`end`
393			`end`
394
395			`//`
396			`// Instruction latch in wb_insn`
397			`//`
398			`always @(posedge clk or posedge rst) begin`
399			`if (rst) begin`
400			wb_insn[31:26] <= #1 `OR32_NOP;
401			`wb_insn[25:0] <= #1 26'd0;`
402			`end`
403			`else if (!wb_freeze) begin`
404			`wb_insn <= #1 ex_insn;`
405			`end`
406			`end`
407
408			`//`
409			`// Decode of sel_imm`
410			`//`
411			`always @(posedge clk or posedge rst) begin`
412			`if (rst)`
413			`sel_imm <= #1 1'b0;`
414			`else if (!id_freeze) begin`
415			`case (if_insn[31:26]) // synopsys full_case parallel_case`
416
417			`// j.jalr`
418			`OR32_JALR:
419			sel_imm <= #1 `off;
420
421			`// l.jr`
422			`OR32_JR:
423			sel_imm <= #1 `off;
424
425			`// l.rfe`
426			`OR32_RFE:
427			sel_imm <= #1 `off;
428
429			`// l.mfspr`
430			`OR32_MFSPR:
431			sel_imm <= #1 `off;
432
433			`// l.mtspr`
434			`OR32_MTSPR:
435			sel_imm <= #1 `off;
436
437			`// l.sys, l.brk and all three sync insns`
438			`OR32_XSYNC:
439			sel_imm <= #1 `off;
440
441			`// l.sw`
442			`OR32_SW:
443			sel_imm <= #1 `off;
444
445			`// l.sb`
446			`OR32_SB:
447			sel_imm <= #1 `off;
448
449			`// l.sh`
450			`OR32_SH:
451			sel_imm <= #1 `off;
452
453			`// ALU instructions except the one with immediate`
454			`OR32_ALU:
455			sel_imm <= #1 `off;
456
457			`// SFXX instructions`
458			`OR32_SFXX:
459			sel_imm <= #1 `off;
460
461			`// l.nop`
462			`OR32_NOP:
463			sel_imm <= #1 `off;
464
465			`// All instructions with immediates`
466			`default: begin`
467			sel_imm <= #1 `on;
468			`end`
469
470			`endcase`
471
472			`end`
473			`end`
474
475
476			`//`
477			`// Decode of alu_op`
478			`//`
479			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
480			`if (rst_or_except_flushpipe)`
481			alu_op <= #1 `ALUOP_NOP;
482			`else if (!ex_freeze & id_freeze)`
483			alu_op <= #1 `ALUOP_NOP;
484			`else if (!ex_freeze) begin`
485			`case (id_insn[31:26]) // synopsys full_case parallel_case`
486
487			`// l.j`
488			`OR32_J:
489			alu_op <= #1 `ALUOP_IMM;
490
491			`// j.jal`
492			`OR32_JAL:
493			alu_op <= #1 `ALUOP_IMM;
494
495			`// j.jalr`
496			`OR32_JALR:
497			alu_op <= #1 `ALUOP_OR;
498
499			`// l.jr`
500			`OR32_JR:
501			alu_op <= #1 `ALUOP_ADD;
502
503			`// l.bnf`
504			`OR32_BNF:
505			alu_op <= #1 `ALUOP_ADD;
506
507			`// l.bf`
508			`OR32_BF:
509			alu_op <= #1 `ALUOP_ADD;
510
511			`// l.rfe`
512			`OR32_RFE:
513			alu_op <= #1 `ALUOP_NOP;
514
515			`// l.movhi`
516			`OR32_MOVHI:
517			alu_op <= #1 `ALUOP_MOVHI;
518
519			`// l.mfspr`
520			`OR32_MFSPR:
521			alu_op <= #1 `ALUOP_MFSR;
522
523			`// l.mtspr`
524			`OR32_MTSPR:
525			alu_op <= #1 `ALUOP_MTSR;
526
527			`// l.sys, l.brk and all three sync insns`
528			`OR32_XSYNC:
529			alu_op <= #1 `ALUOP_NOP;
530
531			`// l.lwz`
532			`OR32_LWZ:
533			alu_op <= #1 `ALUOP_ADD;
534
535			`// l.lbz`
536			`OR32_LBZ:
537			alu_op <= #1 `ALUOP_ADD;
538
539			`// l.lbs`
540			`OR32_LBS:
541			alu_op <= #1 `ALUOP_ADD;
542
543			`// l.lhz`
544			`OR32_LHZ:
545			alu_op <= #1 `ALUOP_ADD;
546
547			`// l.lhs`
548			`OR32_LHS:
549			alu_op <= #1 `ALUOP_ADD;
550
551			`// l.addi`
552			`OR32_ADDI:
553			alu_op <= #1 `ALUOP_ADD;
554
555			`// l.addic`
556			`OR32_ADDIC:
557			alu_op <= #1 `ALUOP_ADD;
558
559			`// l.andi`
560			`OR32_ANDI:
561			alu_op <= #1 `ALUOP_AND;
562
563			`// l.ori`
564			`OR32_ORI:
565			alu_op <= #1 `ALUOP_OR;
566
567			`// l.xori`
568			`OR32_XORI:
569			alu_op <= #1 `ALUOP_XOR;
570
571			`// l.muli`
572			`OR32_MULI:
573			alu_op <= #1 `ALUOP_MUL;
574
575			`// l.maci`
576			`OR32_MACI:
577			alu_op <= #1 `ALUOP_MAC;
578
579			`// Shift and rotate insns with immediate`
580			`OR32_SH_ROTI:
581			alu_op <= #1 `ALUOP_SHROT;
582
583			`// SFXX insns with immediate`
584			`OR32_SFXXI:
585			alu_op <= #1 `ALUOP_COMP;
586
587			`// l.sw`
588			`OR32_SW:
589			alu_op <= #1 `ALUOP_ADD;
590
591			`// l.sb`
592			`OR32_SB:
593			alu_op <= #1 `ALUOP_ADD;
594
595			`// l.sh`
596			`OR32_SH:
597			alu_op <= #1 `ALUOP_ADD;
598
599			`// ALU instructions except the one with immediate`
600			`OR32_ALU:
601			`alu_op <= #1 id_insn[3:0];`
602
603			`// SFXX instructions`
604			`OR32_SFXX:
605			alu_op <= #1 `ALUOP_COMP;
606
607			`// l.nop`
608			`OR32_NOP:
609			alu_op <= #1 `ALUOP_NOP;
610
611			`// Illegal and OR1200 unsupported instructions`
612			`default: begin`
613			alu_op <= #1 `ALUOP_NOP;
614			`ifdef OR1200_VERBOSE
615			`// synopsys translate_off`
616			`$display("%t: Illegal insn.... insn %h", $time, id_insn);`
617			`// synopsys translate_on`
618			`endif
619			`end`
620
621			`endcase`
622
623			`end`
624			`end`
625
626			`//`
627			`// Decode of shrot_op`
628			`//`
629			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
630			`if (rst_or_except_flushpipe)`
631			shrot_op <= #1 `SHROTOP_NOP;
632			`else if (!ex_freeze & id_freeze)`
633			shrot_op <= #1 `SHROTOP_NOP;
634			`else if (!ex_freeze) begin`
635			shrot_op <= #1 id_insn[`SHROTOP_POS];
636			`end`
637			`end`
638
639			`//`
640			`// Decode of rfwb_op`
641			`//`
642			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
643			`if (rst_or_except_flushpipe)`
644			rfwb_op <= #1 `RFWBOP_NOP;
645			`else if (!ex_freeze & id_freeze)`
646			rfwb_op <= #1 `RFWBOP_NOP;
647			`else if (!ex_freeze) begin`
648			`case (id_insn[31:26]) // synopsys full_case parallel_case`
649
650			`// j.jal`
651			`OR32_JAL:
652			rfwb_op <= #1 `RFWBOP_LR;
653
654			`// j.jalr`
655			`OR32_JALR:
656			rfwb_op <= #1 `RFWBOP_LR;
657
658			`// l.movhi`
659			`OR32_MOVHI:
660			rfwb_op <= #1 `RFWBOP_ALU;
661
662			`// l.mfspr`
663			`OR32_MFSPR:
664			rfwb_op <= #1 `RFWBOP_SPRS;
665
666			`// l.lwz`
667			`OR32_LWZ:
668			rfwb_op <= #1 `RFWBOP_LSU;
669
670			`// l.lbz`
671			`OR32_LBZ:
672			rfwb_op <= #1 `RFWBOP_LSU;
673
674			`// l.lbs`
675			`OR32_LBS:
676			rfwb_op <= #1 `RFWBOP_LSU;
677
678			`// l.lhz`
679			`OR32_LHZ:
680			rfwb_op <= #1 `RFWBOP_LSU;
681
682			`// l.lhs`
683			`OR32_LHS:
684			rfwb_op <= #1 `RFWBOP_LSU;
685
686			`// l.addi`
687			`OR32_ADDI:
688			rfwb_op <= #1 `RFWBOP_ALU;
689
690			`// l.addic`
691			`OR32_ADDIC:
692			rfwb_op <= #1 `RFWBOP_ALU;
693
694			`// l.andi`
695			`OR32_ANDI:
696			rfwb_op <= #1 `RFWBOP_ALU;
697
698			`// l.ori`
699			`OR32_ORI:
700			rfwb_op <= #1 `RFWBOP_ALU;
701
702			`// l.xori`
703			`OR32_XORI:
704			rfwb_op <= #1 `RFWBOP_ALU;
705
706			`// l.muli`
707			`OR32_MULI:
708			rfwb_op <= #1 `RFWBOP_ALU;
709
710			`// l.maci`
711			`OR32_MACI:
712			rfwb_op <= #1 `RFWBOP_ALU;
713
714			`// Shift and rotate insns with immediate`
715			`OR32_SH_ROTI:
716			rfwb_op <= #1 `RFWBOP_ALU;
717
718			`// ALU instructions except the one with immediate`
719			`OR32_ALU:
720			rfwb_op <= #1 `RFWBOP_ALU;
721
722			`// Instructions w/o register-file write-back`
723			`default: begin`
724			rfwb_op <= #1 `RFWBOP_NOP;
725			`end`
726
727			`endcase`
728			`end`
729			`end`
730
731			`//`
732			`// Decode of pre_branch_op`
733			`//`
734			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
735			`if (rst_or_except_flushpipe)`
736			pre_branch_op <= #1 `BRANCHOP_NOP;
737			`else if (!id_freeze) begin`
738			`case (if_insn[31:26]) // synopsys full_case parallel_case`
739
740			`// l.j`
741			`OR32_J:
742			pre_branch_op <= #1 `BRANCHOP_BAL;
743
744			`// j.jal`
745			`OR32_JAL:
746			pre_branch_op <= #1 `BRANCHOP_BAL;
747
748			`// j.jalr`
749			`OR32_JALR:
750			pre_branch_op <= #1 `BRANCHOP_JR;
751
752			`// l.jr`
753			`OR32_JR:
754			pre_branch_op <= #1 `BRANCHOP_JR;
755
756			`// l.bnf`
757			`OR32_BNF:
758			pre_branch_op <= #1 `BRANCHOP_BNF;
759
760			`// l.bf`
761			`OR32_BF:
762			pre_branch_op <= #1 `BRANCHOP_BF;
763
764			`// l.rfe`
765			`OR32_RFE:
766			pre_branch_op <= #1 `BRANCHOP_RFE;
767
768			`// Non branch instructions`
769			`default: begin`
770			pre_branch_op <= #1 `BRANCHOP_NOP;
771			`end`
772			`endcase`
773			`end`
774			`end`
775
776			`//`
777			`// Generation of branch_op`
778			`//`
779			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
780			`if (rst_or_except_flushpipe)`
781			branch_op <= #1 `BRANCHOP_NOP;
782			`else if (!ex_freeze & id_freeze)`
783			branch_op <= #1 `BRANCHOP_NOP;
784			`else if (!ex_freeze) begin`
785			`branch_op <= #1 pre_branch_op;`
786			`end`
787			`end`
788
789			`//`
790			`// Decode of lsu_op`
791			`//`
792			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
793			`if (rst_or_except_flushpipe)`
794			lsu_op <= #1 `LSUOP_NOP;
795			`else if (!ex_freeze & id_freeze)`
796			lsu_op <= #1 `LSUOP_NOP;
797			`else if (!ex_freeze) begin`
798			`case (id_insn[31:26]) // synopsys full_case parallel_case`
799
800			`// l.lwz`
801			`OR32_LWZ:
802			lsu_op <= #1 `LSUOP_LWZ;
803
804			`// l.lbz`
805			`OR32_LBZ:
806			lsu_op <= #1 `LSUOP_LBZ;
807
808			`// l.lbs`
809			`OR32_LBS:
810			lsu_op <= #1 `LSUOP_LBS;
811
812			`// l.lhz`
813			`OR32_LHZ:
814			lsu_op <= #1 `LSUOP_LHZ;
815
816			`// l.lhs`
817			`OR32_LHS:
818			lsu_op <= #1 `LSUOP_LHS;
819
820			`// l.sw`
821			`OR32_SW:
822			lsu_op <= #1 `LSUOP_SW;
823
824			`// l.sb`
825			`OR32_SB:
826			lsu_op <= #1 `LSUOP_SB;
827
828			`// l.sh`
829			`OR32_SH:
830			lsu_op <= #1 `LSUOP_SH;
831
832			`// Non load/store instructions`
833			`default: begin`
834			lsu_op <= #1 `LSUOP_NOP;
835			`end`
836			`endcase`
837			`end`
838			`end`
839
840			`//`
841			`// Decode of comp_op`
842			`//`
843			`always @(posedge clk or posedge rst_or_except_flushpipe) begin`
844			`if (rst_or_except_flushpipe)`
845			`comp_op <= #1 4'd0;`
846			`else if (!ex_freeze & id_freeze)`
847			`comp_op <= #1 4'd0;`
848			`else if (!ex_freeze) begin`
849			`comp_op <= #1 id_insn[24:21];`
850			`end`
851			`end`
852
853			`//`
854			`// Decode of l.sys`
855			`//`
856			`always @(posedge clk or posedge rst) begin`
857			`if (rst)`
858			`sig_syscall <= #1 1'b0;`
859			`else if (!ex_freeze & id_freeze)`
860			`sig_syscall <= #1 1'b0;`
861			`else if (!ex_freeze) begin`
862			`ifdef OR1200_VERBOSE
863			`// synopsys translate_off`
864			if (id_insn[31:23] == {`OR32_XSYNC, 3'b000})
865			`$display("Generating sig_syscall");`
866			`// synopsys translate_on`
867			`endif
868			sig_syscall <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b000});
869			`end`
870			`end`
871
872			`//`
873			`// Decode of l.trap`
874			`//`
875			`always @(posedge clk or posedge rst) begin`
876			`if (rst)`
877			`sig_trap <= #1 1'b0;`
878			`else if (!ex_freeze & id_freeze)`
879			`sig_trap <= #1 1'b0;`
880			`else if (!ex_freeze) begin`
881			`ifdef OR1200_VERBOSE
882			`// synopsys translate_off`
883			if (id_insn[31:23] == {`OR32_XSYNC, 3'b010})
884			`$display("Generating sig_trap");`
885			`// synopsys translate_on`
886			`endif
887			sig_trap <= #1 (id_insn[31:23] == {`OR32_XSYNC, 3'b010});
888			`end`
889			`end`
890
891			`endmodule`