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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's instruction fetch                                  ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  PC, instruction fetch, interface to IC.                     ////

////                                                              ////

////  To Do:                                                      ////

////   - make it smaller and faster                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`include "timescale.v"

`include "defines.v"

module ifetch(

        // Clock and reset

        clk, rst,

        // External i/f to IC

        ic_insn, ic_pcaddr, ic_stall, tp_insn, tp_wr_insn,

        // Internal i/f

        pipeline_freeze, if_insn, if_pc, branch_op, except_type,

        branch_addrofs, lr_restor, flag, taken, binsn_addr, except_start,

        epcr

);

//

// I/O

//

//

// Clock and reset

//

input                           clk;

input                           rst;

//

// External i/f to IC

//

input   [31:0]                   ic_insn;

output  [31:0]                   ic_pcaddr;

input                           ic_stall;

input   [31:0]                   tp_insn;

input                           tp_wr_insn;

//

// Internal i/f

//

input                           pipeline_freeze;

output  [31:0]                   if_insn;

output  [31:0]                   if_pc;

input   [`BRANCHOP_WIDTH-1:0]    branch_op;

input   [`EXCEPT_WIDTH-1:0]      except_type;

input   [31:2]                  branch_addrofs;

input   [31:0]                   lr_restor;

input                           flag;

input   [31:2]                  binsn_addr;

output                          taken;

input                           except_start;

input   [31:0]                   epcr;

//

// Internal wires and regs

//

reg     [31:2]                  pcreg;

reg     [32:0]                   if_saved;

reg     [31:0]                   ic_pcaddr;

reg                             taken;  /* Set to in case of jump or taken branch */

// Selection between insn from IC or Trace port

wire [31:0] ic_tp_insn = (tp_wr_insn) ? tp_insn : ic_insn;

//

// Current registered PC (corresponds to fetched instruction)

//

assign if_pc = {pcreg[31:2], 2'b0};

//

// Just fetched instruction

//

assign if_insn = (if_saved[32]) ? if_saved[31:0] : ((taken || ic_stall) ? 32'h1500FFFF : ic_tp_insn);

//

// Async calculation of new PC value. This value is used for addressing the IC.

//

always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type

        or except_start or lr_restor or epcr) begin

        casex ({except_start, branch_op})       // synopsys parallel_case

                {1'b0, `BRANCHOP_NOP}: begin

                        ic_pcaddr <= #1 {pcreg + 'd1, 2'b0};

                        taken <= #1 1'b0;

                end

                {1'b0, `BRANCHOP_J}: begin

                        $display("%t: BRANCHOP_J: ic_pcaddr <= branch_addrofs %h", $time, branch_addrofs);

                        ic_pcaddr <= #1 {branch_addrofs, 2'b0};

                        taken <= #1 1'b1;

                end

                {1'b0, `BRANCHOP_JR}: begin

                        $display("%t: BRANCHOP_JR: ic_pcaddr <= lr_restor %h", $time, lr_restor);

                        ic_pcaddr <= #1 lr_restor;

                        taken <= #1 1'b1;

                end

                {1'b0, `BRANCHOP_BAL}: begin

                        $display("%t: BRANCHOP_BAL: ic_pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);

                        ic_pcaddr <= #1 {binsn_addr + branch_addrofs, 2'b0};

                        taken <= #1 1'b1;

                end

                {1'b0, `BRANCHOP_BF}:

                        if (flag) begin

                                $display("%t: BRANCHOP_BF: ic_pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);

                                ic_pcaddr <= #1 {binsn_addr + branch_addrofs, 2'b0};

                                taken <= #1 1'b1;

                        end

                        else begin

                                $display("%t: BRANCHOP_BF: not taken", $time);

                                ic_pcaddr <= #1 {pcreg + 'd1, 2'b0};

                                taken <= #1 1'b0;

                        end

                {1'b0, `BRANCHOP_BNF}:

                        if (flag) begin

                                ic_pcaddr <= #1 {pcreg + 'd1, 2'b0};

                                $display("%t: BRANCHOP_BNF: not taken", $time);

                                taken <= #1 1'b0;

                        end

                        else begin

                                $display("%t: BRANCHOP_BNF: ic_pcaddr %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);

                                ic_pcaddr <= #1 {binsn_addr + branch_addrofs, 2'b0};

                                taken <= #1 1'b1;

                        end

                {1'b0, `BRANCHOP_RFE}: begin

                        $display("%t: BRANCHOP_RFE: ic_pcaddr <= epcr %h", $time, epcr);

                        ic_pcaddr <= #1 epcr;

                        taken <= #1 1'b1;

                end

                default: begin

// synopsys translate_off

                        $display("Starting exception: %h.", except_type);

// synopsys translate_on

                        ic_pcaddr <= #1 { 21'h0, except_type, 8'h00};

                        taken <= #1 1'b1;

                end

        endcase

end

//

// PC register

//

always @(posedge clk or posedge rst) begin

        if (rst)

                pcreg <= #1 30'd64;

        else if (!pipeline_freeze && !ic_stall) begin

                pcreg <= #1 ic_pcaddr[31:2];

                $display("%t: pcreg incremented to %h", $time, {ic_pcaddr[31:2], 2'b0});

        end

end

//

// Stores INSN when pipeline is frozen

//

always @(posedge clk or posedge rst)

        if (rst) begin

                if_saved <= #1 33'b0;

        end

        else if (pipeline_freeze && !if_saved[32] && !ic_stall && !taken) begin

                if_saved <= #1 {1'b1, ic_tp_insn};

                $display("%t: if_saved <= %h", $time, {1'b1, ic_tp_insn});

        end

        else if (!pipeline_freeze) begin

                if_saved[32] <= #1 1'b0;

                if_saved[31:0] <= #1 32'h1500eeee;

                $display("%t: if_saved[32] <= 0", $time);

        end

endmodule