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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's Insn MMU top level                                 ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Instantiation of all IMMU blocks.                           ////

////                                                              ////

////  To Do:                                                      ////

////   - make it smaller and faster                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.1  2001/08/17 08:03:35  lampret

// *** empty log message ***

//

// Revision 1.2  2001/07/22 03:31:53  lampret

// Fixed RAM's oen bug. Cache bypass under development.

//

// Revision 1.1  2001/07/20 00:46:03  lampret

// Development version of RTL. Libraries are missing.

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "defines.v"

//

// Insn MMU

//

module immu(

        // Rst and clk

        clk, rst,

        // Fetch i/f

        immu_en, supv, immufetch_vaddr, immufetch_op, immufetch_stall,

        // Except I/F

        immuexcept_miss, immuexcept_fault,

        // SPR access

        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,

        // IC i/f

        icimmu_paddr

);

parameter dw = `OPERAND_WIDTH;

parameter aw = `OPERAND_WIDTH;

//

// I/O

//

//

// Clock and reset

//

input                           clk;

input                           rst;

//

// FETCH I/F

//

input                           immu_en;

input                           supv;

input   [aw-1:0]         immufetch_vaddr;

input                           immufetch_op;

output                          immufetch_stall;

//

// Exception I/F

//

output                          immuexcept_miss;

output                          immuexcept_fault;

//

// SPR access

//

input                           spr_cs;

input                           spr_write;

input   [aw-1:0]         spr_addr;

input   [31:0]                   spr_dat_i;

output  [31:0]                   spr_dat_o;

//

// IC I/F

//

output  [aw-1:0]         icimmu_paddr;

//

// Internal wires and regs

//

wire                            itlb_spr_access;

wire    [31:13]                 itlb_ppn;

wire                            itlb_hit;

wire                            itlb_uxe;

wire                            itlb_sxe;

wire    [31:0]                   itlb_dat_o;

//

// Implemented bits inside match and translate registers

//

// itlbwYmrX: vpn 31-10  v 0

// itlbwYtrX: ppn 31-10  uxe 7  sxe 6

//

// itlb memory width:

// 19 bits for ppn

// 13 bits for vpn

// 1 bit for valid

// 2 bits for protection

`ifdef OR1200_NO_IMMU

//

// Put all outputs in inactive state

//

assign immufetch_stall = 1'b0;

assign immuexcept_miss = 1'b0;

assign immuexcept_miss = 1'b1;

output spr_dat_o = 32'h00000000;

output icimmu_paddr = immfetch_vaddr;

`else

//

// ITLB SPR access

//

// 1400 - 1600  itlbmr w0-3

// 1400 - 1480  itlbmr w0

// 1400 - 1440  itlbmr w0 [63:0]

//

// 1600 - 1800  itlbtr w0-3

// 1600 - 1680  itlbtr w0

// 1600 - 1640  itlbtr w0 [63:0]

//

assign itlb_spr_access = spr_cs & spr_addr[10];

//

// Physical address is either translated virtual address or

// simply equal when IMMU is disabled

//

assign icimmu_paddr = immu_en ? {itlb_ppn, immufetch_vaddr[12:0]} : immufetch_vaddr;

//

// Output to SPRS unit

//

assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000;

//

// IMMU stall

//

assign immufetch_stall = 1'b0;

//

// Page fault exception logic

//

assign immuexcept_fault = immu_en &&

                        (  (immufetch_op & !supv & !itlb_uxe) // Fetch in user mode not enabled

                        || (immufetch_op & supv & !itlb_sxe) ); // Fetch in supv mode not enabled

//

// TLB Miss exception logic

//

assign immuexcept_miss = immufetch_op && immu_en && !itlb_hit;

//

// Instantiation of ITLB

//

itlb itlb(

        // Rst and clk

        .clk(clk),

        .rst(rst),

        // I/F for translation

        .tlb_en(immu_en),

        .vaddr(immufetch_vaddr),

        .hit(itlb_hit),

        .ppn(itlb_ppn),

        .uxe(itlb_uxe),

        .sxe(itlb_sxe),

        // SPR access

        .spr_cs(itlb_spr_access),

        .spr_write(spr_write),

        .spr_addr(spr_addr),

        .spr_dat_i(spr_dat_i),

        .spr_dat_o(itlb_dat_o)

);

`endif

endmodule