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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Insn MMU top level                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of all IMMU blocks.                           ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/17 08:03:35  lampret
// *** empty log message ***
//
// Revision 1.2  2001/07/22 03:31:53  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Insn MMU
//
 
module immu(
        // Rst and clk
        clk, rst,
 
        // Fetch i/f
        immu_en, supv, immufetch_vaddr, immufetch_op, immufetch_stall,
 
        // Except I/F
        immuexcept_miss, immuexcept_fault,
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
        // IC i/f
        icimmu_paddr
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// FETCH I/F
//
input                           immu_en;
input                           supv;
input   [aw-1:0]         immufetch_vaddr;
input                           immufetch_op;
output                          immufetch_stall;
 
//
// Exception I/F
//
output                          immuexcept_miss;
output                          immuexcept_fault;
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [aw-1:0]         spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// IC I/F
//
output  [aw-1:0]         icimmu_paddr;
 
//
// Internal wires and regs
//
wire                            itlb_spr_access;
wire    [31:13]                 itlb_ppn;
wire                            itlb_hit;
wire                            itlb_uxe;
wire                            itlb_sxe;
wire    [31:0]                   itlb_dat_o;
 
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-10  v 0
// itlbwYtrX: ppn 31-10  uxe 7  sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
 
`ifdef OR1200_NO_IMMU
 
//
// Put all outputs in inactive state
//
assign immufetch_stall = 1'b0;
assign immuexcept_miss = 1'b0;
assign immuexcept_fault = 1'b0;
assign spr_dat_o = 32'h00000000;
assign icimmu_paddr = immufetch_vaddr;
 
`else
 
//
// ITLB SPR access
//
// 1400 - 1600  itlbmr w0-3
// 1400 - 1480  itlbmr w0
// 1400 - 1440  itlbmr w0 [63:0]
//
// 1600 - 1800  itlbtr w0-3
// 1600 - 1680  itlbtr w0
// 1600 - 1640  itlbtr w0 [63:0]
//
assign itlb_spr_access = spr_cs & spr_addr[10];
 
//
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
//
assign icimmu_paddr = immu_en ? {itlb_ppn, immufetch_vaddr[12:0]} : immufetch_vaddr;
 
//
// Output to SPRS unit
//
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000;
 
//
// IMMU stall
//
assign immufetch_stall = 1'b0;
 
//
// Page fault exception logic
//
assign immuexcept_fault = immu_en &&
                        (  (immufetch_op & !supv & !itlb_uxe) // Fetch in user mode not enabled
                        || (immufetch_op & supv & !itlb_sxe) ); // Fetch in supv mode not enabled
 
//
// TLB Miss exception logic
//
assign immuexcept_miss = immufetch_op && immu_en && !itlb_hit;
 
//
// Instantiation of ITLB
//
itlb itlb(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // I/F for translation
        .tlb_en(immu_en),
        .vaddr(immufetch_vaddr),
        .hit(itlb_hit),
        .ppn(itlb_ppn),
        .uxe(itlb_uxe),
        .sxe(itlb_sxe),
 
        // SPR access
        .spr_cs(itlb_spr_access),
        .spr_write(spr_write),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_i),
        .spr_dat_o(itlb_dat_o)
);
 
`endif
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [immu.v] - Blame information for rev 215

Line No.	Rev	Author	Line
1	215	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Insn MMU top level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of all IMMU blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.1 2001/08/17 08:03:35 lampret`
51			`// * empty log message *`
52			`//`
53			`// Revision 1.2 2001/07/22 03:31:53 lampret`
54			`// Fixed RAM's oen bug. Cache bypass under development.`
55			`//`
56			`// Revision 1.1 2001/07/20 00:46:03 lampret`
57			`// Development version of RTL. Libraries are missing.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "defines.v"
65
66			`//`
67			`// Insn MMU`
68			`//`
69
70			`module immu(`
71			`// Rst and clk`
72			`clk, rst,`
73
74			`// Fetch i/f`
75			`immu_en, supv, immufetch_vaddr, immufetch_op, immufetch_stall,`
76
77			`// Except I/F`
78			`immuexcept_miss, immuexcept_fault,`
79
80			`// SPR access`
81			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
82
83			`// IC i/f`
84			`icimmu_paddr`
85			`);`
86
87			parameter dw = `OPERAND_WIDTH;
88			parameter aw = `OPERAND_WIDTH;
89
90			`//`
91			`// I/O`
92			`//`
93
94			`//`
95			`// Clock and reset`
96			`//`
97			`input clk;`
98			`input rst;`
99
100			`//`
101			`// FETCH I/F`
102			`//`
103			`input immu_en;`
104			`input supv;`
105			`input [aw-1:0] immufetch_vaddr;`
106			`input immufetch_op;`
107			`output immufetch_stall;`
108
109			`//`
110			`// Exception I/F`
111			`//`
112			`output immuexcept_miss;`
113			`output immuexcept_fault;`
114
115			`//`
116			`// SPR access`
117			`//`
118			`input spr_cs;`
119			`input spr_write;`
120			`input [aw-1:0] spr_addr;`
121			`input [31:0] spr_dat_i;`
122			`output [31:0] spr_dat_o;`
123
124			`//`
125			`// IC I/F`
126			`//`
127			`output [aw-1:0] icimmu_paddr;`
128
129			`//`
130			`// Internal wires and regs`
131			`//`
132			`wire itlb_spr_access;`
133			`wire [31:13] itlb_ppn;`
134			`wire itlb_hit;`
135			`wire itlb_uxe;`
136			`wire itlb_sxe;`
137			`wire [31:0] itlb_dat_o;`
138
139			`//`
140			`// Implemented bits inside match and translate registers`
141			`//`
142			`// itlbwYmrX: vpn 31-10 v 0`
143			`// itlbwYtrX: ppn 31-10 uxe 7 sxe 6`
144			`//`
145			`// itlb memory width:`
146			`// 19 bits for ppn`
147			`// 13 bits for vpn`
148			`// 1 bit for valid`
149			`// 2 bits for protection`
150
151			`ifdef OR1200_NO_IMMU
152
153			`//`
154			`// Put all outputs in inactive state`
155			`//`
156			`assign immufetch_stall = 1'b0;`
157			`assign immuexcept_miss = 1'b0;`
158			`assign immuexcept_fault = 1'b0;`
159			`assign spr_dat_o = 32'h00000000;`
160			`assign icimmu_paddr = immufetch_vaddr;`
161
162			`else
163
164			`//`
165			`// ITLB SPR access`
166			`//`
167			`// 1400 - 1600 itlbmr w0-3`
168			`// 1400 - 1480 itlbmr w0`
169			`// 1400 - 1440 itlbmr w0 [63:0]`
170			`//`
171			`// 1600 - 1800 itlbtr w0-3`
172			`// 1600 - 1680 itlbtr w0`
173			`// 1600 - 1640 itlbtr w0 [63:0]`
174			`//`
175			`assign itlb_spr_access = spr_cs & spr_addr[10];`
176
177			`//`
178			`// Physical address is either translated virtual address or`
179			`// simply equal when IMMU is disabled`
180			`//`
181			`assign icimmu_paddr = immu_en ? {itlb_ppn, immufetch_vaddr[12:0]} : immufetch_vaddr;`
182
183			`//`
184			`// Output to SPRS unit`
185			`//`
186			`assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000;`
187
188			`//`
189			`// IMMU stall`
190			`//`
191			`assign immufetch_stall = 1'b0;`
192
193			`//`
194			`// Page fault exception logic`
195			`//`
196			`assign immuexcept_fault = immu_en &&`
197			`( (immufetch_op & !supv & !itlb_uxe) // Fetch in user mode not enabled`
198			`\|\| (immufetch_op & supv & !itlb_sxe) ); // Fetch in supv mode not enabled`
199
200			`//`
201			`// TLB Miss exception logic`
202			`//`
203			`assign immuexcept_miss = immufetch_op && immu_en && !itlb_hit;`
204
205			`//`
206			`// Instantiation of ITLB`
207			`//`
208			`itlb itlb(`
209			`// Rst and clk`
210			`.clk(clk),`
211			`.rst(rst),`
212
213			`// I/F for translation`
214			`.tlb_en(immu_en),`
215			`.vaddr(immufetch_vaddr),`
216			`.hit(itlb_hit),`
217			`.ppn(itlb_ppn),`
218			`.uxe(itlb_uxe),`
219			`.sxe(itlb_sxe),`
220
221			`// SPR access`
222			`.spr_cs(itlb_spr_access),`
223			`.spr_write(spr_write),`
224			`.spr_addr(spr_addr),`
225			`.spr_dat_i(spr_dat_i),`
226			`.spr_dat_o(itlb_dat_o)`
227			`);`
228
229			`endif
230
231			`endmodule`