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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Insn TLB                                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of ITLB.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Insn TLB
//
 
module itlb(
        // Rst and clk
        clk, rst,
 
        // I/F for translation
        tlb_en, vaddr, hit, ppn, uxe, sxe,
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// I/F for translation
//
input                           tlb_en;
input   [aw-1:0]         vaddr;
output                          hit;
output  [31:13]                 ppn;
output                          uxe;
output                          sxe;
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [31:19]                 vpn;
wire                            v;
wire    [5:0]                    tlb_index;
wire                            tlb_mr_en;
wire                            tlb_mr_we;
wire    [13:0]                   tlb_mr_ram_in;
wire    [13:0]                   tlb_mr_ram_out;
wire                            tlb_tr_en;
wire                            tlb_tr_we;
wire    [20:0]                   tlb_tr_ram_in;
wire    [20:0]                   tlb_tr_ram_out;
 
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19  v 0
// itlbwYtrX: ppn 31-13  uxe 7  sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
 
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[9]);
 
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[9];
 
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[9]);
 
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[9];
 
//
// Output to SPRS unit
//
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[9]) ?
                        {vpn, {18{1'b1}}, v} :
                (spr_cs & !spr_write & spr_addr[9]) ?
                        {ppn, 5'b00000, uxe, sxe, {6{1'b1}}} :
                        32'h00000000;
 
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
 
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[31:19], spr_dat_i[0]};
 
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe} = tlb_tr_ram_out;
 
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:13], spr_dat_i[7:6]};
 
//
// Generate hit
//
assign hit = (vpn == vaddr[31:19]) & v;
 
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[5:0] : vaddr[18:13];
 
//
// Instantiation of ITLB Match Registers
//
generic_spram_64x14 itlb_mr_ram(
        .clk(clk),
        .rst(rst),
        .ce(tlb_mr_en),
        .we(tlb_mr_we),
        .oe(1'b1),
        .addr(tlb_index),
        .di(tlb_mr_ram_in),
        .do(tlb_mr_ram_out)
);
 
//
// Instantiation of ITLB Translate Registers
//
generic_spram_64x21 itlb_tr_ram(
        .clk(clk),
        .rst(rst),
        .ce(tlb_tr_en),
        .we(tlb_tr_we),
        .oe(1'b1),
        .addr(tlb_index),
        .di(tlb_tr_ram_in),
        .do(tlb_tr_ram_out)
);
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [itlb.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Insn TLB ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of ITLB. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.7 2001/10/14 13:12:09 lampret`
48			`// MP3 version.`
49			`//`
50			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
51			`// no message`
52			`//`
53			`//`
54
55			`// synopsys translate_off`
56			`include "timescale.v"
57			`// synopsys translate_on`
58			`include "defines.v"
59
60			`//`
61			`// Insn TLB`
62			`//`
63
64			`module itlb(`
65			`// Rst and clk`
66			`clk, rst,`
67
68			`// I/F for translation`
69			`tlb_en, vaddr, hit, ppn, uxe, sxe,`
70
71			`// SPR access`
72			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
73			`);`
74
75			parameter dw = `OPERAND_WIDTH;
76			parameter aw = `OPERAND_WIDTH;
77
78			`//`
79			`// I/O`
80			`//`
81
82			`//`
83			`// Clock and reset`
84			`//`
85			`input clk;`
86			`input rst;`
87
88			`//`
89			`// I/F for translation`
90			`//`
91			`input tlb_en;`
92			`input [aw-1:0] vaddr;`
93			`output hit;`
94			`output [31:13] ppn;`
95			`output uxe;`
96			`output sxe;`
97
98			`//`
99			`// SPR access`
100			`//`
101			`input spr_cs;`
102			`input spr_write;`
103			`input [31:0] spr_addr;`
104			`input [31:0] spr_dat_i;`
105			`output [31:0] spr_dat_o;`
106
107			`//`
108			`// Internal wires and regs`
109			`//`
110			`wire [31:19] vpn;`
111			`wire v;`
112			`wire [5:0] tlb_index;`
113			`wire tlb_mr_en;`
114			`wire tlb_mr_we;`
115			`wire [13:0] tlb_mr_ram_in;`
116			`wire [13:0] tlb_mr_ram_out;`
117			`wire tlb_tr_en;`
118			`wire tlb_tr_we;`
119			`wire [20:0] tlb_tr_ram_in;`
120			`wire [20:0] tlb_tr_ram_out;`
121
122			`//`
123			`// Implemented bits inside match and translate registers`
124			`//`
125			`// itlbwYmrX: vpn 31-19 v 0`
126			`// itlbwYtrX: ppn 31-13 uxe 7 sxe 6`
127			`//`
128			`// itlb memory width:`
129			`// 19 bits for ppn`
130			`// 13 bits for vpn`
131			`// 1 bit for valid`
132			`// 2 bits for protection`
133
134			`//`
135			`// Enable for Match registers`
136			`//`
137			`assign tlb_mr_en = tlb_en \| (spr_cs & !spr_addr[9]);`
138
139			`//`
140			`// Write enable for Match registers`
141			`//`
142			`assign tlb_mr_we = spr_cs & spr_write & !spr_addr[9];`
143
144			`//`
145			`// Enable for Translate registers`
146			`//`
147			`assign tlb_tr_en = tlb_en \| (spr_cs & spr_addr[9]);`
148
149			`//`
150			`// Write enable for Translate registers`
151			`//`
152			`assign tlb_tr_we = spr_cs & spr_write & spr_addr[9];`
153
154			`//`
155			`// Output to SPRS unit`
156			`//`
157			`assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[9]) ?`
158			`{vpn, {18{1'b1}}, v} :`
159			`(spr_cs & !spr_write & spr_addr[9]) ?`
160			`{ppn, 5'b00000, uxe, sxe, {6{1'b1}}} :`
161			`32'h00000000;`
162
163			`//`
164			`// Assign outputs from Match registers`
165			`//`
166			`assign {vpn, v} = tlb_mr_ram_out;`
167
168			`//`
169			`// Assign to Match registers inputs`
170			`//`
171			`assign tlb_mr_ram_in = {spr_dat_i[31:19], spr_dat_i[0]};`
172
173			`//`
174			`// Assign outputs from Translate registers`
175			`//`
176			`assign {ppn, uxe, sxe} = tlb_tr_ram_out;`
177
178			`//`
179			`// Assign to Translate registers inputs`
180			`//`
181			`assign tlb_tr_ram_in = {spr_dat_i[31:13], spr_dat_i[7:6]};`
182
183			`//`
184			`// Generate hit`
185			`//`
186			`assign hit = (vpn == vaddr[31:19]) & v;`
187
188			`//`
189			`// TLB index is normally vaddr[18:13]. If it is SPR access then index is`
190			`// spr_addr[5:0].`
191			`//`
192			`assign tlb_index = spr_cs ? spr_addr[5:0] : vaddr[18:13];`
193
194			`//`
195			`// Instantiation of ITLB Match Registers`
196			`//`
197			`generic_spram_64x14 itlb_mr_ram(`
198			`.clk(clk),`
199			`.rst(rst),`
200			`.ce(tlb_mr_en),`
201			`.we(tlb_mr_we),`
202			`.oe(1'b1),`
203			`.addr(tlb_index),`
204			`.di(tlb_mr_ram_in),`
205			`.do(tlb_mr_ram_out)`
206			`);`
207
208			`//`
209			`// Instantiation of ITLB Translate Registers`
210			`//`
211			`generic_spram_64x21 itlb_tr_ram(`
212			`.clk(clk),`
213			`.rst(rst),`
214			`.ce(tlb_tr_en),`
215			`.we(tlb_tr_we),`
216			`.oe(1'b1),`
217			`.addr(tlb_index),`
218			`.di(tlb_tr_ram_in),`
219			`.do(tlb_tr_ram_out)`
220			`);`
221
222			`endmodule`