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lampret |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's Load/Store unit ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Interface between CPU and DC. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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`include "general.h"
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module lsu(clk, rst, addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall,
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dc_stall, dc_addr, dc_datain, dc_dataout, dc_lsuop);
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parameter dw = `OPERAND_WIDTH;
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parameter aw = `REGFILE_ADDR_WIDTH;
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input clk;
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input rst;
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input [31:0] addrbase;
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input [31:0] addrofs;
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input [`LSUOP_WIDTH-1:0] lsu_op;
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input [dw-1:0] lsu_datain;
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output [dw-1:0] lsu_dataout;
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output lsu_stall;
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input dc_stall;
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output [31:0] dc_addr;
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input [dw-1:0] dc_datain;
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output [dw-1:0] dc_dataout;
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output [`LSUOP_WIDTH-1:0] dc_lsuop;
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assign dc_addr = addrbase + addrofs;
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assign dc_dataout = lsu_datain;
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assign lsu_dataout = dc_datain;
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assign lsu_stall = dc_stall;
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assign dc_lsuop = lsu_op;
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endmodule
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