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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [lsu.v] - Blame information for rev 1778

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1 218 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Load/Store unit                                    ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Interface between CPU and DC.                               ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.7  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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module lsu(
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        // Clock and reset
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        clk, rst,
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        // Internal i/f
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        addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall,
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        // External i/f to DC
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        dc_stall, dc_addr, dc_datain, dc_dataout, dc_lsuop
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);
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parameter dw = `OPERAND_WIDTH;
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parameter aw = `REGFILE_ADDR_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input                           clk;
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input                           rst;
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//
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// Internal i/f
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//
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input   [31:0]                   addrbase;
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input   [31:0]                   addrofs;
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input   [`LSUOP_WIDTH-1:0]       lsu_op;
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input   [dw-1:0]         lsu_datain;
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output  [dw-1:0]         lsu_dataout;
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output                          lsu_stall;
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//
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// External i/f to DC
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//
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input                           dc_stall;
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output  [31:0]                   dc_addr;
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input   [dw-1:0]         dc_datain;
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output  [dw-1:0]         dc_dataout;
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output  [`LSUOP_WIDTH-1:0]       dc_lsuop;
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//
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// Not much of a LSU right now
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//
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assign dc_addr = addrbase + addrofs;
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assign dc_dataout = lsu_datain;
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assign lsu_dataout = dc_datain;
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assign lsu_stall = dc_stall;
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assign dc_lsuop = lsu_op;
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endmodule

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