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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Load/Store unit                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Interface between CPU and DC.                               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module lsu(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall,
 
        // External i/f to DC
        dc_stall, dc_addr, dc_datain, dc_dataout, dc_lsuop
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `REGFILE_ADDR_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Internal i/f
//
input   [31:0]                   addrbase;
input   [31:0]                   addrofs;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
input   [dw-1:0]         lsu_datain;
output  [dw-1:0]         lsu_dataout;
output                          lsu_stall;
 
//
// External i/f to DC
//
input                           dc_stall;
output  [31:0]                   dc_addr;
input   [dw-1:0]         dc_datain;
output  [dw-1:0]         dc_dataout;
output  [`LSUOP_WIDTH-1:0]       dc_lsuop;
 
//
// Not much of a LSU right now
//
assign dc_addr = addrbase + addrofs;
assign dc_dataout = lsu_datain;
assign lsu_dataout = dc_datain;
assign lsu_stall = dc_stall;
assign dc_lsuop = lsu_op;
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Load/Store unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Interface between CPU and DC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.2 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	168	lampret	`//`
54	161	lampret
55	203	lampret	`// synopsys translate_off`
56	168	lampret	`include "timescale.v"
57	203	lampret	`// synopsys translate_on`
58	168	lampret	`include "defines.v"
59	161	lampret
60	168	lampret	`module lsu(`
61			`// Clock and reset`
62			`clk, rst,`
63	161	lampret
64	168	lampret	`// Internal i/f`
65			`addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall,`
66
67			`// External i/f to DC`
68			`dc_stall, dc_addr, dc_datain, dc_dataout, dc_lsuop`
69			`);`
70
71	161	lampret	parameter dw = `OPERAND_WIDTH;
72			parameter aw = `REGFILE_ADDR_WIDTH;
73
74	168	lampret	`//`
75			`// I/O`
76			`//`
77	161	lampret
78	168	lampret	`//`
79			`// Clock and reset`
80			`//`
81			`input clk;`
82			`input rst;`
83	161	lampret
84	168	lampret	`//`
85			`// Internal i/f`
86			`//`
87			`input [31:0] addrbase;`
88			`input [31:0] addrofs;`
89			input [`LSUOP_WIDTH-1:0] lsu_op;
90			`input [dw-1:0] lsu_datain;`
91			`output [dw-1:0] lsu_dataout;`
92			`output lsu_stall;`
93
94			`//`
95			`// External i/f to DC`
96			`//`
97			`input dc_stall;`
98			`output [31:0] dc_addr;`
99			`input [dw-1:0] dc_datain;`
100			`output [dw-1:0] dc_dataout;`
101			output [`LSUOP_WIDTH-1:0] dc_lsuop;
102
103			`//`
104			`// Not much of a LSU right now`
105			`//`
106	161	lampret	`assign dc_addr = addrbase + addrofs;`
107			`assign dc_dataout = lsu_datain;`
108			`assign lsu_dataout = dc_datain;`
109			`assign lsu_stall = dc_stall;`
110			`assign dc_lsuop = lsu_op;`
111
112			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [lsu.v] - Blame information for rev 203