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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// Faster implementation of mem2reg
//
`ifdef MEM2REG_FAST
 
`define SEL_00 2'b00
`define SEL_01 2'b01
`define SEL_10 2'b10
`define SEL_11 2'b11
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
reg     [1:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b01x, 2'b00}:
                        sel_byte0 <= #1 `SEL_11;
                {3'b01x, 2'b01}:
                        sel_byte0 <= #1 `SEL_10;
                {3'b01x, 2'b10}:
                        sel_byte0 <= #1 `SEL_01;
                {3'b01x, 2'b11}:
                        sel_byte0 <= #1 `SEL_00;
                {3'b10x, 2'b00}:
                        sel_byte0 <= #1 `SEL_10;
                {3'b10x, 2'b10}:
                        sel_byte0 <= #1 `SEL_00;
                default:
                        sel_byte0 <= #1 `SEL_00;
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx}:
                        sel_byte1 <= #1 `SEL_00;        // zero extend
                {3'b011, 2'bxx}:
                        sel_byte1 <= #1 `SEL_10;        // sign extend byte
                {3'b10x, 2'b00}:
                        sel_byte1 <= #1 `SEL_11;
                default:
                        sel_byte1 <= #1 `SEL_01;
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte2 <= #1 `SEL_00;        // zero extend
                {3'b011, 2'bxx}:
                        sel_byte2 <= #1 `SEL_01;        // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte2 <= #1 `SEL_11;        // sign extend halfword
                default:
                        sel_byte2 <= #1 `SEL_10;
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte3 <= #1 `SEL_00;        // zero extend
                {3'b011, 2'bxx}:
                        sel_byte3 <= #1 `SEL_01;        // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte3 <= #1 `SEL_10;        // sign extend halfword
                default:
                        sel_byte3 <= #1 `SEL_11;
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[7:0] <= #1 memdata[7:0];
                        end
                `SEL_01: begin
                                regdata[7:0] <= #1 memdata[15:8];
                        end
                `SEL_10: begin
                                regdata[7:0] <= #1 memdata[23:16];
                        end
                `SEL_11: begin
                                regdata[7:0] <= #1 memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[15:8] <= #1 8'b0;
                        end
                `SEL_01: begin
                                regdata[15:8] <= #1 memdata[15:8];
                        end
                `SEL_10: begin
                                regdata[15:8] <= #1 {8{memdata[7]}};
                        end
                `SEL_11: begin
                                regdata[15:8] <= #1 memdata[31:24];
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[23:16] <= #1 8'b0;
                        end
                `SEL_01: begin
                                regdata[23:16] <= #1 {8{memdata[7]}};
                        end
                `SEL_10: begin
                                regdata[23:16] <= #1 memdata[23:16];
                        end
                `SEL_11: begin
                                regdata[23:16] <= #1 {8{memdata[15]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[31:24] <= #1 8'b0;
                        end
                `SEL_01: begin
                                regdata[31:24] <= #1 {8{memdata[7]}};
                        end
                `SEL_10: begin
                                regdata[31:24] <= #1 {8{memdata[15]}};
                        end
                `SEL_11: begin
                                regdata[31:24] <= #1 memdata[31:24];
                        end
        endcase
end
 
`else
 
//
// Slow implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
        case(addr) // synopsys infer_mux
                2'b00:
                        aligned <= #1 memdata;
                2'b01:
                        aligned <= #1 {memdata[23:0], 8'b0};
                2'b10:
                        aligned <= #1 {memdata[15:0], 16'b0};
                2'b11:
                        aligned <= #1 {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
        case(lsu_op) // synopsys infer_mux
                `LSUOP_LBZ: begin
                                regdata[7:0] <= #1 aligned[31:24];
                                regdata[31:8] <= #1 24'b0;
                        end
                `LSUOP_LBS: begin
                                regdata[7:0] <= #1 aligned[31:24];
                                regdata[31:8] <= #1 {24{aligned[31]}};
                        end
                `LSUOP_LHZ: begin
                                regdata[15:0] <= #1 aligned[31:16];
                                regdata[31:16] <= #1 16'b0;
                        end
                `LSUOP_LHS: begin
                                regdata[15:0] <= #1 aligned[31:16];
                                regdata[31:16] <= #1 {16{aligned[31]}};
                        end
                default:
                                regdata <= #1 aligned;
        endcase
end
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	168	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
48			`// Development version of RTL. Libraries are missing.`
49	161	lampret	`//`
50	168	lampret	`//`
51	161	lampret
52	168	lampret	`include "timescale.v"
53			`include "defines.v"
54	161	lampret
55			`module mem2reg(addr, lsu_op, memdata, regdata);`
56
57			parameter width = `OPERAND_WIDTH;
58
59	168	lampret	`//`
60			`// I/O`
61			`//`
62			`input [1:0] addr;`
63			input [`LSUOP_WIDTH-1:0] lsu_op;
64			`input [width-1:0] memdata;`
65			`output [width-1:0] regdata;`
66	161	lampret
67
68	168	lampret	`//`
69			`// Faster implementation of mem2reg`
70			`//`
71	161	lampret	`ifdef MEM2REG_FAST
72
73			`define SEL_00 2'b00
74			`define SEL_01 2'b01
75			`define SEL_10 2'b10
76			`define SEL_11 2'b11
77
78	168	lampret	`reg [width-1:0] regdata;`
79			`reg [width-1:0] aligned;`
80			`reg [1:0] sel_byte0, sel_byte1,`
81			`sel_byte2, sel_byte3;`
82	161	lampret
83	168	lampret	`//`
84			`// Byte select 0`
85			`//`
86	161	lampret	`always @(addr or lsu_op) begin`
87			`casex({lsu_op[2:0], addr})`
88			`{3'b01x, 2'b00}:`
89			sel_byte0 <= #1 `SEL_11;
90			`{3'b01x, 2'b01}:`
91			sel_byte0 <= #1 `SEL_10;
92			`{3'b01x, 2'b10}:`
93			sel_byte0 <= #1 `SEL_01;
94			`{3'b01x, 2'b11}:`
95			sel_byte0 <= #1 `SEL_00;
96			`{3'b10x, 2'b00}:`
97			sel_byte0 <= #1 `SEL_10;
98			`{3'b10x, 2'b10}:`
99			sel_byte0 <= #1 `SEL_00;
100			`default:`
101			sel_byte0 <= #1 `SEL_00;
102			`endcase`
103			`end`
104
105	168	lampret	`//`
106			`// Byte select 1`
107			`//`
108	161	lampret	`always @(addr or lsu_op) begin`
109			`casex({lsu_op[2:0], addr})`
110			`{3'b010, 2'bxx}:`
111			sel_byte1 <= #1 `SEL_00; // zero extend
112			`{3'b011, 2'bxx}:`
113			sel_byte1 <= #1 `SEL_10; // sign extend byte
114			`{3'b10x, 2'b00}:`
115			sel_byte1 <= #1 `SEL_11;
116			`default:`
117			sel_byte1 <= #1 `SEL_01;
118			`endcase`
119			`end`
120
121	168	lampret	`//`
122			`// Byte select 2`
123			`//`
124	161	lampret	`always @(addr or lsu_op) begin`
125			`casex({lsu_op[2:0], addr})`
126			`{3'b010, 2'bxx},`
127			`{3'b100, 2'bxx}:`
128			sel_byte2 <= #1 `SEL_00; // zero extend
129			`{3'b011, 2'bxx}:`
130			sel_byte2 <= #1 `SEL_01; // sign extend byte
131			`{3'b101, 2'bxx}:`
132			sel_byte2 <= #1 `SEL_11; // sign extend halfword
133			`default:`
134			sel_byte2 <= #1 `SEL_10;
135			`endcase`
136			`end`
137
138	168	lampret	`//`
139			`// Byte select 3`
140			`//`
141	161	lampret	`always @(addr or lsu_op) begin`
142			`casex({lsu_op[2:0], addr})`
143			`{3'b010, 2'bxx},`
144			`{3'b100, 2'bxx}:`
145			sel_byte3 <= #1 `SEL_00; // zero extend
146			`{3'b011, 2'bxx}:`
147			sel_byte3 <= #1 `SEL_01; // sign extend byte
148			`{3'b101, 2'bxx}:`
149			sel_byte3 <= #1 `SEL_10; // sign extend halfword
150			`default:`
151			sel_byte3 <= #1 `SEL_11;
152			`endcase`
153			`end`
154
155	168	lampret	`//`
156			`// Byte 0`
157			`//`
158	161	lampret	`always @(sel_byte0 or memdata) begin`
159			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
160			`SEL_00: begin
161			`regdata[7:0] <= #1 memdata[7:0];`
162			`end`
163			`SEL_01: begin
164			`regdata[7:0] <= #1 memdata[15:8];`
165			`end`
166			`SEL_10: begin
167			`regdata[7:0] <= #1 memdata[23:16];`
168			`end`
169			`SEL_11: begin
170			`regdata[7:0] <= #1 memdata[31:24];`
171			`end`
172			`endcase`
173			`end`
174
175	168	lampret	`//`
176			`// Byte 1`
177			`//`
178	161	lampret	`always @(sel_byte1 or memdata) begin`
179			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
180			`SEL_00: begin
181			`regdata[15:8] <= #1 8'b0;`
182			`end`
183			`SEL_01: begin
184			`regdata[15:8] <= #1 memdata[15:8];`
185			`end`
186			`SEL_10: begin
187			`regdata[15:8] <= #1 {8{memdata[7]}};`
188			`end`
189			`SEL_11: begin
190			`regdata[15:8] <= #1 memdata[31:24];`
191			`end`
192			`endcase`
193			`end`
194
195	168	lampret	`//`
196			`// Byte 2`
197			`//`
198	161	lampret	`always @(sel_byte2 or memdata) begin`
199			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
200			`SEL_00: begin
201			`regdata[23:16] <= #1 8'b0;`
202			`end`
203			`SEL_01: begin
204			`regdata[23:16] <= #1 {8{memdata[7]}};`
205			`end`
206			`SEL_10: begin
207			`regdata[23:16] <= #1 memdata[23:16];`
208			`end`
209			`SEL_11: begin
210			`regdata[23:16] <= #1 {8{memdata[15]}};`
211			`end`
212			`endcase`
213			`end`
214
215	168	lampret	`//`
216			`// Byte 3`
217			`//`
218	161	lampret	`always @(sel_byte3 or memdata) begin`
219			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
220			`SEL_00: begin
221			`regdata[31:24] <= #1 8'b0;`
222			`end`
223			`SEL_01: begin
224			`regdata[31:24] <= #1 {8{memdata[7]}};`
225			`end`
226			`SEL_10: begin
227			`regdata[31:24] <= #1 {8{memdata[15]}};`
228			`end`
229			`SEL_11: begin
230			`regdata[31:24] <= #1 memdata[31:24];`
231			`end`
232			`endcase`
233			`end`
234
235			`else
236
237	168	lampret	`//`
238			`// Slow implementation of mem2reg`
239			`//`
240	161	lampret
241	168	lampret	`reg [width-1:0] regdata;`
242			`reg [width-1:0] aligned;`
243
244			`//`
245			`// Alignment`
246			`//`
247	161	lampret	`always @(addr or memdata) begin`
248			`case(addr) // synopsys infer_mux`
249			`2'b00:`
250			`aligned <= #1 memdata;`
251			`2'b01:`
252			`aligned <= #1 {memdata[23:0], 8'b0};`
253			`2'b10:`
254			`aligned <= #1 {memdata[15:0], 16'b0};`
255			`2'b11:`
256			`aligned <= #1 {memdata[7:0], 24'b0};`
257			`endcase`
258			`end`
259
260	168	lampret	`//`
261			`// Bytes`
262			`//`
263	161	lampret	`always @(lsu_op or aligned) begin`
264			`case(lsu_op) // synopsys infer_mux`
265			`LSUOP_LBZ: begin
266			`regdata[7:0] <= #1 aligned[31:24];`
267			`regdata[31:8] <= #1 24'b0;`
268			`end`
269			`LSUOP_LBS: begin
270			`regdata[7:0] <= #1 aligned[31:24];`
271			`regdata[31:8] <= #1 {24{aligned[31]}};`
272			`end`
273			`LSUOP_LHZ: begin
274			`regdata[15:0] <= #1 aligned[31:16];`
275			`regdata[31:16] <= #1 16'b0;`
276			`end`
277			`LSUOP_LHS: begin
278			`regdata[15:0] <= #1 aligned[31:16];`
279			`regdata[31:16] <= #1 {16{aligned[31]}};`
280			`end`
281			`default:`
282			`regdata <= #1 aligned;`
283			`endcase`
284			`end`
285
286			`endif
287
288			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [mem2reg.v] - Blame information for rev 168