URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [mem2reg.v] - Blame information for rev 1778

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// Faster implementation of mem2reg
//
`ifdef MEM2REG_FAST
 
`define SEL_00 2'b00
`define SEL_01 2'b01
`define SEL_10 2'b10
`define SEL_11 2'b11
 
reg     [7:0]                    regdata_hh;
reg     [7:0]                    regdata_hl;
reg     [7:0]                    regdata_lh;
reg     [7:0]                    regdata_ll;
reg     [width-1:0]              aligned;
reg     [1:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b01x, 2'b00}:
                        sel_byte0 = `SEL_11;
                {3'b01x, 2'b01}:
                        sel_byte0 = `SEL_10;
                {3'b01x, 2'b10}:
                        sel_byte0 = `SEL_01;
                {3'b01x, 2'b11}:
                        sel_byte0 = `SEL_00;
                {3'b10x, 2'b00}:
                        sel_byte0 = `SEL_10;
                {3'b10x, 2'b10}:
                        sel_byte0 = `SEL_00;
                default:
                        sel_byte0 = `SEL_00;
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx}:
                        sel_byte1 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte1 = `SEL_10;    // sign extend byte
                {3'b10x, 2'b00}:
                        sel_byte1 = `SEL_11;
                default:
                        sel_byte1 = `SEL_01;
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte2 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte2 = `SEL_01;    // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte2 = `SEL_11;    // sign extend halfword
                default:
                        sel_byte2 = `SEL_10;
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte3 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte3 = `SEL_01;    // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte3 = `SEL_10;    // sign extend halfword
                default:
                        sel_byte3 = `SEL_11;
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata_ll = memdata[7:0];
                        end
                `SEL_01: begin
                                regdata_ll = memdata[15:8];
                        end
                `SEL_10: begin
                                regdata_ll = memdata[23:16];
                        end
                `SEL_11: begin
                                regdata_ll = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata_lh = 8'b0;
                        end
                `SEL_01: begin
                                regdata_lh = memdata[15:8];
                        end
                `SEL_10: begin
                                regdata_lh = {8{memdata[7]}};
                        end
                `SEL_11: begin
                                regdata_lh = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata_hl = 8'b0;
                        end
                `SEL_01: begin
                                regdata_hl = {8{memdata[7]}};
                        end
                `SEL_10: begin
                                regdata_hl = memdata[23:16];
                        end
                `SEL_11: begin
                                regdata_hl = {8{memdata[15]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata_hh = 8'b0;
                        end
                `SEL_01: begin
                                regdata_hh = {8{memdata[7]}};
                        end
                `SEL_10: begin
                                regdata_hh = {8{memdata[15]}};
                        end
                `SEL_11: begin
                                regdata_hh = memdata[31:24];
                        end
        endcase
end
 
`else
 
//
// Slow implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
        case(addr) // synopsys infer_mux
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
        case(lsu_op) // synopsys infer_mux
                `LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [mem2reg.v] - Blame information for rev 1778

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	217	lampret	`// $Log: not supported by cvs2svn $`
47	218	lampret	`// Revision 1.8 2001/10/19 23:28:46 lampret`
48			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
49			`//`
50	217	lampret	`// Revision 1.7 2001/10/14 13:12:09 lampret`
51			`// MP3 version.`
52	218	lampret	`//`
53			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
54			`// no message`
55			`//`
56			`// Revision 1.2 2001/08/09 13:39:33 lampret`
57			`// Major clean-up.`
58			`//`
59			`// Revision 1.1 2001/07/20 00:46:03 lampret`
60			`// Development version of RTL. Libraries are missing.`
61			`//`
62			`//`
63	217	lampret
64	218	lampret	`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "defines.v"
68
69			`module mem2reg(addr, lsu_op, memdata, regdata);`
70
71			parameter width = `OPERAND_WIDTH;
72
73			`//`
74			`// I/O`
75			`//`
76			`input [1:0] addr;`
77			input [`LSUOP_WIDTH-1:0] lsu_op;
78			`input [width-1:0] memdata;`
79			`output [width-1:0] regdata;`
80
81
82			`//`
83			`// Faster implementation of mem2reg`
84			`//`
85			`ifdef MEM2REG_FAST
86
87			`define SEL_00 2'b00
88			`define SEL_01 2'b01
89			`define SEL_10 2'b10
90			`define SEL_11 2'b11
91
92			`reg [7:0] regdata_hh;`
93			`reg [7:0] regdata_hl;`
94			`reg [7:0] regdata_lh;`
95			`reg [7:0] regdata_ll;`
96			`reg [width-1:0] aligned;`
97			`reg [1:0] sel_byte0, sel_byte1,`
98			`sel_byte2, sel_byte3;`
99
100	217	lampret	`assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};`
101
102	218	lampret	`//`
103			`// Byte select 0`
104			`//`
105			`always @(addr or lsu_op) begin`
106			`casex({lsu_op[2:0], addr})`
107			`{3'b01x, 2'b00}:`
108			sel_byte0 = `SEL_11;
109			`{3'b01x, 2'b01}:`
110			sel_byte0 = `SEL_10;
111			`{3'b01x, 2'b10}:`
112			sel_byte0 = `SEL_01;
113			`{3'b01x, 2'b11}:`
114			sel_byte0 = `SEL_00;
115			`{3'b10x, 2'b00}:`
116			sel_byte0 = `SEL_10;
117			`{3'b10x, 2'b10}:`
118			sel_byte0 = `SEL_00;
119			`default:`
120			sel_byte0 = `SEL_00;
121			`endcase`
122			`end`
123
124			`//`
125			`// Byte select 1`
126			`//`
127			`always @(addr or lsu_op) begin`
128			`casex({lsu_op[2:0], addr})`
129			`{3'b010, 2'bxx}:`
130			sel_byte1 = `SEL_00; // zero extend
131			`{3'b011, 2'bxx}:`
132			sel_byte1 = `SEL_10; // sign extend byte
133			`{3'b10x, 2'b00}:`
134			sel_byte1 = `SEL_11;
135			`default:`
136			sel_byte1 = `SEL_01;
137			`endcase`
138			`end`
139
140			`//`
141			`// Byte select 2`
142			`//`
143			`always @(addr or lsu_op) begin`
144			`casex({lsu_op[2:0], addr})`
145			`{3'b010, 2'bxx},`
146			`{3'b100, 2'bxx}:`
147			sel_byte2 = `SEL_00; // zero extend
148			`{3'b011, 2'bxx}:`
149			sel_byte2 = `SEL_01; // sign extend byte
150			`{3'b101, 2'bxx}:`
151			sel_byte2 = `SEL_11; // sign extend halfword
152			`default:`
153			sel_byte2 = `SEL_10;
154			`endcase`
155			`end`
156
157			`//`
158			`// Byte select 3`
159			`//`
160			`always @(addr or lsu_op) begin`
161			`casex({lsu_op[2:0], addr})`
162			`{3'b010, 2'bxx},`
163			`{3'b100, 2'bxx}:`
164			sel_byte3 = `SEL_00; // zero extend
165			`{3'b011, 2'bxx}:`
166			sel_byte3 = `SEL_01; // sign extend byte
167			`{3'b101, 2'bxx}:`
168			sel_byte3 = `SEL_10; // sign extend halfword
169			`default:`
170			sel_byte3 = `SEL_11;
171			`endcase`
172			`end`
173
174			`//`
175			`// Byte 0`
176			`//`
177			`always @(sel_byte0 or memdata) begin`
178			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
179			`SEL_00: begin
180			`regdata_ll = memdata[7:0];`
181			`end`
182			`SEL_01: begin
183			`regdata_ll = memdata[15:8];`
184			`end`
185			`SEL_10: begin
186			`regdata_ll = memdata[23:16];`
187			`end`
188			`SEL_11: begin
189			`regdata_ll = memdata[31:24];`
190			`end`
191			`endcase`
192			`end`
193
194			`//`
195			`// Byte 1`
196			`//`
197			`always @(sel_byte1 or memdata) begin`
198			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
199			`SEL_00: begin
200			`regdata_lh = 8'b0;`
201			`end`
202			`SEL_01: begin
203			`regdata_lh = memdata[15:8];`
204			`end`
205			`SEL_10: begin
206			`regdata_lh = {8{memdata[7]}};`
207			`end`
208			`SEL_11: begin
209			`regdata_lh = memdata[31:24];`
210			`end`
211			`endcase`
212			`end`
213
214			`//`
215			`// Byte 2`
216			`//`
217			`always @(sel_byte2 or memdata) begin`
218			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
219			`SEL_00: begin
220			`regdata_hl = 8'b0;`
221			`end`
222			`SEL_01: begin
223			`regdata_hl = {8{memdata[7]}};`
224			`end`
225			`SEL_10: begin
226			`regdata_hl = memdata[23:16];`
227			`end`
228			`SEL_11: begin
229			`regdata_hl = {8{memdata[15]}};`
230			`end`
231			`endcase`
232			`end`
233
234			`//`
235			`// Byte 3`
236			`//`
237			`always @(sel_byte3 or memdata) begin`
238			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
239			`SEL_00: begin
240			`regdata_hh = 8'b0;`
241			`end`
242			`SEL_01: begin
243			`regdata_hh = {8{memdata[7]}};`
244			`end`
245			`SEL_10: begin
246			`regdata_hh = {8{memdata[15]}};`
247			`end`
248			`SEL_11: begin
249			`regdata_hh = memdata[31:24];`
250			`end`
251			`endcase`
252			`end`
253
254			`else
255
256			`//`
257			`// Slow implementation of mem2reg`
258			`//`
259
260			`reg [width-1:0] regdata;`
261			`reg [width-1:0] aligned;`
262
263			`//`
264			`// Alignment`
265			`//`
266			`always @(addr or memdata) begin`
267			`case(addr) // synopsys infer_mux`
268			`2'b00:`
269			`aligned = memdata;`
270			`2'b01:`
271			`aligned = {memdata[23:0], 8'b0};`
272			`2'b10:`
273			`aligned = {memdata[15:0], 16'b0};`
274			`2'b11:`
275			`aligned = {memdata[7:0], 24'b0};`
276			`endcase`
277			`end`
278
279			`//`
280			`// Bytes`
281			`//`
282			`always @(lsu_op or aligned) begin`
283			`case(lsu_op) // synopsys infer_mux`
284			`LSUOP_LBZ: begin
285			`regdata[7:0] = aligned[31:24];`
286			`regdata[31:8] = 24'b0;`
287			`end`
288			`LSUOP_LBS: begin
289			`regdata[7:0] = aligned[31:24];`
290			`regdata[31:8] = {24{aligned[31]}};`
291			`end`
292			`LSUOP_LHZ: begin
293			`regdata[15:0] = aligned[31:16];`
294			`regdata[31:16] = 16'b0;`
295			`end`
296			`LSUOP_LHS: begin
297			`regdata[15:0] = aligned[31:16];`
298			`regdata[31:16] = {16{aligned[31]}};`
299			`end`
300			`default:`
301			`regdata = aligned;`
302			`endcase`
303			`end`
304
305			`endif
306
307			`endmodule`