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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// Faster implementation of mem2reg
//
`ifdef MEM2REG_FAST
 
`define SEL_00 2'b00
`define SEL_01 2'b01
`define SEL_10 2'b10
`define SEL_11 2'b11
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
reg     [1:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b01x, 2'b00}:
                        sel_byte0 = `SEL_11;
                {3'b01x, 2'b01}:
                        sel_byte0 = `SEL_10;
                {3'b01x, 2'b10}:
                        sel_byte0 = `SEL_01;
                {3'b01x, 2'b11}:
                        sel_byte0 = `SEL_00;
                {3'b10x, 2'b00}:
                        sel_byte0 = `SEL_10;
                {3'b10x, 2'b10}:
                        sel_byte0 = `SEL_00;
                default:
                        sel_byte0 = `SEL_00;
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx}:
                        sel_byte1 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte1 = `SEL_10;    // sign extend byte
                {3'b10x, 2'b00}:
                        sel_byte1 = `SEL_11;
                default:
                        sel_byte1 = `SEL_01;
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte2 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte2 = `SEL_01;    // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte2 = `SEL_11;    // sign extend halfword
                default:
                        sel_byte2 = `SEL_10;
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})
                {3'b010, 2'bxx},
                {3'b100, 2'bxx}:
                        sel_byte3 = `SEL_00;    // zero extend
                {3'b011, 2'bxx}:
                        sel_byte3 = `SEL_01;    // sign extend byte
                {3'b101, 2'bxx}:
                        sel_byte3 = `SEL_10;    // sign extend halfword
                default:
                        sel_byte3 = `SEL_11;
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[7:0] = memdata[7:0];
                        end
                `SEL_01: begin
                                regdata[7:0] = memdata[15:8];
                        end
                `SEL_10: begin
                                regdata[7:0] = memdata[23:16];
                        end
                `SEL_11: begin
                                regdata[7:0] = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[15:8] = 8'b0;
                        end
                `SEL_01: begin
                                regdata[15:8] = memdata[15:8];
                        end
                `SEL_10: begin
                                regdata[15:8] = {8{memdata[7]}};
                        end
                `SEL_11: begin
                                regdata[15:8] = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[23:16] = 8'b0;
                        end
                `SEL_01: begin
                                regdata[23:16] = {8{memdata[7]}};
                        end
                `SEL_10: begin
                                regdata[23:16] = memdata[23:16];
                        end
                `SEL_11: begin
                                regdata[23:16] = {8{memdata[15]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
                `SEL_00: begin
                                regdata[31:24] = 8'b0;
                        end
                `SEL_01: begin
                                regdata[31:24] = {8{memdata[7]}};
                        end
                `SEL_10: begin
                                regdata[31:24] = {8{memdata[15]}};
                        end
                `SEL_11: begin
                                regdata[31:24] = memdata[31:24];
                        end
        endcase
end
 
`else
 
//
// Slow implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
        case(addr) // synopsys infer_mux
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
        case(lsu_op) // synopsys infer_mux
                `LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.2 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.1 2001/07/20 00:46:03 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	168	lampret	`//`
54	161	lampret
55	203	lampret	`// synopsys translate_off`
56	168	lampret	`include "timescale.v"
57	203	lampret	`// synopsys translate_on`
58	168	lampret	`include "defines.v"
59	161	lampret
60			`module mem2reg(addr, lsu_op, memdata, regdata);`
61
62			parameter width = `OPERAND_WIDTH;
63
64	168	lampret	`//`
65			`// I/O`
66			`//`
67			`input [1:0] addr;`
68			input [`LSUOP_WIDTH-1:0] lsu_op;
69			`input [width-1:0] memdata;`
70			`output [width-1:0] regdata;`
71	161	lampret
72
73	168	lampret	`//`
74			`// Faster implementation of mem2reg`
75			`//`
76	161	lampret	`ifdef MEM2REG_FAST
77
78			`define SEL_00 2'b00
79			`define SEL_01 2'b01
80			`define SEL_10 2'b10
81			`define SEL_11 2'b11
82
83	168	lampret	`reg [width-1:0] regdata;`
84			`reg [width-1:0] aligned;`
85			`reg [1:0] sel_byte0, sel_byte1,`
86			`sel_byte2, sel_byte3;`
87	161	lampret
88	168	lampret	`//`
89			`// Byte select 0`
90			`//`
91	161	lampret	`always @(addr or lsu_op) begin`
92			`casex({lsu_op[2:0], addr})`
93			`{3'b01x, 2'b00}:`
94	203	lampret	sel_byte0 = `SEL_11;
95	161	lampret	`{3'b01x, 2'b01}:`
96	203	lampret	sel_byte0 = `SEL_10;
97	161	lampret	`{3'b01x, 2'b10}:`
98	203	lampret	sel_byte0 = `SEL_01;
99	161	lampret	`{3'b01x, 2'b11}:`
100	203	lampret	sel_byte0 = `SEL_00;
101	161	lampret	`{3'b10x, 2'b00}:`
102	203	lampret	sel_byte0 = `SEL_10;
103	161	lampret	`{3'b10x, 2'b10}:`
104	203	lampret	sel_byte0 = `SEL_00;
105	161	lampret	`default:`
106	203	lampret	sel_byte0 = `SEL_00;
107	161	lampret	`endcase`
108			`end`
109
110	168	lampret	`//`
111			`// Byte select 1`
112			`//`
113	161	lampret	`always @(addr or lsu_op) begin`
114			`casex({lsu_op[2:0], addr})`
115			`{3'b010, 2'bxx}:`
116	203	lampret	sel_byte1 = `SEL_00; // zero extend
117	161	lampret	`{3'b011, 2'bxx}:`
118	203	lampret	sel_byte1 = `SEL_10; // sign extend byte
119	161	lampret	`{3'b10x, 2'b00}:`
120	203	lampret	sel_byte1 = `SEL_11;
121	161	lampret	`default:`
122	203	lampret	sel_byte1 = `SEL_01;
123	161	lampret	`endcase`
124			`end`
125
126	168	lampret	`//`
127			`// Byte select 2`
128			`//`
129	161	lampret	`always @(addr or lsu_op) begin`
130			`casex({lsu_op[2:0], addr})`
131			`{3'b010, 2'bxx},`
132			`{3'b100, 2'bxx}:`
133	203	lampret	sel_byte2 = `SEL_00; // zero extend
134	161	lampret	`{3'b011, 2'bxx}:`
135	203	lampret	sel_byte2 = `SEL_01; // sign extend byte
136	161	lampret	`{3'b101, 2'bxx}:`
137	203	lampret	sel_byte2 = `SEL_11; // sign extend halfword
138	161	lampret	`default:`
139	203	lampret	sel_byte2 = `SEL_10;
140	161	lampret	`endcase`
141			`end`
142
143	168	lampret	`//`
144			`// Byte select 3`
145			`//`
146	161	lampret	`always @(addr or lsu_op) begin`
147			`casex({lsu_op[2:0], addr})`
148			`{3'b010, 2'bxx},`
149			`{3'b100, 2'bxx}:`
150	203	lampret	sel_byte3 = `SEL_00; // zero extend
151	161	lampret	`{3'b011, 2'bxx}:`
152	203	lampret	sel_byte3 = `SEL_01; // sign extend byte
153	161	lampret	`{3'b101, 2'bxx}:`
154	203	lampret	sel_byte3 = `SEL_10; // sign extend halfword
155	161	lampret	`default:`
156	203	lampret	sel_byte3 = `SEL_11;
157	161	lampret	`endcase`
158			`end`
159
160	168	lampret	`//`
161			`// Byte 0`
162			`//`
163	161	lampret	`always @(sel_byte0 or memdata) begin`
164			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
165			`SEL_00: begin
166	203	lampret	`regdata[7:0] = memdata[7:0];`
167	161	lampret	`end`
168			`SEL_01: begin
169	203	lampret	`regdata[7:0] = memdata[15:8];`
170	161	lampret	`end`
171			`SEL_10: begin
172	203	lampret	`regdata[7:0] = memdata[23:16];`
173	161	lampret	`end`
174			`SEL_11: begin
175	203	lampret	`regdata[7:0] = memdata[31:24];`
176	161	lampret	`end`
177			`endcase`
178			`end`
179
180	168	lampret	`//`
181			`// Byte 1`
182			`//`
183	161	lampret	`always @(sel_byte1 or memdata) begin`
184			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
185			`SEL_00: begin
186	203	lampret	`regdata[15:8] = 8'b0;`
187	161	lampret	`end`
188			`SEL_01: begin
189	203	lampret	`regdata[15:8] = memdata[15:8];`
190	161	lampret	`end`
191			`SEL_10: begin
192	203	lampret	`regdata[15:8] = {8{memdata[7]}};`
193	161	lampret	`end`
194			`SEL_11: begin
195	203	lampret	`regdata[15:8] = memdata[31:24];`
196	161	lampret	`end`
197			`endcase`
198			`end`
199
200	168	lampret	`//`
201			`// Byte 2`
202			`//`
203	161	lampret	`always @(sel_byte2 or memdata) begin`
204			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
205			`SEL_00: begin
206	203	lampret	`regdata[23:16] = 8'b0;`
207	161	lampret	`end`
208			`SEL_01: begin
209	203	lampret	`regdata[23:16] = {8{memdata[7]}};`
210	161	lampret	`end`
211			`SEL_10: begin
212	203	lampret	`regdata[23:16] = memdata[23:16];`
213	161	lampret	`end`
214			`SEL_11: begin
215	203	lampret	`regdata[23:16] = {8{memdata[15]}};`
216	161	lampret	`end`
217			`endcase`
218			`end`
219
220	168	lampret	`//`
221			`// Byte 3`
222			`//`
223	161	lampret	`always @(sel_byte3 or memdata) begin`
224			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
225			`SEL_00: begin
226	203	lampret	`regdata[31:24] = 8'b0;`
227	161	lampret	`end`
228			`SEL_01: begin
229	203	lampret	`regdata[31:24] = {8{memdata[7]}};`
230	161	lampret	`end`
231			`SEL_10: begin
232	203	lampret	`regdata[31:24] = {8{memdata[15]}};`
233	161	lampret	`end`
234			`SEL_11: begin
235	203	lampret	`regdata[31:24] = memdata[31:24];`
236	161	lampret	`end`
237			`endcase`
238			`end`
239
240			`else
241
242	168	lampret	`//`
243			`// Slow implementation of mem2reg`
244			`//`
245	161	lampret
246	168	lampret	`reg [width-1:0] regdata;`
247			`reg [width-1:0] aligned;`
248
249			`//`
250			`// Alignment`
251			`//`
252	161	lampret	`always @(addr or memdata) begin`
253			`case(addr) // synopsys infer_mux`
254			`2'b00:`
255	203	lampret	`aligned = memdata;`
256	161	lampret	`2'b01:`
257	203	lampret	`aligned = {memdata[23:0], 8'b0};`
258	161	lampret	`2'b10:`
259	203	lampret	`aligned = {memdata[15:0], 16'b0};`
260	161	lampret	`2'b11:`
261	203	lampret	`aligned = {memdata[7:0], 24'b0};`
262	161	lampret	`endcase`
263			`end`
264
265	168	lampret	`//`
266			`// Bytes`
267			`//`
268	161	lampret	`always @(lsu_op or aligned) begin`
269			`case(lsu_op) // synopsys infer_mux`
270			`LSUOP_LBZ: begin
271	203	lampret	`regdata[7:0] = aligned[31:24];`
272			`regdata[31:8] = 24'b0;`
273	161	lampret	`end`
274			`LSUOP_LBS: begin
275	203	lampret	`regdata[7:0] = aligned[31:24];`
276			`regdata[31:8] = {24{aligned[31]}};`
277	161	lampret	`end`
278			`LSUOP_LHZ: begin
279	203	lampret	`regdata[15:0] = aligned[31:16];`
280			`regdata[31:16] = 16'b0;`
281	161	lampret	`end`
282			`LSUOP_LHS: begin
283	203	lampret	`regdata[15:0] = aligned[31:16];`
284			`regdata[31:16] = {16{aligned[31]}};`
285	161	lampret	`end`
286			`default:`
287	203	lampret	`regdata = aligned;`
288	161	lampret	`endcase`
289			`end`
290
291			`endif
292
293			`endmodule`

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