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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Top level multiplier and MAC                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Multiplier is 32x32 however multiply instructions only      ////
////  use lower 32 bits of the result. MAC is 32x32=64+64.        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module mult_mac(clk, rst, id_macrc_op, macrc_op, a, b, alu_op, result, mac_stall_r);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input                           clk;
input                           rst;
input                           id_macrc_op;
input                           macrc_op;
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [`ALUOP_WIDTH-1:0]       alu_op;
output  [width-1:0]              result;
output                          mac_stall_r;
 
//
// Internal wires and regs
//
wire    [width-1:0]              result;
reg     [2*width-1:0]            mul_prod_r;
reg     [2*width-1:0]            mac_r;
wire    [2*width-1:0]            mul_prod;
wire                            mac_op;
reg                             mac_op_r1;
reg                             mac_op_r2;
reg                             mac_op_r3;
reg                             mac_stall_r;
 
//
// Combinatorial logic
//
assign result = (alu_op == `ALUOP_MUL) ? mul_prod_r[31:0] : mac_r[59:28];
assign mac_op = (alu_op == `ALUOP_MAC);
 
//
// Instantiation of the multiplier
//
multp2_32x32 multp2_32x32(
        .X(a),
        .Y(b),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
 
//
// Registered output from the multiplier
//
always @(posedge rst or posedge clk)
        if (rst)
                mul_prod_r <= #1 64'h0000_0000_0000_0000;
        else
                mul_prod_r <= #1 mul_prod[63:0];
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r1 <= #1 1'b0;
        else
                mac_op_r1 <= #1 mac_op;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r2 <= #1 1'b0;
        else
                mac_op_r2 <= #1 mac_op_r1;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r3 <= #1 1'b0;
        else
                mac_op_r3 <= #1 mac_op_r2;
 
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_r <= #1 64'h0000_0000_0000_0000;
        else if (mac_op_r3)
                mac_r <= #1 mac_r + mul_prod_r;
        else if (macrc_op)
                mac_r <= #1 64'h0000_0000_0000_0000;
 
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_stall_r <= #1 1'b0;
        else
                mac_stall_r <= #1 (mac_op | mac_op_r1 | mac_op_r2) & id_macrc_op;
 
endmodule

Line No.	Rev	Author	Line
1	210	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Top level multiplier and MAC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Multiplier is 32x32 however multiply instructions only ////`
10			`//// use lower 32 bits of the result. MAC is 32x32=64+64. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`//`
49
50			`// synopsys translate_off`
51			`include "timescale.v"
52			`// synopsys translate_on`
53			`include "defines.v"
54
55			`module mult_mac(clk, rst, id_macrc_op, macrc_op, a, b, alu_op, result, mac_stall_r);`
56
57			parameter width = `OPERAND_WIDTH;
58
59			`//`
60			`// I/O`
61			`//`
62			`input clk;`
63			`input rst;`
64			`input id_macrc_op;`
65			`input macrc_op;`
66			`input [width-1:0] a;`
67			`input [width-1:0] b;`
68			input [`ALUOP_WIDTH-1:0] alu_op;
69			`output [width-1:0] result;`
70			`output mac_stall_r;`
71
72			`//`
73			`// Internal wires and regs`
74			`//`
75			`wire [width-1:0] result;`
76			`reg [2*width-1:0] mul_prod_r;`
77			`reg [2*width-1:0] mac_r;`
78			`wire [2*width-1:0] mul_prod;`
79			`wire mac_op;`
80			`reg mac_op_r1;`
81			`reg mac_op_r2;`
82			`reg mac_op_r3;`
83			`reg mac_stall_r;`
84
85			`//`
86			`// Combinatorial logic`
87			`//`
88			assign result = (alu_op == `ALUOP_MUL) ? mul_prod_r[31:0] : mac_r[59:28];
89			assign mac_op = (alu_op == `ALUOP_MAC);
90
91			`//`
92			`// Instantiation of the multiplier`
93			`//`
94			`multp2_32x32 multp2_32x32(`
95			`.X(a),`
96			`.Y(b),`
97			`.RST(rst),`
98			`.CLK(clk),`
99			`.P(mul_prod)`
100			`);`
101
102			`//`
103			`// Registered output from the multiplier`
104			`//`
105			`always @(posedge rst or posedge clk)`
106			`if (rst)`
107			`mul_prod_r <= #1 64'h0000_0000_0000_0000;`
108			`else`
109			`mul_prod_r <= #1 mul_prod[63:0];`
110
111			`//`
112			`// Propagation of l.mac opcode`
113			`//`
114			`always @(posedge clk or posedge rst)`
115			`if (rst)`
116			`mac_op_r1 <= #1 1'b0;`
117			`else`
118			`mac_op_r1 <= #1 mac_op;`
119
120			`//`
121			`// Propagation of l.mac opcode`
122			`//`
123			`always @(posedge clk or posedge rst)`
124			`if (rst)`
125			`mac_op_r2 <= #1 1'b0;`
126			`else`
127			`mac_op_r2 <= #1 mac_op_r1;`
128
129			`//`
130			`// Propagation of l.mac opcode`
131			`//`
132			`always @(posedge clk or posedge rst)`
133			`if (rst)`
134			`mac_op_r3 <= #1 1'b0;`
135			`else`
136			`mac_op_r3 <= #1 mac_op_r2;`
137
138			`//`
139			`// Implementation of MAC`
140			`//`
141			`always @(posedge rst or posedge clk)`
142			`if (rst)`
143			`mac_r <= #1 64'h0000_0000_0000_0000;`
144			`else if (mac_op_r3)`
145			`mac_r <= #1 mac_r + mul_prod_r;`
146			`else if (macrc_op)`
147			`mac_r <= #1 64'h0000_0000_0000_0000;`
148
149			`//`
150			`// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions`
151			`// in EX stage (e.g. inside multiplier)`
152			`//`
153			`always @(posedge rst or posedge clk)`
154			`if (rst)`
155			`mac_stall_r <= #1 1'b0;`
156			`else`
157			`mac_stall_r <= #1 (mac_op \| mac_op_r1 \| mac_op_r2) & id_macrc_op;`
158
159			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [mult_mac.v] - Blame information for rev 210