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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file read operands mux                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Mux for two register file read operands.                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/20 00:46:05  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module operandmuxes(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        pipeline_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
        simm, sel_a, sel_b, operand_a, operand_b, muxed_b
);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input                           clk;
input                           rst;
input                           pipeline_freeze;
input   [width-1:0]              rf_dataa;
input   [width-1:0]              rf_datab;
input   [width-1:0]              ex_forw;
input   [width-1:0]              wb_forw;
input   [width-1:0]              simm;
input   [`SEL_WIDTH-1:0] sel_a;
input   [`SEL_WIDTH-1:0] sel_b;
output  [width-1:0]              operand_a;
output  [width-1:0]              operand_b;
output  [width-1:0]              muxed_b;
 
//
// Internal wires and regs
//
reg     [width-1:0]              operand_a;
reg     [width-1:0]              operand_b;
reg     [width-1:0]              muxed_a;
reg     [width-1:0]              muxed_b;
 
//
// Operand A register
//
always @(posedge clk or posedge rst) begin
        if (rst)
                operand_a <= #1 32'd0;
        else if (!pipeline_freeze)
                operand_a <= #1 muxed_a;
end
 
//
// Operand B register
//
always @(posedge clk or posedge rst) begin
        if (rst)
                operand_b <= #1 32'd0;
        else if (!pipeline_freeze)
                operand_b <= #1 muxed_b;
end
 
//
// Forwarding logic for operand A register
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
        casex (sel_a)   // synopsys full_case parallel_case infer_mux
                `SEL_EX_FORW:
                        muxed_a <= #1 ex_forw;
                `SEL_WB_FORW:
                        muxed_a <= #1 wb_forw;
                default:
                        muxed_a <= #1 rf_dataa;
        endcase
end
 
//
// Forwarding logic for operand B register
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
        casex (sel_b)   // synopsys full_case parallel_case infer_mux
                `SEL_IMM:
                        muxed_b <= #1 simm;
                `SEL_EX_FORW:
                        muxed_b <= #1 ex_forw;
                `SEL_WB_FORW:
                        muxed_b <= #1 wb_forw;
                default:
                        muxed_b <= #1 rf_datab;
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file read operands mux ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Mux for two register file read operands. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	168	lampret	`// Revision 1.1 2001/07/20 00:46:05 lampret`
48			`// Development version of RTL. Libraries are missing.`
49	161	lampret	`//`
50	168	lampret	`//`
51	161	lampret
52	168	lampret	`include "timescale.v"
53			`include "defines.v"
54	161	lampret
55	168	lampret	`module operandmuxes(`
56			`// Clock and reset`
57			`clk, rst,`
58	161	lampret
59	168	lampret	`// Internal i/f`
60			`pipeline_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,`
61			`simm, sel_a, sel_b, operand_a, operand_b, muxed_b`
62			`);`
63
64	161	lampret	parameter width = `OPERAND_WIDTH;
65
66	168	lampret	`//`
67			`// I/O`
68			`//`
69			`input clk;`
70			`input rst;`
71			`input pipeline_freeze;`
72			`input [width-1:0] rf_dataa;`
73			`input [width-1:0] rf_datab;`
74			`input [width-1:0] ex_forw;`
75			`input [width-1:0] wb_forw;`
76			`input [width-1:0] simm;`
77			input [`SEL_WIDTH-1:0] sel_a;
78			input [`SEL_WIDTH-1:0] sel_b;
79			`output [width-1:0] operand_a;`
80			`output [width-1:0] operand_b;`
81			`output [width-1:0] muxed_b;`
82	161	lampret
83	168	lampret	`//`
84			`// Internal wires and regs`
85			`//`
86			`reg [width-1:0] operand_a;`
87			`reg [width-1:0] operand_b;`
88			`reg [width-1:0] muxed_a;`
89			`reg [width-1:0] muxed_b;`
90	161	lampret
91	168	lampret	`//`
92			`// Operand A register`
93			`//`
94	161	lampret	`always @(posedge clk or posedge rst) begin`
95			`if (rst)`
96			`operand_a <= #1 32'd0;`
97			`else if (!pipeline_freeze)`
98			`operand_a <= #1 muxed_a;`
99			`end`
100
101	168	lampret	`//`
102			`// Operand B register`
103			`//`
104	161	lampret	`always @(posedge clk or posedge rst) begin`
105			`if (rst)`
106			`operand_b <= #1 32'd0;`
107			`else if (!pipeline_freeze)`
108			`operand_b <= #1 muxed_b;`
109			`end`
110
111	168	lampret	`//`
112			`// Forwarding logic for operand A register`
113			`//`
114	161	lampret	`always @(ex_forw or wb_forw or rf_dataa or sel_a) begin`
115			`casex (sel_a) // synopsys full_case parallel_case infer_mux`
116			`SEL_EX_FORW:
117			`muxed_a <= #1 ex_forw;`
118			`SEL_WB_FORW:
119			`muxed_a <= #1 wb_forw;`
120			`default:`
121			`muxed_a <= #1 rf_dataa;`
122			`endcase`
123			`end`
124
125	168	lampret	`//`
126			`// Forwarding logic for operand B register`
127			`//`
128	161	lampret	`always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin`
129			`casex (sel_b) // synopsys full_case parallel_case infer_mux`
130			`SEL_IMM:
131			`muxed_b <= #1 simm;`
132			`SEL_EX_FORW:
133			`muxed_b <= #1 ex_forw;`
134			`SEL_WB_FORW:
135			`muxed_b <= #1 wb_forw;`
136			`default:`
137			`muxed_b <= #1 rf_datab;`
138			`endcase`
139			`end`
140
141			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [operandmuxes.v] - Blame information for rev 168